]> bbs.cooldavid.org Git - jme.git/blame_incremental - jme.c
git://bbs.cooldavid.org / jme.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Import jme 1.0.4-backport source
[jme.git] / jme.c
... / ...
CommitLineData
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/mii.h>
31#include <linux/crc32.h>
32#include <linux/delay.h>
33#include <linux/spinlock.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/if_vlan.h>
40#include <net/ip6_checksum.h>
41#include "jme.h"
42
43static int force_pseudohp = -1;
44static int no_pseudohp = -1;
45static int no_extplug = -1;
46module_param(force_pseudohp, int, 0);
47MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49module_param(no_pseudohp, int, 0);
50MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51module_param(no_extplug, int, 0);
52MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55static int
56jme_mdio_read(struct net_device *netdev, int phy, int reg)
57{
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83}
84
85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107}
108
109static inline void
110jme_reset_phy_processor(struct jme_adapter *jme)
111{
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134}
135
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
162
163static inline void
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194}
195
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
204jme_clear_pm(struct jme_adapter *jme)
205{
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209}
210
211static int
212jme_reload_eeprom(struct jme_adapter *jme)
213{
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239}
240
241static void
242jme_load_macaddr(struct net_device *netdev)
243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259}
260
261static inline void
262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292}
293
294static void
295jme_start_irq(struct jme_adapter *jme)
296{
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
316static inline void
317jme_stop_irq(struct jme_adapter *jme)
318{
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323}
324
325static inline void
326jme_enable_shadow(struct jme_adapter *jme)
327{
328 jwrite32(jme,
329 JME_SHBA_LO,
330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
331}
332
333static inline void
334jme_disable_shadow(struct jme_adapter *jme)
335{
336 jwrite32(jme, JME_SHBA_LO, 0x0);
337}
338
339static u32
340jme_linkstat_from_phy(struct jme_adapter *jme)
341{
342 u32 phylink, bmsr;
343
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346 if (bmsr & BMSR_ANCOMP)
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
348
349 return phylink;
350}
351
352static inline void
353jme_set_phyfifoa(struct jme_adapter *jme)
354{
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
356}
357
358static inline void
359jme_set_phyfifob(struct jme_adapter *jme)
360{
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
362}
363
364static int
365jme_check_link(struct net_device *netdev, int testonly)
366{
367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
369 char linkmsg[64];
370 int rc = 0;
371
372 linkmsg[0] = '\0';
373
374 if (jme->fpgaver)
375 phylink = jme_linkstat_from_phy(jme);
376 else
377 phylink = jread32(jme, JME_PHY_LINK);
378
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
381 /*
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
384 */
385 phylink = PHY_LINK_UP;
386
387 bmcr = jme_mdio_read(jme->dev,
388 jme->mii_if.phy_id,
389 MII_BMCR);
390
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
396 PHY_LINK_SPEED_10M;
397
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
399 PHY_LINK_DUPLEX : 0;
400
401 strcat(linkmsg, "Forced: ");
402 } else {
403 /*
404 * Keep polling for speed/duplex resolve complete
405 */
406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
407 --cnt) {
408
409 udelay(1);
410
411 if (jme->fpgaver)
412 phylink = jme_linkstat_from_phy(jme);
413 else
414 phylink = jread32(jme, JME_PHY_LINK);
415 }
416 if (!cnt)
417 jeprintk(jme->pdev,
418 "Waiting speed resolve timeout.\n");
419
420 strcat(linkmsg, "ANed: ");
421 }
422
423 if (jme->phylink == phylink) {
424 rc = 1;
425 goto out;
426 }
427 if (testonly)
428 goto out;
429
430 jme->phylink = phylink;
431
432 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
433 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
435 switch (phylink & PHY_LINK_SPEED_MASK) {
436 case PHY_LINK_SPEED_10M:
437 ghc |= GHC_SPEED_10M |
438 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
439 strcat(linkmsg, "10 Mbps, ");
440 break;
441 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M |
443 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
444 strcat(linkmsg, "100 Mbps, ");
445 break;
446 case PHY_LINK_SPEED_1000M:
447 ghc |= GHC_SPEED_1000M |
448 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
449 strcat(linkmsg, "1000 Mbps, ");
450 break;
451 default:
452 break;
453 }
454
455 if (phylink & PHY_LINK_DUPLEX) {
456 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
457 ghc |= GHC_DPX;
458 } else {
459 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
460 TXMCS_BACKOFF |
461 TXMCS_CARRIERSENSE |
462 TXMCS_COLLISION);
463 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
464 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
465 TXTRHD_TXREN |
466 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
467 }
468
469 gpreg1 = GPREG1_DEFAULT;
470 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
471 if (!(phylink & PHY_LINK_DUPLEX))
472 gpreg1 |= GPREG1_HALFMODEPATCH;
473 switch (phylink & PHY_LINK_SPEED_MASK) {
474 case PHY_LINK_SPEED_10M:
475 jme_set_phyfifoa(jme);
476 gpreg1 |= GPREG1_RSSPATCH;
477 break;
478 case PHY_LINK_SPEED_100M:
479 jme_set_phyfifob(jme);
480 gpreg1 |= GPREG1_RSSPATCH;
481 break;
482 case PHY_LINK_SPEED_1000M:
483 jme_set_phyfifoa(jme);
484 break;
485 default:
486 break;
487 }
488 }
489
490 jwrite32(jme, JME_GPREG1, gpreg1);
491 jwrite32(jme, JME_GHC, ghc);
492 jme->reg_ghc = ghc;
493
494 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
495 "Full-Duplex, " :
496 "Half-Duplex, ");
497 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
498 "MDI-X" :
499 "MDI");
500 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev);
502 } else {
503 if (testonly)
504 goto out;
505
506 msg_link(jme, "Link is down.\n");
507 jme->phylink = 0;
508 netif_carrier_off(netdev);
509 }
510
511out:
512 return rc;
513}
514
515static int
516jme_setup_tx_resources(struct jme_adapter *jme)
517{
518 struct jme_ring *txring = &(jme->txring[0]);
519
520 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
521 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
522 &(txring->dmaalloc),
523 GFP_ATOMIC);
524
525 if (!txring->alloc) {
526 txring->desc = NULL;
527 txring->dmaalloc = 0;
528 txring->dma = 0;
529 return -ENOMEM;
530 }
531
532 /*
533 * 16 Bytes align
534 */
535 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
536 RING_DESC_ALIGN);
537 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
538 txring->next_to_use = 0;
539 atomic_set(&txring->next_to_clean, 0);
540 atomic_set(&txring->nr_free, jme->tx_ring_size);
541
542 /*
543 * Initialize Transmit Descriptors
544 */
545 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
546 memset(txring->bufinf, 0,
547 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
548
549 return 0;
550}
551
552static void
553jme_free_tx_resources(struct jme_adapter *jme)
554{
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi = txring->bufinf;
558
559 if (txring->alloc) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
562 if (txbi->skb) {
563 dev_kfree_skb(txbi->skb);
564 txbi->skb = NULL;
565 }
566 txbi->mapping = 0;
567 txbi->len = 0;
568 txbi->nr_desc = 0;
569 txbi->start_xmit = 0;
570 }
571
572 dma_free_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
574 txring->alloc,
575 txring->dmaalloc);
576
577 txring->alloc = NULL;
578 txring->desc = NULL;
579 txring->dmaalloc = 0;
580 txring->dma = 0;
581 }
582 txring->next_to_use = 0;
583 atomic_set(&txring->next_to_clean, 0);
584 atomic_set(&txring->nr_free, 0);
585
586}
587
588static inline void
589jme_enable_tx_engine(struct jme_adapter *jme)
590{
591 /*
592 * Select Queue 0
593 */
594 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
595 wmb();
596
597 /*
598 * Setup TX Queue 0 DMA Bass Address
599 */
600 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
601 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
602 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
603
604 /*
605 * Setup TX Descptor Count
606 */
607 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
608
609 /*
610 * Enable TX Engine
611 */
612 wmb();
613 jwrite32(jme, JME_TXCS, jme->reg_txcs |
614 TXCS_SELECT_QUEUE0 |
615 TXCS_ENABLE);
616
617}
618
619static inline void
620jme_restart_tx_engine(struct jme_adapter *jme)
621{
622 /*
623 * Restart TX Engine
624 */
625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
626 TXCS_SELECT_QUEUE0 |
627 TXCS_ENABLE);
628}
629
630static inline void
631jme_disable_tx_engine(struct jme_adapter *jme)
632{
633 int i;
634 u32 val;
635
636 /*
637 * Disable TX Engine
638 */
639 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
640 wmb();
641
642 val = jread32(jme, JME_TXCS);
643 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
644 mdelay(1);
645 val = jread32(jme, JME_TXCS);
646 rmb();
647 }
648
649 if (!i)
650 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
651}
652
653static void
654jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
655{
656 struct jme_ring *rxring = jme->rxring;
657 register struct rxdesc *rxdesc = rxring->desc;
658 struct jme_buffer_info *rxbi = rxring->bufinf;
659 rxdesc += i;
660 rxbi += i;
661
662 rxdesc->dw[0] = 0;
663 rxdesc->dw[1] = 0;
664 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
665 rxdesc->desc1.bufaddrl = cpu_to_le32(
666 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
667 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
668 if (jme->dev->features & NETIF_F_HIGHDMA)
669 rxdesc->desc1.flags = RXFLAG_64BIT;
670 wmb();
671 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
672}
673
674static int
675jme_make_new_rx_buf(struct jme_adapter *jme, int i)
676{
677 struct jme_ring *rxring = &(jme->rxring[0]);
678 struct jme_buffer_info *rxbi = rxring->bufinf + i;
679 struct sk_buff *skb;
680
681 skb = netdev_alloc_skb(jme->dev,
682 jme->dev->mtu + RX_EXTRA_LEN);
683 if (unlikely(!skb))
684 return -ENOMEM;
685#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
686 skb->dev = jme->dev;
687#endif
688
689 rxbi->skb = skb;
690 rxbi->len = skb_tailroom(skb);
691 rxbi->mapping = pci_map_page(jme->pdev,
692 virt_to_page(skb->data),
693 offset_in_page(skb->data),
694 rxbi->len,
695 PCI_DMA_FROMDEVICE);
696
697 return 0;
698}
699
700static void
701jme_free_rx_buf(struct jme_adapter *jme, int i)
702{
703 struct jme_ring *rxring = &(jme->rxring[0]);
704 struct jme_buffer_info *rxbi = rxring->bufinf;
705 rxbi += i;
706
707 if (rxbi->skb) {
708 pci_unmap_page(jme->pdev,
709 rxbi->mapping,
710 rxbi->len,
711 PCI_DMA_FROMDEVICE);
712 dev_kfree_skb(rxbi->skb);
713 rxbi->skb = NULL;
714 rxbi->mapping = 0;
715 rxbi->len = 0;
716 }
717}
718
719static void
720jme_free_rx_resources(struct jme_adapter *jme)
721{
722 int i;
723 struct jme_ring *rxring = &(jme->rxring[0]);
724
725 if (rxring->alloc) {
726 for (i = 0 ; i < jme->rx_ring_size ; ++i)
727 jme_free_rx_buf(jme, i);
728
729 dma_free_coherent(&(jme->pdev->dev),
730 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
731 rxring->alloc,
732 rxring->dmaalloc);
733 rxring->alloc = NULL;
734 rxring->desc = NULL;
735 rxring->dmaalloc = 0;
736 rxring->dma = 0;
737 }
738 rxring->next_to_use = 0;
739 atomic_set(&rxring->next_to_clean, 0);
740}
741
742static int
743jme_setup_rx_resources(struct jme_adapter *jme)
744{
745 int i;
746 struct jme_ring *rxring = &(jme->rxring[0]);
747
748 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
749 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
750 &(rxring->dmaalloc),
751 GFP_ATOMIC);
752 if (!rxring->alloc) {
753 rxring->desc = NULL;
754 rxring->dmaalloc = 0;
755 rxring->dma = 0;
756 return -ENOMEM;
757 }
758
759 /*
760 * 16 Bytes align
761 */
762 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
763 RING_DESC_ALIGN);
764 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
765 rxring->next_to_use = 0;
766 atomic_set(&rxring->next_to_clean, 0);
767
768 /*
769 * Initiallize Receive Descriptors
770 */
771 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
772 if (unlikely(jme_make_new_rx_buf(jme, i))) {
773 jme_free_rx_resources(jme);
774 return -ENOMEM;
775 }
776
777 jme_set_clean_rxdesc(jme, i);
778 }
779
780 return 0;
781}
782
783static inline void
784jme_enable_rx_engine(struct jme_adapter *jme)
785{
786 /*
787 * Select Queue 0
788 */
789 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
790 RXCS_QUEUESEL_Q0);
791 wmb();
792
793 /*
794 * Setup RX DMA Bass Address
795 */
796 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
797 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
798 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
799
800 /*
801 * Setup RX Descriptor Count
802 */
803 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
804
805 /*
806 * Setup Unicast Filter
807 */
808 jme_set_multi(jme->dev);
809
810 /*
811 * Enable RX Engine
812 */
813 wmb();
814 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
815 RXCS_QUEUESEL_Q0 |
816 RXCS_ENABLE |
817 RXCS_QST);
818}
819
820static inline void
821jme_restart_rx_engine(struct jme_adapter *jme)
822{
823 /*
824 * Start RX Engine
825 */
826 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
827 RXCS_QUEUESEL_Q0 |
828 RXCS_ENABLE |
829 RXCS_QST);
830}
831
832static inline void
833jme_disable_rx_engine(struct jme_adapter *jme)
834{
835 int i;
836 u32 val;
837
838 /*
839 * Disable RX Engine
840 */
841 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
842 wmb();
843
844 val = jread32(jme, JME_RXCS);
845 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
846 mdelay(1);
847 val = jread32(jme, JME_RXCS);
848 rmb();
849 }
850
851 if (!i)
852 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
853
854}
855
856static int
857jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
858{
859 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
860 return false;
861
862 if (unlikely(!(flags & RXWBFLAG_MF) &&
863 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
864 msg_rx_err(jme, "TCP Checksum error.\n");
865 goto out_sumerr;
866 }
867
868 if (unlikely(!(flags & RXWBFLAG_MF) &&
869 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
870 msg_rx_err(jme, "UDP Checksum error.\n");
871 goto out_sumerr;
872 }
873
874 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
875 msg_rx_err(jme, "IPv4 Checksum error.\n");
876 goto out_sumerr;
877 }
878
879 return true;
880
881out_sumerr:
882 return false;
883}
884
885static void
886jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
887{
888 struct jme_ring *rxring = &(jme->rxring[0]);
889 struct rxdesc *rxdesc = rxring->desc;
890 struct jme_buffer_info *rxbi = rxring->bufinf;
891 struct sk_buff *skb;
892 int framesize;
893
894 rxdesc += idx;
895 rxbi += idx;
896
897 skb = rxbi->skb;
898 pci_dma_sync_single_for_cpu(jme->pdev,
899 rxbi->mapping,
900 rxbi->len,
901 PCI_DMA_FROMDEVICE);
902
903 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
904 pci_dma_sync_single_for_device(jme->pdev,
905 rxbi->mapping,
906 rxbi->len,
907 PCI_DMA_FROMDEVICE);
908
909 ++(NET_STAT(jme).rx_dropped);
910 } else {
911 framesize = le16_to_cpu(rxdesc->descwb.framesize)
912 - RX_PREPAD_SIZE;
913
914 skb_reserve(skb, RX_PREPAD_SIZE);
915 skb_put(skb, framesize);
916 skb->protocol = eth_type_trans(skb, jme->dev);
917
918 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
919 skb->ip_summed = CHECKSUM_UNNECESSARY;
920 else
921 skb->ip_summed = CHECKSUM_NONE;
922
923 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
924 if (jme->vlgrp) {
925 jme->jme_vlan_rx(skb, jme->vlgrp,
926 le16_to_cpu(rxdesc->descwb.vlan));
927 NET_STAT(jme).rx_bytes += 4;
928 }
929 } else {
930 jme->jme_rx(skb);
931 }
932
933 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
934 cpu_to_le16(RXWBFLAG_DEST_MUL))
935 ++(NET_STAT(jme).multicast);
936
937 NET_STAT(jme).rx_bytes += framesize;
938 ++(NET_STAT(jme).rx_packets);
939 }
940
941 jme_set_clean_rxdesc(jme, idx);
942
943}
944
945static int
946jme_process_receive(struct jme_adapter *jme, int limit)
947{
948 struct jme_ring *rxring = &(jme->rxring[0]);
949 struct rxdesc *rxdesc = rxring->desc;
950 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
951
952 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
953 goto out_inc;
954
955 if (unlikely(atomic_read(&jme->link_changing) != 1))
956 goto out_inc;
957
958 if (unlikely(!netif_carrier_ok(jme->dev)))
959 goto out_inc;
960
961 i = atomic_read(&rxring->next_to_clean);
962 while (limit-- > 0) {
963 rxdesc = rxring->desc;
964 rxdesc += i;
965
966 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
967 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
968 goto out;
969
970 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
971
972 if (unlikely(desccnt > 1 ||
973 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
974
975 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
976 ++(NET_STAT(jme).rx_crc_errors);
977 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
978 ++(NET_STAT(jme).rx_fifo_errors);
979 else
980 ++(NET_STAT(jme).rx_errors);
981
982 if (desccnt > 1)
983 limit -= desccnt - 1;
984
985 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
986 jme_set_clean_rxdesc(jme, j);
987 j = (j + 1) & (mask);
988 }
989
990 } else {
991 jme_alloc_and_feed_skb(jme, i);
992 }
993
994 i = (i + desccnt) & (mask);
995 }
996
997out:
998 atomic_set(&rxring->next_to_clean, i);
999
1000out_inc:
1001 atomic_inc(&jme->rx_cleaning);
1002
1003 return limit > 0 ? limit : 0;
1004
1005}
1006
1007static void
1008jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1009{
1010 if (likely(atmp == dpi->cur)) {
1011 dpi->cnt = 0;
1012 return;
1013 }
1014
1015 if (dpi->attempt == atmp) {
1016 ++(dpi->cnt);
1017 } else {
1018 dpi->attempt = atmp;
1019 dpi->cnt = 0;
1020 }
1021
1022}
1023
1024static void
1025jme_dynamic_pcc(struct jme_adapter *jme)
1026{
1027 register struct dynpcc_info *dpi = &(jme->dpi);
1028
1029 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1030 jme_attempt_pcc(dpi, PCC_P3);
1031 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1032 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1033 jme_attempt_pcc(dpi, PCC_P2);
1034 else
1035 jme_attempt_pcc(dpi, PCC_P1);
1036
1037 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1038 if (dpi->attempt < dpi->cur)
1039 tasklet_schedule(&jme->rxclean_task);
1040 jme_set_rx_pcc(jme, dpi->attempt);
1041 dpi->cur = dpi->attempt;
1042 dpi->cnt = 0;
1043 }
1044}
1045
1046static void
1047jme_start_pcc_timer(struct jme_adapter *jme)
1048{
1049 struct dynpcc_info *dpi = &(jme->dpi);
1050 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1051 dpi->last_pkts = NET_STAT(jme).rx_packets;
1052 dpi->intr_cnt = 0;
1053 jwrite32(jme, JME_TMCSR,
1054 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1055}
1056
1057static inline void
1058jme_stop_pcc_timer(struct jme_adapter *jme)
1059{
1060 jwrite32(jme, JME_TMCSR, 0);
1061}
1062
1063static void
1064jme_shutdown_nic(struct jme_adapter *jme)
1065{
1066 u32 phylink;
1067
1068 phylink = jme_linkstat_from_phy(jme);
1069
1070 if (!(phylink & PHY_LINK_UP)) {
1071 /*
1072 * Disable all interrupt before issue timer
1073 */
1074 jme_stop_irq(jme);
1075 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1076 }
1077}
1078
1079static void
1080jme_pcc_tasklet(unsigned long arg)
1081{
1082 struct jme_adapter *jme = (struct jme_adapter *)arg;
1083 struct net_device *netdev = jme->dev;
1084
1085 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1086 jme_shutdown_nic(jme);
1087 return;
1088 }
1089
1090 if (unlikely(!netif_carrier_ok(netdev) ||
1091 (atomic_read(&jme->link_changing) != 1)
1092 )) {
1093 jme_stop_pcc_timer(jme);
1094 return;
1095 }
1096
1097 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1098 jme_dynamic_pcc(jme);
1099
1100 jme_start_pcc_timer(jme);
1101}
1102
1103static inline void
1104jme_polling_mode(struct jme_adapter *jme)
1105{
1106 jme_set_rx_pcc(jme, PCC_OFF);
1107}
1108
1109static inline void
1110jme_interrupt_mode(struct jme_adapter *jme)
1111{
1112 jme_set_rx_pcc(jme, PCC_P1);
1113}
1114
1115static inline int
1116jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1117{
1118 u32 apmc;
1119 apmc = jread32(jme, JME_APMC);
1120 return apmc & JME_APMC_PSEUDO_HP_EN;
1121}
1122
1123static void
1124jme_start_shutdown_timer(struct jme_adapter *jme)
1125{
1126 u32 apmc;
1127
1128 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1129 apmc &= ~JME_APMC_EPIEN_CTRL;
1130 if (!no_extplug) {
1131 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1132 wmb();
1133 }
1134 jwrite32f(jme, JME_APMC, apmc);
1135
1136 jwrite32f(jme, JME_TIMER2, 0);
1137 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1138 jwrite32(jme, JME_TMCSR,
1139 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1140}
1141
1142static void
1143jme_stop_shutdown_timer(struct jme_adapter *jme)
1144{
1145 u32 apmc;
1146
1147 jwrite32f(jme, JME_TMCSR, 0);
1148 jwrite32f(jme, JME_TIMER2, 0);
1149 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1150
1151 apmc = jread32(jme, JME_APMC);
1152 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1153 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1154 wmb();
1155 jwrite32f(jme, JME_APMC, apmc);
1156}
1157
1158static void
1159jme_link_change_tasklet(unsigned long arg)
1160{
1161 struct jme_adapter *jme = (struct jme_adapter *)arg;
1162 struct net_device *netdev = jme->dev;
1163 int rc;
1164
1165 while (!atomic_dec_and_test(&jme->link_changing)) {
1166 atomic_inc(&jme->link_changing);
1167 msg_intr(jme, "Get link change lock failed.\n");
1168 while (atomic_read(&jme->link_changing) != 1)
1169 msg_intr(jme, "Waiting link change lock.\n");
1170 }
1171
1172 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1173 goto out;
1174
1175 jme->old_mtu = netdev->mtu;
1176 netif_stop_queue(netdev);
1177 if (jme_pseudo_hotplug_enabled(jme))
1178 jme_stop_shutdown_timer(jme);
1179
1180 jme_stop_pcc_timer(jme);
1181 tasklet_disable(&jme->txclean_task);
1182 tasklet_disable(&jme->rxclean_task);
1183 tasklet_disable(&jme->rxempty_task);
1184
1185 if (netif_carrier_ok(netdev)) {
1186 jme_reset_ghc_speed(jme);
1187 jme_disable_rx_engine(jme);
1188 jme_disable_tx_engine(jme);
1189 jme_reset_mac_processor(jme);
1190 jme_free_rx_resources(jme);
1191 jme_free_tx_resources(jme);
1192
1193 if (test_bit(JME_FLAG_POLL, &jme->flags))
1194 jme_polling_mode(jme);
1195
1196 netif_carrier_off(netdev);
1197 }
1198
1199 jme_check_link(netdev, 0);
1200 if (netif_carrier_ok(netdev)) {
1201 rc = jme_setup_rx_resources(jme);
1202 if (rc) {
1203 jeprintk(jme->pdev, "Allocating resources for RX error"
1204 ", Device STOPPED!\n");
1205 goto out_enable_tasklet;
1206 }
1207
1208 rc = jme_setup_tx_resources(jme);
1209 if (rc) {
1210 jeprintk(jme->pdev, "Allocating resources for TX error"
1211 ", Device STOPPED!\n");
1212 goto err_out_free_rx_resources;
1213 }
1214
1215 jme_enable_rx_engine(jme);
1216 jme_enable_tx_engine(jme);
1217
1218 netif_start_queue(netdev);
1219
1220 if (test_bit(JME_FLAG_POLL, &jme->flags))
1221 jme_interrupt_mode(jme);
1222
1223 jme_start_pcc_timer(jme);
1224 } else if (jme_pseudo_hotplug_enabled(jme)) {
1225 jme_start_shutdown_timer(jme);
1226 }
1227
1228 goto out_enable_tasklet;
1229
1230err_out_free_rx_resources:
1231 jme_free_rx_resources(jme);
1232out_enable_tasklet:
1233 tasklet_enable(&jme->txclean_task);
1234 tasklet_hi_enable(&jme->rxclean_task);
1235 tasklet_hi_enable(&jme->rxempty_task);
1236out:
1237 atomic_inc(&jme->link_changing);
1238}
1239
1240static void
1241jme_rx_clean_tasklet(unsigned long arg)
1242{
1243 struct jme_adapter *jme = (struct jme_adapter *)arg;
1244 struct dynpcc_info *dpi = &(jme->dpi);
1245
1246 jme_process_receive(jme, jme->rx_ring_size);
1247 ++(dpi->intr_cnt);
1248
1249}
1250
1251static int
1252jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1253{
1254 struct jme_adapter *jme = jme_napi_priv(holder);
1255 DECLARE_NETDEV
1256 int rest;
1257
1258 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1259
1260 while (atomic_read(&jme->rx_empty) > 0) {
1261 atomic_dec(&jme->rx_empty);
1262 ++(NET_STAT(jme).rx_dropped);
1263 jme_restart_rx_engine(jme);
1264 }
1265 atomic_inc(&jme->rx_empty);
1266
1267 if (rest) {
1268 JME_RX_COMPLETE(netdev, holder);
1269 jme_interrupt_mode(jme);
1270 }
1271
1272 JME_NAPI_WEIGHT_SET(budget, rest);
1273 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1274}
1275
1276static void
1277jme_rx_empty_tasklet(unsigned long arg)
1278{
1279 struct jme_adapter *jme = (struct jme_adapter *)arg;
1280
1281 if (unlikely(atomic_read(&jme->link_changing) != 1))
1282 return;
1283
1284 if (unlikely(!netif_carrier_ok(jme->dev)))
1285 return;
1286
1287 msg_rx_status(jme, "RX Queue Full!\n");
1288
1289 jme_rx_clean_tasklet(arg);
1290
1291 while (atomic_read(&jme->rx_empty) > 0) {
1292 atomic_dec(&jme->rx_empty);
1293 ++(NET_STAT(jme).rx_dropped);
1294 jme_restart_rx_engine(jme);
1295 }
1296 atomic_inc(&jme->rx_empty);
1297}
1298
1299static void
1300jme_wake_queue_if_stopped(struct jme_adapter *jme)
1301{
1302 struct jme_ring *txring = jme->txring;
1303
1304 smp_wmb();
1305 if (unlikely(netif_queue_stopped(jme->dev) &&
1306 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1307 msg_tx_done(jme, "TX Queue Waked.\n");
1308 netif_wake_queue(jme->dev);
1309 }
1310
1311}
1312
1313static void
1314jme_tx_clean_tasklet(unsigned long arg)
1315{
1316 struct jme_adapter *jme = (struct jme_adapter *)arg;
1317 struct jme_ring *txring = &(jme->txring[0]);
1318 struct txdesc *txdesc = txring->desc;
1319 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1320 int i, j, cnt = 0, max, err, mask;
1321
1322 tx_dbg(jme, "Into txclean.\n");
1323
1324 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1325 goto out;
1326
1327 if (unlikely(atomic_read(&jme->link_changing) != 1))
1328 goto out;
1329
1330 if (unlikely(!netif_carrier_ok(jme->dev)))
1331 goto out;
1332
1333 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1334 mask = jme->tx_ring_mask;
1335
1336 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1337
1338 ctxbi = txbi + i;
1339
1340 if (likely(ctxbi->skb &&
1341 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1342
1343 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1344 i, ctxbi->nr_desc, jiffies);
1345
1346 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1347
1348 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1349 ttxbi = txbi + ((i + j) & (mask));
1350 txdesc[(i + j) & (mask)].dw[0] = 0;
1351
1352 pci_unmap_page(jme->pdev,
1353 ttxbi->mapping,
1354 ttxbi->len,
1355 PCI_DMA_TODEVICE);
1356
1357 ttxbi->mapping = 0;
1358 ttxbi->len = 0;
1359 }
1360
1361 dev_kfree_skb(ctxbi->skb);
1362
1363 cnt += ctxbi->nr_desc;
1364
1365 if (unlikely(err)) {
1366 ++(NET_STAT(jme).tx_carrier_errors);
1367 } else {
1368 ++(NET_STAT(jme).tx_packets);
1369 NET_STAT(jme).tx_bytes += ctxbi->len;
1370 }
1371
1372 ctxbi->skb = NULL;
1373 ctxbi->len = 0;
1374 ctxbi->start_xmit = 0;
1375
1376 } else {
1377 break;
1378 }
1379
1380 i = (i + ctxbi->nr_desc) & mask;
1381
1382 ctxbi->nr_desc = 0;
1383 }
1384
1385 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1386 atomic_set(&txring->next_to_clean, i);
1387 atomic_add(cnt, &txring->nr_free);
1388
1389 jme_wake_queue_if_stopped(jme);
1390
1391out:
1392 atomic_inc(&jme->tx_cleaning);
1393}
1394
1395static void
1396jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1397{
1398 /*
1399 * Disable interrupt
1400 */
1401 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1402
1403 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1404 /*
1405 * Link change event is critical
1406 * all other events are ignored
1407 */
1408 jwrite32(jme, JME_IEVE, intrstat);
1409 tasklet_schedule(&jme->linkch_task);
1410 goto out_reenable;
1411 }
1412
1413 if (intrstat & INTR_TMINTR) {
1414 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1415 tasklet_schedule(&jme->pcc_task);
1416 }
1417
1418 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1419 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1420 tasklet_schedule(&jme->txclean_task);
1421 }
1422
1423 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1424 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1425 INTR_PCCRX0 |
1426 INTR_RX0EMP)) |
1427 INTR_RX0);
1428 }
1429
1430 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1431 if (intrstat & INTR_RX0EMP)
1432 atomic_inc(&jme->rx_empty);
1433
1434 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1435 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1436 jme_polling_mode(jme);
1437 JME_RX_SCHEDULE(jme);
1438 }
1439 }
1440 } else {
1441 if (intrstat & INTR_RX0EMP) {
1442 atomic_inc(&jme->rx_empty);
1443 tasklet_hi_schedule(&jme->rxempty_task);
1444 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1445 tasklet_hi_schedule(&jme->rxclean_task);
1446 }
1447 }
1448
1449out_reenable:
1450 /*
1451 * Re-enable interrupt
1452 */
1453 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1454}
1455
1456#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1457static irqreturn_t
1458jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1459#else
1460static irqreturn_t
1461jme_intr(int irq, void *dev_id)
1462#endif
1463{
1464 struct net_device *netdev = dev_id;
1465 struct jme_adapter *jme = netdev_priv(netdev);
1466 u32 intrstat;
1467
1468 intrstat = jread32(jme, JME_IEVE);
1469
1470 /*
1471 * Check if it's really an interrupt for us
1472 */
1473 if (unlikely((intrstat & INTR_ENABLE) == 0))
1474 return IRQ_NONE;
1475
1476 /*
1477 * Check if the device still exist
1478 */
1479 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1480 return IRQ_NONE;
1481
1482 jme_intr_msi(jme, intrstat);
1483
1484 return IRQ_HANDLED;
1485}
1486
1487#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1488static irqreturn_t
1489jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1490#else
1491static irqreturn_t
1492jme_msi(int irq, void *dev_id)
1493#endif
1494{
1495 struct net_device *netdev = dev_id;
1496 struct jme_adapter *jme = netdev_priv(netdev);
1497 u32 intrstat;
1498
1499 pci_dma_sync_single_for_cpu(jme->pdev,
1500 jme->shadow_dma,
1501 sizeof(u32) * SHADOW_REG_NR,
1502 PCI_DMA_FROMDEVICE);
1503 intrstat = jme->shadow_regs[SHADOW_IEVE];
1504 jme->shadow_regs[SHADOW_IEVE] = 0;
1505
1506 jme_intr_msi(jme, intrstat);
1507
1508 return IRQ_HANDLED;
1509}
1510
1511static void
1512jme_reset_link(struct jme_adapter *jme)
1513{
1514 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1515}
1516
1517static void
1518jme_restart_an(struct jme_adapter *jme)
1519{
1520 u32 bmcr;
1521
1522 spin_lock_bh(&jme->phy_lock);
1523 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1524 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1525 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1526 spin_unlock_bh(&jme->phy_lock);
1527}
1528
1529static int
1530jme_request_irq(struct jme_adapter *jme)
1531{
1532 int rc;
1533 struct net_device *netdev = jme->dev;
1534#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1535 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1536 int irq_flags = SA_SHIRQ;
1537#else
1538 irq_handler_t handler = jme_intr;
1539 int irq_flags = IRQF_SHARED;
1540#endif
1541
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1544 handler = jme_msi;
1545 irq_flags = 0;
1546 }
1547
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1549 netdev);
1550 if (rc) {
1551 jeprintk(jme->pdev,
1552 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1554 rc);
1555
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
1559 }
1560 } else {
1561 netdev->irq = jme->pdev->irq;
1562 }
1563
1564 return rc;
1565}
1566
1567static void
1568jme_free_irq(struct jme_adapter *jme)
1569{
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
1574 jme->dev->irq = jme->pdev->irq;
1575 }
1576}
1577
1578static int
1579jme_open(struct net_device *netdev)
1580{
1581 struct jme_adapter *jme = netdev_priv(netdev);
1582 int rc;
1583
1584 jme_clear_pm(jme);
1585 JME_NAPI_ENABLE(jme);
1586
1587 tasklet_enable(&jme->txclean_task);
1588 tasklet_hi_enable(&jme->rxclean_task);
1589 tasklet_hi_enable(&jme->rxempty_task);
1590
1591 rc = jme_request_irq(jme);
1592 if (rc)
1593 goto err_out;
1594
1595 jme_enable_shadow(jme);
1596 jme_start_irq(jme);
1597
1598 if (test_bit(JME_FLAG_SSET, &jme->flags))
1599 jme_set_settings(netdev, &jme->old_ecmd);
1600 else
1601 jme_reset_phy_processor(jme);
1602
1603 jme_reset_link(jme);
1604
1605 return 0;
1606
1607err_out:
1608 netif_stop_queue(netdev);
1609 netif_carrier_off(netdev);
1610 return rc;
1611}
1612
1613#ifdef CONFIG_PM
1614static void
1615jme_set_100m_half(struct jme_adapter *jme)
1616{
1617 u32 bmcr, tmp;
1618
1619 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1620 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1621 BMCR_SPEED1000 | BMCR_FULLDPLX);
1622 tmp |= BMCR_SPEED100;
1623
1624 if (bmcr != tmp)
1625 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1626
1627 if (jme->fpgaver)
1628 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1629 else
1630 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1631}
1632
1633#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1634static void
1635jme_wait_link(struct jme_adapter *jme)
1636{
1637 u32 phylink, to = JME_WAIT_LINK_TIME;
1638
1639 mdelay(1000);
1640 phylink = jme_linkstat_from_phy(jme);
1641 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1642 mdelay(10);
1643 phylink = jme_linkstat_from_phy(jme);
1644 }
1645}
1646#endif
1647
1648static inline void
1649jme_phy_off(struct jme_adapter *jme)
1650{
1651 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1652}
1653
1654static int
1655jme_close(struct net_device *netdev)
1656{
1657 struct jme_adapter *jme = netdev_priv(netdev);
1658
1659 netif_stop_queue(netdev);
1660 netif_carrier_off(netdev);
1661
1662 jme_stop_irq(jme);
1663 jme_disable_shadow(jme);
1664 jme_free_irq(jme);
1665
1666 JME_NAPI_DISABLE(jme);
1667
1668 tasklet_kill(&jme->linkch_task);
1669 tasklet_kill(&jme->txclean_task);
1670 tasklet_kill(&jme->rxclean_task);
1671 tasklet_kill(&jme->rxempty_task);
1672
1673 jme_reset_ghc_speed(jme);
1674 jme_disable_rx_engine(jme);
1675 jme_disable_tx_engine(jme);
1676 jme_reset_mac_processor(jme);
1677 jme_free_rx_resources(jme);
1678 jme_free_tx_resources(jme);
1679 jme->phylink = 0;
1680 jme_phy_off(jme);
1681
1682 return 0;
1683}
1684
1685static int
1686jme_alloc_txdesc(struct jme_adapter *jme,
1687 struct sk_buff *skb)
1688{
1689 struct jme_ring *txring = jme->txring;
1690 int idx, nr_alloc, mask = jme->tx_ring_mask;
1691
1692 idx = txring->next_to_use;
1693 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1694
1695 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1696 return -1;
1697
1698 atomic_sub(nr_alloc, &txring->nr_free);
1699
1700 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1701
1702 return idx;
1703}
1704
1705static void
1706jme_fill_tx_map(struct pci_dev *pdev,
1707 struct txdesc *txdesc,
1708 struct jme_buffer_info *txbi,
1709 struct page *page,
1710 u32 page_offset,
1711 u32 len,
1712 u8 hidma)
1713{
1714 dma_addr_t dmaaddr;
1715
1716 dmaaddr = pci_map_page(pdev,
1717 page,
1718 page_offset,
1719 len,
1720 PCI_DMA_TODEVICE);
1721
1722 pci_dma_sync_single_for_device(pdev,
1723 dmaaddr,
1724 len,
1725 PCI_DMA_TODEVICE);
1726
1727 txdesc->dw[0] = 0;
1728 txdesc->dw[1] = 0;
1729 txdesc->desc2.flags = TXFLAG_OWN;
1730 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1731 txdesc->desc2.datalen = cpu_to_le16(len);
1732 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1733 txdesc->desc2.bufaddrl = cpu_to_le32(
1734 (__u64)dmaaddr & 0xFFFFFFFFUL);
1735
1736 txbi->mapping = dmaaddr;
1737 txbi->len = len;
1738}
1739
1740static void
1741jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1742{
1743 struct jme_ring *txring = jme->txring;
1744 struct txdesc *txdesc = txring->desc, *ctxdesc;
1745 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1746 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1747 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1748 int mask = jme->tx_ring_mask;
1749 struct skb_frag_struct *frag;
1750 u32 len;
1751
1752 for (i = 0 ; i < nr_frags ; ++i) {
1753 frag = &skb_shinfo(skb)->frags[i];
1754 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1755 ctxbi = txbi + ((idx + i + 2) & (mask));
1756
1757 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1758 frag->page_offset, frag->size, hidma);
1759 }
1760
1761 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1762 ctxdesc = txdesc + ((idx + 1) & (mask));
1763 ctxbi = txbi + ((idx + 1) & (mask));
1764 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1765 offset_in_page(skb->data), len, hidma);
1766
1767}
1768
1769static int
1770jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1771{
1772 if (unlikely(
1773#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)
1774 skb_shinfo(skb)->tso_size
1775#else
1776 skb_shinfo(skb)->gso_size
1777#endif
1778 && skb_header_cloned(skb) &&
1779 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1780 dev_kfree_skb(skb);
1781 return -1;
1782 }
1783
1784 return 0;
1785}
1786
1787static int
1788jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1789{
1790#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)
1791 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1792#else
1793 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1794#endif
1795 if (*mss) {
1796 *flags |= TXFLAG_LSEN;
1797
1798 if (skb->protocol == htons(ETH_P_IP)) {
1799 struct iphdr *iph = ip_hdr(skb);
1800
1801 iph->check = 0;
1802 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1803 iph->daddr, 0,
1804 IPPROTO_TCP,
1805 0);
1806 } else {
1807 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1808
1809 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1810 &ip6h->daddr, 0,
1811 IPPROTO_TCP,
1812 0);
1813 }
1814
1815 return 0;
1816 }
1817
1818 return 1;
1819}
1820
1821static void
1822jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1823{
1824#ifdef CHECKSUM_PARTIAL
1825 if (skb->ip_summed == CHECKSUM_PARTIAL)
1826#else
1827 if (skb->ip_summed == CHECKSUM_HW)
1828#endif
1829 {
1830 u8 ip_proto;
1831
1832#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1833 if (skb->protocol == htons(ETH_P_IP))
1834 ip_proto = ip_hdr(skb)->protocol;
1835 else if (skb->protocol == htons(ETH_P_IPV6))
1836 ip_proto = ipv6_hdr(skb)->nexthdr;
1837 else
1838 ip_proto = 0;
1839#else
1840 switch (skb->protocol) {
1841 case htons(ETH_P_IP):
1842 ip_proto = ip_hdr(skb)->protocol;
1843 break;
1844 case htons(ETH_P_IPV6):
1845 ip_proto = ipv6_hdr(skb)->nexthdr;
1846 break;
1847 default:
1848 ip_proto = 0;
1849 break;
1850 }
1851#endif
1852
1853 switch (ip_proto) {
1854 case IPPROTO_TCP:
1855 *flags |= TXFLAG_TCPCS;
1856 break;
1857 case IPPROTO_UDP:
1858 *flags |= TXFLAG_UDPCS;
1859 break;
1860 default:
1861 msg_tx_err(jme, "Error upper layer protocol.\n");
1862 break;
1863 }
1864 }
1865}
1866
1867static inline void
1868jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1869{
1870 if (vlan_tx_tag_present(skb)) {
1871 *flags |= TXFLAG_TAGON;
1872 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1873 }
1874}
1875
1876static int
1877jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1878{
1879 struct jme_ring *txring = jme->txring;
1880 struct txdesc *txdesc;
1881 struct jme_buffer_info *txbi;
1882 u8 flags;
1883
1884 txdesc = (struct txdesc *)txring->desc + idx;
1885 txbi = txring->bufinf + idx;
1886
1887 txdesc->dw[0] = 0;
1888 txdesc->dw[1] = 0;
1889 txdesc->dw[2] = 0;
1890 txdesc->dw[3] = 0;
1891 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1892 /*
1893 * Set OWN bit at final.
1894 * When kernel transmit faster than NIC.
1895 * And NIC trying to send this descriptor before we tell
1896 * it to start sending this TX queue.
1897 * Other fields are already filled correctly.
1898 */
1899 wmb();
1900 flags = TXFLAG_OWN | TXFLAG_INT;
1901 /*
1902 * Set checksum flags while not tso
1903 */
1904 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1905 jme_tx_csum(jme, skb, &flags);
1906 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1907 jme_map_tx_skb(jme, skb, idx);
1908 txdesc->desc1.flags = flags;
1909 /*
1910 * Set tx buffer info after telling NIC to send
1911 * For better tx_clean timing
1912 */
1913 wmb();
1914 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1915 txbi->skb = skb;
1916 txbi->len = skb->len;
1917 txbi->start_xmit = jiffies;
1918 if (!txbi->start_xmit)
1919 txbi->start_xmit = (0UL-1);
1920
1921 return 0;
1922}
1923
1924static void
1925jme_stop_queue_if_full(struct jme_adapter *jme)
1926{
1927 struct jme_ring *txring = jme->txring;
1928 struct jme_buffer_info *txbi = txring->bufinf;
1929 int idx = atomic_read(&txring->next_to_clean);
1930
1931 txbi += idx;
1932
1933 smp_wmb();
1934 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1935 netif_stop_queue(jme->dev);
1936 msg_tx_queued(jme, "TX Queue Paused.\n");
1937 smp_wmb();
1938 if (atomic_read(&txring->nr_free)
1939 >= (jme->tx_wake_threshold)) {
1940 netif_wake_queue(jme->dev);
1941 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1942 }
1943 }
1944
1945 if (unlikely(txbi->start_xmit &&
1946 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1947 txbi->skb)) {
1948 netif_stop_queue(jme->dev);
1949 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1950 }
1951}
1952
1953/*
1954 * This function is already protected by netif_tx_lock()
1955 */
1956
1957static int
1958jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1959{
1960 struct jme_adapter *jme = netdev_priv(netdev);
1961 int idx;
1962
1963 if (unlikely(jme_expand_header(jme, skb))) {
1964 ++(NET_STAT(jme).tx_dropped);
1965 return NETDEV_TX_OK;
1966 }
1967
1968 idx = jme_alloc_txdesc(jme, skb);
1969
1970 if (unlikely(idx < 0)) {
1971 netif_stop_queue(netdev);
1972 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1973
1974 return NETDEV_TX_BUSY;
1975 }
1976
1977 jme_fill_tx_desc(jme, skb, idx);
1978
1979 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1980 TXCS_SELECT_QUEUE0 |
1981 TXCS_QUEUE0S |
1982 TXCS_ENABLE);
1983 netdev->trans_start = jiffies;
1984
1985 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1986 skb_shinfo(skb)->nr_frags + 2,
1987 jiffies);
1988 jme_stop_queue_if_full(jme);
1989
1990 return NETDEV_TX_OK;
1991}
1992
1993static int
1994jme_set_macaddr(struct net_device *netdev, void *p)
1995{
1996 struct jme_adapter *jme = netdev_priv(netdev);
1997 struct sockaddr *addr = p;
1998 u32 val;
1999
2000 if (netif_running(netdev))
2001 return -EBUSY;
2002
2003 spin_lock_bh(&jme->macaddr_lock);
2004 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2005
2006 val = (addr->sa_data[3] & 0xff) << 24 |
2007 (addr->sa_data[2] & 0xff) << 16 |
2008 (addr->sa_data[1] & 0xff) << 8 |
2009 (addr->sa_data[0] & 0xff);
2010 jwrite32(jme, JME_RXUMA_LO, val);
2011 val = (addr->sa_data[5] & 0xff) << 8 |
2012 (addr->sa_data[4] & 0xff);
2013 jwrite32(jme, JME_RXUMA_HI, val);
2014 spin_unlock_bh(&jme->macaddr_lock);
2015
2016 return 0;
2017}
2018
2019static void
2020jme_set_multi(struct net_device *netdev)
2021{
2022 struct jme_adapter *jme = netdev_priv(netdev);
2023 u32 mc_hash[2] = {};
2024 int i;
2025
2026 spin_lock_bh(&jme->rxmcs_lock);
2027
2028 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2029
2030 if (netdev->flags & IFF_PROMISC) {
2031 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2032 } else if (netdev->flags & IFF_ALLMULTI) {
2033 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2034 } else if (netdev->flags & IFF_MULTICAST) {
2035 struct dev_mc_list *mclist;
2036 int bit_nr;
2037
2038 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2039 for (i = 0, mclist = netdev->mc_list;
2040 mclist && i < netdev->mc_count;
2041 ++i, mclist = mclist->next) {
2042
2043 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2044 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2045 }
2046
2047 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2048 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2049 }
2050
2051 wmb();
2052 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2053
2054 spin_unlock_bh(&jme->rxmcs_lock);
2055}
2056
2057static int
2058jme_change_mtu(struct net_device *netdev, int new_mtu)
2059{
2060 struct jme_adapter *jme = netdev_priv(netdev);
2061
2062 if (new_mtu == jme->old_mtu)
2063 return 0;
2064
2065 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2066 ((new_mtu) < IPV6_MIN_MTU))
2067 return -EINVAL;
2068
2069 if (new_mtu > 4000) {
2070 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2071 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2072 jme_restart_rx_engine(jme);
2073 } else {
2074 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2075 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2076 jme_restart_rx_engine(jme);
2077 }
2078
2079 if (new_mtu > 1900) {
2080 netdev->features &= ~(NETIF_F_HW_CSUM |
2081 NETIF_F_TSO
2082#ifdef NETIF_F_TSO6
2083 | NETIF_F_TSO6
2084#endif
2085 );
2086 } else {
2087 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2088 netdev->features |= NETIF_F_HW_CSUM;
2089 if (test_bit(JME_FLAG_TSO, &jme->flags))
2090 netdev->features |= NETIF_F_TSO
2091#ifdef NETIF_F_TSO6
2092 | NETIF_F_TSO6
2093#endif
2094 ;
2095 }
2096
2097 netdev->mtu = new_mtu;
2098 jme_reset_link(jme);
2099
2100 return 0;
2101}
2102
2103static void
2104jme_tx_timeout(struct net_device *netdev)
2105{
2106 struct jme_adapter *jme = netdev_priv(netdev);
2107
2108 jme->phylink = 0;
2109 jme_reset_phy_processor(jme);
2110 if (test_bit(JME_FLAG_SSET, &jme->flags))
2111 jme_set_settings(netdev, &jme->old_ecmd);
2112
2113 /*
2114 * Force to Reset the link again
2115 */
2116 jme_reset_link(jme);
2117}
2118
2119static void
2120jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2121{
2122 struct jme_adapter *jme = netdev_priv(netdev);
2123
2124 jme->vlgrp = grp;
2125}
2126
2127static void
2128jme_get_drvinfo(struct net_device *netdev,
2129 struct ethtool_drvinfo *info)
2130{
2131 struct jme_adapter *jme = netdev_priv(netdev);
2132
2133 strcpy(info->driver, DRV_NAME);
2134 strcpy(info->version, DRV_VERSION);
2135 strcpy(info->bus_info, pci_name(jme->pdev));
2136}
2137
2138static int
2139jme_get_regs_len(struct net_device *netdev)
2140{
2141 return JME_REG_LEN;
2142}
2143
2144static void
2145mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2146{
2147 int i;
2148
2149 for (i = 0 ; i < len ; i += 4)
2150 p[i >> 2] = jread32(jme, reg + i);
2151}
2152
2153static void
2154mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2155{
2156 int i;
2157 u16 *p16 = (u16 *)p;
2158
2159 for (i = 0 ; i < reg_nr ; ++i)
2160 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2161}
2162
2163static void
2164jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2165{
2166 struct jme_adapter *jme = netdev_priv(netdev);
2167 u32 *p32 = (u32 *)p;
2168
2169 memset(p, 0xFF, JME_REG_LEN);
2170
2171 regs->version = 1;
2172 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2173
2174 p32 += 0x100 >> 2;
2175 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2176
2177 p32 += 0x100 >> 2;
2178 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2179
2180 p32 += 0x100 >> 2;
2181 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2182
2183 p32 += 0x100 >> 2;
2184 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2185}
2186
2187static int
2188jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2189{
2190 struct jme_adapter *jme = netdev_priv(netdev);
2191
2192 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2193 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2194
2195 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2196 ecmd->use_adaptive_rx_coalesce = false;
2197 ecmd->rx_coalesce_usecs = 0;
2198 ecmd->rx_max_coalesced_frames = 0;
2199 return 0;
2200 }
2201
2202 ecmd->use_adaptive_rx_coalesce = true;
2203
2204 switch (jme->dpi.cur) {
2205 case PCC_P1:
2206 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2207 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2208 break;
2209 case PCC_P2:
2210 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2211 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2212 break;
2213 case PCC_P3:
2214 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2215 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2216 break;
2217 default:
2218 break;
2219 }
2220
2221 return 0;
2222}
2223
2224static int
2225jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2226{
2227 struct jme_adapter *jme = netdev_priv(netdev);
2228 struct dynpcc_info *dpi = &(jme->dpi);
2229
2230 if (netif_running(netdev))
2231 return -EBUSY;
2232
2233 if (ecmd->use_adaptive_rx_coalesce
2234 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2235 clear_bit(JME_FLAG_POLL, &jme->flags);
2236 jme->jme_rx = netif_rx;
2237 jme->jme_vlan_rx = vlan_hwaccel_rx;
2238 dpi->cur = PCC_P1;
2239 dpi->attempt = PCC_P1;
2240 dpi->cnt = 0;
2241 jme_set_rx_pcc(jme, PCC_P1);
2242 jme_interrupt_mode(jme);
2243 } else if (!(ecmd->use_adaptive_rx_coalesce)
2244 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2245 set_bit(JME_FLAG_POLL, &jme->flags);
2246 jme->jme_rx = netif_receive_skb;
2247 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2248 jme_interrupt_mode(jme);
2249 }
2250
2251 return 0;
2252}
2253
2254static void
2255jme_get_pauseparam(struct net_device *netdev,
2256 struct ethtool_pauseparam *ecmd)
2257{
2258 struct jme_adapter *jme = netdev_priv(netdev);
2259 u32 val;
2260
2261 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2262 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2263
2264 spin_lock_bh(&jme->phy_lock);
2265 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2266 spin_unlock_bh(&jme->phy_lock);
2267
2268 ecmd->autoneg =
2269 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2270}
2271
2272static int
2273jme_set_pauseparam(struct net_device *netdev,
2274 struct ethtool_pauseparam *ecmd)
2275{
2276 struct jme_adapter *jme = netdev_priv(netdev);
2277 u32 val;
2278
2279 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2280 (ecmd->tx_pause != 0)) {
2281
2282 if (ecmd->tx_pause)
2283 jme->reg_txpfc |= TXPFC_PF_EN;
2284 else
2285 jme->reg_txpfc &= ~TXPFC_PF_EN;
2286
2287 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2288 }
2289
2290 spin_lock_bh(&jme->rxmcs_lock);
2291 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2292 (ecmd->rx_pause != 0)) {
2293
2294 if (ecmd->rx_pause)
2295 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2296 else
2297 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2298
2299 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2300 }
2301 spin_unlock_bh(&jme->rxmcs_lock);
2302
2303 spin_lock_bh(&jme->phy_lock);
2304 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2305 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2306 (ecmd->autoneg != 0)) {
2307
2308 if (ecmd->autoneg)
2309 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2310 else
2311 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2312
2313 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2314 MII_ADVERTISE, val);
2315 }
2316 spin_unlock_bh(&jme->phy_lock);
2317
2318 return 0;
2319}
2320
2321static void
2322jme_get_wol(struct net_device *netdev,
2323 struct ethtool_wolinfo *wol)
2324{
2325 struct jme_adapter *jme = netdev_priv(netdev);
2326
2327 wol->supported = WAKE_MAGIC | WAKE_PHY;
2328
2329 wol->wolopts = 0;
2330
2331 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2332 wol->wolopts |= WAKE_PHY;
2333
2334 if (jme->reg_pmcs & PMCS_MFEN)
2335 wol->wolopts |= WAKE_MAGIC;
2336
2337}
2338
2339static int
2340jme_set_wol(struct net_device *netdev,
2341 struct ethtool_wolinfo *wol)
2342{
2343 struct jme_adapter *jme = netdev_priv(netdev);
2344
2345 if (wol->wolopts & (WAKE_MAGICSECURE |
2346 WAKE_UCAST |
2347 WAKE_MCAST |
2348 WAKE_BCAST |
2349 WAKE_ARP))
2350 return -EOPNOTSUPP;
2351
2352 jme->reg_pmcs = 0;
2353
2354 if (wol->wolopts & WAKE_PHY)
2355 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2356
2357 if (wol->wolopts & WAKE_MAGIC)
2358 jme->reg_pmcs |= PMCS_MFEN;
2359
2360 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2361
2362 return 0;
2363}
2364
2365static int
2366jme_get_settings(struct net_device *netdev,
2367 struct ethtool_cmd *ecmd)
2368{
2369 struct jme_adapter *jme = netdev_priv(netdev);
2370 int rc;
2371
2372 spin_lock_bh(&jme->phy_lock);
2373 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2374 spin_unlock_bh(&jme->phy_lock);
2375 return rc;
2376}
2377
2378static int
2379jme_set_settings(struct net_device *netdev,
2380 struct ethtool_cmd *ecmd)
2381{
2382 struct jme_adapter *jme = netdev_priv(netdev);
2383 int rc, fdc = 0;
2384
2385 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2386 return -EINVAL;
2387
2388 if (jme->mii_if.force_media &&
2389 ecmd->autoneg != AUTONEG_ENABLE &&
2390 (jme->mii_if.full_duplex != ecmd->duplex))
2391 fdc = 1;
2392
2393 spin_lock_bh(&jme->phy_lock);
2394 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2395 spin_unlock_bh(&jme->phy_lock);
2396
2397 if (!rc && fdc)
2398 jme_reset_link(jme);
2399
2400 if (!rc) {
2401 set_bit(JME_FLAG_SSET, &jme->flags);
2402 jme->old_ecmd = *ecmd;
2403 }
2404
2405 return rc;
2406}
2407
2408static u32
2409jme_get_link(struct net_device *netdev)
2410{
2411 struct jme_adapter *jme = netdev_priv(netdev);
2412 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2413}
2414
2415static u32
2416jme_get_msglevel(struct net_device *netdev)
2417{
2418 struct jme_adapter *jme = netdev_priv(netdev);
2419 return jme->msg_enable;
2420}
2421
2422static void
2423jme_set_msglevel(struct net_device *netdev, u32 value)
2424{
2425 struct jme_adapter *jme = netdev_priv(netdev);
2426 jme->msg_enable = value;
2427}
2428
2429static u32
2430jme_get_rx_csum(struct net_device *netdev)
2431{
2432 struct jme_adapter *jme = netdev_priv(netdev);
2433 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2434}
2435
2436static int
2437jme_set_rx_csum(struct net_device *netdev, u32 on)
2438{
2439 struct jme_adapter *jme = netdev_priv(netdev);
2440
2441 spin_lock_bh(&jme->rxmcs_lock);
2442 if (on)
2443 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2444 else
2445 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2446 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2447 spin_unlock_bh(&jme->rxmcs_lock);
2448
2449 return 0;
2450}
2451
2452static int
2453jme_set_tx_csum(struct net_device *netdev, u32 on)
2454{
2455 struct jme_adapter *jme = netdev_priv(netdev);
2456
2457 if (on) {
2458 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2459 if (netdev->mtu <= 1900)
2460 netdev->features |= NETIF_F_HW_CSUM;
2461 } else {
2462 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2463 netdev->features &= ~NETIF_F_HW_CSUM;
2464 }
2465
2466 return 0;
2467}
2468
2469static int
2470jme_set_tso(struct net_device *netdev, u32 on)
2471{
2472 struct jme_adapter *jme = netdev_priv(netdev);
2473
2474 if (on) {
2475 set_bit(JME_FLAG_TSO, &jme->flags);
2476 if (netdev->mtu <= 1900)
2477 netdev->features |= NETIF_F_TSO
2478#ifdef NETIF_F_TSO6
2479 | NETIF_F_TSO6
2480#endif
2481 ;
2482 } else {
2483 clear_bit(JME_FLAG_TSO, &jme->flags);
2484 netdev->features &= ~(NETIF_F_TSO
2485#ifdef NETIF_F_TSO6
2486 | NETIF_F_TSO6
2487#endif
2488 );
2489 }
2490
2491 return 0;
2492}
2493
2494static int
2495jme_nway_reset(struct net_device *netdev)
2496{
2497 struct jme_adapter *jme = netdev_priv(netdev);
2498 jme_restart_an(jme);
2499 return 0;
2500}
2501
2502static u8
2503jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2504{
2505 u32 val;
2506 int to;
2507
2508 val = jread32(jme, JME_SMBCSR);
2509 to = JME_SMB_BUSY_TIMEOUT;
2510 while ((val & SMBCSR_BUSY) && --to) {
2511 msleep(1);
2512 val = jread32(jme, JME_SMBCSR);
2513 }
2514 if (!to) {
2515 msg_hw(jme, "SMB Bus Busy.\n");
2516 return 0xFF;
2517 }
2518
2519 jwrite32(jme, JME_SMBINTF,
2520 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2521 SMBINTF_HWRWN_READ |
2522 SMBINTF_HWCMD);
2523
2524 val = jread32(jme, JME_SMBINTF);
2525 to = JME_SMB_BUSY_TIMEOUT;
2526 while ((val & SMBINTF_HWCMD) && --to) {
2527 msleep(1);
2528 val = jread32(jme, JME_SMBINTF);
2529 }
2530 if (!to) {
2531 msg_hw(jme, "SMB Bus Busy.\n");
2532 return 0xFF;
2533 }
2534
2535 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2536}
2537
2538static void
2539jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2540{
2541 u32 val;
2542 int to;
2543
2544 val = jread32(jme, JME_SMBCSR);
2545 to = JME_SMB_BUSY_TIMEOUT;
2546 while ((val & SMBCSR_BUSY) && --to) {
2547 msleep(1);
2548 val = jread32(jme, JME_SMBCSR);
2549 }
2550 if (!to) {
2551 msg_hw(jme, "SMB Bus Busy.\n");
2552 return;
2553 }
2554
2555 jwrite32(jme, JME_SMBINTF,
2556 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2557 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2558 SMBINTF_HWRWN_WRITE |
2559 SMBINTF_HWCMD);
2560
2561 val = jread32(jme, JME_SMBINTF);
2562 to = JME_SMB_BUSY_TIMEOUT;
2563 while ((val & SMBINTF_HWCMD) && --to) {
2564 msleep(1);
2565 val = jread32(jme, JME_SMBINTF);
2566 }
2567 if (!to) {
2568 msg_hw(jme, "SMB Bus Busy.\n");
2569 return;
2570 }
2571
2572 mdelay(2);
2573}
2574
2575static int
2576jme_get_eeprom_len(struct net_device *netdev)
2577{
2578 struct jme_adapter *jme = netdev_priv(netdev);
2579 u32 val;
2580 val = jread32(jme, JME_SMBCSR);
2581 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2582}
2583
2584static int
2585jme_get_eeprom(struct net_device *netdev,
2586 struct ethtool_eeprom *eeprom, u8 *data)
2587{
2588 struct jme_adapter *jme = netdev_priv(netdev);
2589 int i, offset = eeprom->offset, len = eeprom->len;
2590
2591 /*
2592 * ethtool will check the boundary for us
2593 */
2594 eeprom->magic = JME_EEPROM_MAGIC;
2595 for (i = 0 ; i < len ; ++i)
2596 data[i] = jme_smb_read(jme, i + offset);
2597
2598 return 0;
2599}
2600
2601static int
2602jme_set_eeprom(struct net_device *netdev,
2603 struct ethtool_eeprom *eeprom, u8 *data)
2604{
2605 struct jme_adapter *jme = netdev_priv(netdev);
2606 int i, offset = eeprom->offset, len = eeprom->len;
2607
2608 if (eeprom->magic != JME_EEPROM_MAGIC)
2609 return -EINVAL;
2610
2611 /*
2612 * ethtool will check the boundary for us
2613 */
2614 for (i = 0 ; i < len ; ++i)
2615 jme_smb_write(jme, i + offset, data[i]);
2616
2617 return 0;
2618}
2619
2620#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2621static struct ethtool_ops jme_ethtool_ops = {
2622#else
2623static const struct ethtool_ops jme_ethtool_ops = {
2624#endif
2625 .get_drvinfo = jme_get_drvinfo,
2626 .get_regs_len = jme_get_regs_len,
2627 .get_regs = jme_get_regs,
2628 .get_coalesce = jme_get_coalesce,
2629 .set_coalesce = jme_set_coalesce,
2630 .get_pauseparam = jme_get_pauseparam,
2631 .set_pauseparam = jme_set_pauseparam,
2632 .get_wol = jme_get_wol,
2633 .set_wol = jme_set_wol,
2634 .get_settings = jme_get_settings,
2635 .set_settings = jme_set_settings,
2636 .get_link = jme_get_link,
2637 .get_msglevel = jme_get_msglevel,
2638 .set_msglevel = jme_set_msglevel,
2639 .get_rx_csum = jme_get_rx_csum,
2640 .set_rx_csum = jme_set_rx_csum,
2641 .set_tx_csum = jme_set_tx_csum,
2642 .set_tso = jme_set_tso,
2643 .set_sg = ethtool_op_set_sg,
2644 .nway_reset = jme_nway_reset,
2645 .get_eeprom_len = jme_get_eeprom_len,
2646 .get_eeprom = jme_get_eeprom,
2647 .set_eeprom = jme_set_eeprom,
2648};
2649
2650static int
2651jme_pci_dma64(struct pci_dev *pdev)
2652{
2653 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2654 !pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2655 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2656 return 1;
2657
2658 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2659 !pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2660 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2661 return 1;
2662
2663 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2664 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2665 return 0;
2666
2667 return -1;
2668}
2669
2670static inline void
2671jme_phy_init(struct jme_adapter *jme)
2672{
2673 u16 reg26;
2674
2675 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2676 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2677}
2678
2679static inline void
2680jme_check_hw_ver(struct jme_adapter *jme)
2681{
2682 u32 chipmode;
2683
2684 chipmode = jread32(jme, JME_CHIPMODE);
2685
2686 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2687 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2688}
2689
2690#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2691static const struct net_device_ops jme_netdev_ops = {
2692 .ndo_open = jme_open,
2693 .ndo_stop = jme_close,
2694 .ndo_validate_addr = eth_validate_addr,
2695 .ndo_start_xmit = jme_start_xmit,
2696 .ndo_set_mac_address = jme_set_macaddr,
2697 .ndo_set_multicast_list = jme_set_multi,
2698 .ndo_change_mtu = jme_change_mtu,
2699 .ndo_tx_timeout = jme_tx_timeout,
2700 .ndo_vlan_rx_register = jme_vlan_rx_register,
2701};
2702#endif
2703
2704static int __devinit
2705jme_init_one(struct pci_dev *pdev,
2706 const struct pci_device_id *ent)
2707{
2708 int rc = 0, using_dac, i;
2709 struct net_device *netdev;
2710 struct jme_adapter *jme;
2711 u16 bmcr, bmsr;
2712 u32 apmc;
2713
2714 /*
2715 * set up PCI device basics
2716 */
2717 rc = pci_enable_device(pdev);
2718 if (rc) {
2719 jeprintk(pdev, "Cannot enable PCI device.\n");
2720 goto err_out;
2721 }
2722
2723 using_dac = jme_pci_dma64(pdev);
2724 if (using_dac < 0) {
2725 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2726 rc = -EIO;
2727 goto err_out_disable_pdev;
2728 }
2729
2730 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2731 jeprintk(pdev, "No PCI resource region found.\n");
2732 rc = -ENOMEM;
2733 goto err_out_disable_pdev;
2734 }
2735
2736 rc = pci_request_regions(pdev, DRV_NAME);
2737 if (rc) {
2738 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2739 goto err_out_disable_pdev;
2740 }
2741
2742 pci_set_master(pdev);
2743
2744 /*
2745 * alloc and init net device
2746 */
2747 netdev = alloc_etherdev(sizeof(*jme));
2748 if (!netdev) {
2749 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2750 rc = -ENOMEM;
2751 goto err_out_release_regions;
2752 }
2753#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2754 netdev->netdev_ops = &jme_netdev_ops;
2755#else
2756 netdev->open = jme_open;
2757 netdev->stop = jme_close;
2758 netdev->hard_start_xmit = jme_start_xmit;
2759 netdev->set_mac_address = jme_set_macaddr;
2760 netdev->set_multicast_list = jme_set_multi;
2761 netdev->change_mtu = jme_change_mtu;
2762 netdev->tx_timeout = jme_tx_timeout;
2763 netdev->vlan_rx_register = jme_vlan_rx_register;
2764 NETDEV_GET_STATS(netdev, &jme_get_stats);
2765#endif
2766 netdev->ethtool_ops = &jme_ethtool_ops;
2767 netdev->watchdog_timeo = TX_TIMEOUT;
2768 netdev->features = NETIF_F_HW_CSUM |
2769 NETIF_F_SG |
2770 NETIF_F_TSO |
2771#ifdef NETIF_F_TSO6
2772 NETIF_F_TSO6 |
2773#endif
2774 NETIF_F_HW_VLAN_TX |
2775 NETIF_F_HW_VLAN_RX;
2776 if (using_dac)
2777 netdev->features |= NETIF_F_HIGHDMA;
2778
2779 SET_NETDEV_DEV(netdev, &pdev->dev);
2780 pci_set_drvdata(pdev, netdev);
2781
2782 /*
2783 * init adapter info
2784 */
2785 jme = netdev_priv(netdev);
2786 jme->pdev = pdev;
2787 jme->dev = netdev;
2788 jme->jme_rx = netif_rx;
2789 jme->jme_vlan_rx = vlan_hwaccel_rx;
2790 jme->old_mtu = netdev->mtu = 1500;
2791 jme->phylink = 0;
2792#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2793 jme->tx_ring_size = 1 << 9;
2794 jme->tx_wake_threshold = 1 << 8;
2795 jme->rx_ring_size = 1 << 8;
2796#else
2797 jme->tx_ring_size = 1 << 10;
2798 jme->tx_wake_threshold = 1 << 9;
2799 jme->rx_ring_size = 1 << 9;
2800#endif
2801 jme->tx_ring_mask = jme->tx_ring_size - 1;
2802 jme->rx_ring_mask = jme->rx_ring_size - 1;
2803 jme->msg_enable = JME_DEF_MSG_ENABLE;
2804 jme->regs = ioremap(pci_resource_start(pdev, 0),
2805 pci_resource_len(pdev, 0));
2806 if (!(jme->regs)) {
2807 jeprintk(pdev, "Mapping PCI resource region error.\n");
2808 rc = -ENOMEM;
2809 goto err_out_free_netdev;
2810 }
2811 jme->shadow_regs = pci_alloc_consistent(pdev,
2812 sizeof(u32) * SHADOW_REG_NR,
2813 &(jme->shadow_dma));
2814 if (!(jme->shadow_regs)) {
2815 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2816 rc = -ENOMEM;
2817 goto err_out_unmap;
2818 }
2819
2820 if (no_pseudohp) {
2821 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2822 jwrite32(jme, JME_APMC, apmc);
2823 } else if (force_pseudohp) {
2824 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2825 jwrite32(jme, JME_APMC, apmc);
2826 }
2827
2828 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2829
2830 spin_lock_init(&jme->phy_lock);
2831 spin_lock_init(&jme->macaddr_lock);
2832 spin_lock_init(&jme->rxmcs_lock);
2833
2834 atomic_set(&jme->link_changing, 1);
2835 atomic_set(&jme->rx_cleaning, 1);
2836 atomic_set(&jme->tx_cleaning, 1);
2837 atomic_set(&jme->rx_empty, 1);
2838
2839 tasklet_init(&jme->pcc_task,
2840 &jme_pcc_tasklet,
2841 (unsigned long) jme);
2842 tasklet_init(&jme->linkch_task,
2843 &jme_link_change_tasklet,
2844 (unsigned long) jme);
2845 tasklet_init(&jme->txclean_task,
2846 &jme_tx_clean_tasklet,
2847 (unsigned long) jme);
2848 tasklet_init(&jme->rxclean_task,
2849 &jme_rx_clean_tasklet,
2850 (unsigned long) jme);
2851 tasklet_init(&jme->rxempty_task,
2852 &jme_rx_empty_tasklet,
2853 (unsigned long) jme);
2854 tasklet_disable_nosync(&jme->txclean_task);
2855 tasklet_disable_nosync(&jme->rxclean_task);
2856 tasklet_disable_nosync(&jme->rxempty_task);
2857 jme->dpi.cur = PCC_P1;
2858
2859 jme->reg_ghc = 0;
2860 jme->reg_rxcs = RXCS_DEFAULT;
2861 jme->reg_rxmcs = RXMCS_DEFAULT;
2862 jme->reg_txpfc = 0;
2863 jme->reg_pmcs = PMCS_MFEN;
2864 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2865 set_bit(JME_FLAG_TSO, &jme->flags);
2866
2867 /*
2868 * Get Max Read Req Size from PCI Config Space
2869 */
2870 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2871 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2872 switch (jme->mrrs) {
2873 case MRRS_128B:
2874 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2875 break;
2876 case MRRS_256B:
2877 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2878 break;
2879 default:
2880 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2881 break;
2882 };
2883
2884 /*
2885 * Must check before reset_mac_processor
2886 */
2887 jme_check_hw_ver(jme);
2888 jme->mii_if.dev = netdev;
2889 if (jme->fpgaver) {
2890 jme->mii_if.phy_id = 0;
2891 for (i = 1 ; i < 32 ; ++i) {
2892 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2893 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2894 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2895 jme->mii_if.phy_id = i;
2896 break;
2897 }
2898 }
2899
2900 if (!jme->mii_if.phy_id) {
2901 rc = -EIO;
2902 jeprintk(pdev, "Can not find phy_id.\n");
2903 goto err_out_free_shadow;
2904 }
2905
2906 jme->reg_ghc |= GHC_LINK_POLL;
2907 } else {
2908 jme->mii_if.phy_id = 1;
2909 }
2910 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2911 jme->mii_if.supports_gmii = true;
2912 else
2913 jme->mii_if.supports_gmii = false;
2914 jme->mii_if.mdio_read = jme_mdio_read;
2915 jme->mii_if.mdio_write = jme_mdio_write;
2916
2917 jme_clear_pm(jme);
2918 jme_set_phyfifoa(jme);
2919 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2920 if (!jme->fpgaver)
2921 jme_phy_init(jme);
2922 jme_phy_off(jme);
2923
2924 /*
2925 * Reset MAC processor and reload EEPROM for MAC Address
2926 */
2927 jme_reset_mac_processor(jme);
2928 rc = jme_reload_eeprom(jme);
2929 if (rc) {
2930 jeprintk(pdev,
2931 "Reload eeprom for reading MAC Address error.\n");
2932 goto err_out_free_shadow;
2933 }
2934 jme_load_macaddr(netdev);
2935
2936 /*
2937 * Tell stack that we are not ready to work until open()
2938 */
2939 netif_carrier_off(netdev);
2940 netif_stop_queue(netdev);
2941
2942 /*
2943 * Register netdev
2944 */
2945 rc = register_netdev(netdev);
2946 if (rc) {
2947 jeprintk(pdev, "Cannot register net device.\n");
2948 goto err_out_free_shadow;
2949 }
2950
2951 msg_probe(jme, "%s%s ver:%x rev:%x macaddr:%pM\n",
2952 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2953 "JMC250 Gigabit Ethernet" :
2954 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2955 "JMC260 Fast Ethernet" : "Unknown",
2956 (jme->fpgaver != 0) ? " (FPGA)" : "",
2957 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2958 jme->rev, netdev->dev_addr);
2959
2960 return 0;
2961
2962err_out_free_shadow:
2963 pci_free_consistent(pdev,
2964 sizeof(u32) * SHADOW_REG_NR,
2965 jme->shadow_regs,
2966 jme->shadow_dma);
2967err_out_unmap:
2968 iounmap(jme->regs);
2969err_out_free_netdev:
2970 pci_set_drvdata(pdev, NULL);
2971 free_netdev(netdev);
2972err_out_release_regions:
2973 pci_release_regions(pdev);
2974err_out_disable_pdev:
2975 pci_disable_device(pdev);
2976err_out:
2977 return rc;
2978}
2979
2980static void __devexit
2981jme_remove_one(struct pci_dev *pdev)
2982{
2983 struct net_device *netdev = pci_get_drvdata(pdev);
2984 struct jme_adapter *jme = netdev_priv(netdev);
2985
2986 unregister_netdev(netdev);
2987 pci_free_consistent(pdev,
2988 sizeof(u32) * SHADOW_REG_NR,
2989 jme->shadow_regs,
2990 jme->shadow_dma);
2991 iounmap(jme->regs);
2992 pci_set_drvdata(pdev, NULL);
2993 free_netdev(netdev);
2994 pci_release_regions(pdev);
2995 pci_disable_device(pdev);
2996
2997}
2998
2999#ifdef CONFIG_PM
3000static int
3001jme_suspend(struct pci_dev *pdev, pm_message_t state)
3002{
3003 struct net_device *netdev = pci_get_drvdata(pdev);
3004 struct jme_adapter *jme = netdev_priv(netdev);
3005
3006 atomic_dec(&jme->link_changing);
3007
3008 netif_device_detach(netdev);
3009 netif_stop_queue(netdev);
3010 jme_stop_irq(jme);
3011
3012 tasklet_disable(&jme->txclean_task);
3013 tasklet_disable(&jme->rxclean_task);
3014 tasklet_disable(&jme->rxempty_task);
3015
3016 jme_disable_shadow(jme);
3017
3018 if (netif_carrier_ok(netdev)) {
3019 if (test_bit(JME_FLAG_POLL, &jme->flags))
3020 jme_polling_mode(jme);
3021
3022 jme_stop_pcc_timer(jme);
3023 jme_reset_ghc_speed(jme);
3024 jme_disable_rx_engine(jme);
3025 jme_disable_tx_engine(jme);
3026 jme_reset_mac_processor(jme);
3027 jme_free_rx_resources(jme);
3028 jme_free_tx_resources(jme);
3029 netif_carrier_off(netdev);
3030 jme->phylink = 0;
3031 }
3032
3033 tasklet_enable(&jme->txclean_task);
3034 tasklet_hi_enable(&jme->rxclean_task);
3035 tasklet_hi_enable(&jme->rxempty_task);
3036
3037 pci_save_state(pdev);
3038 if (jme->reg_pmcs) {
3039 jme_set_100m_half(jme);
3040
3041 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3042 jme_wait_link(jme);
3043
3044 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3045
3046 pci_enable_wake(pdev, PCI_D3cold, true);
3047 } else {
3048 jme_phy_off(jme);
3049 }
3050 pci_set_power_state(pdev, PCI_D3cold);
3051
3052 return 0;
3053}
3054
3055static int
3056jme_resume(struct pci_dev *pdev)
3057{
3058 struct net_device *netdev = pci_get_drvdata(pdev);
3059 struct jme_adapter *jme = netdev_priv(netdev);
3060
3061 jme_clear_pm(jme);
3062 pci_restore_state(pdev);
3063
3064 if (test_bit(JME_FLAG_SSET, &jme->flags))
3065 jme_set_settings(netdev, &jme->old_ecmd);
3066 else
3067 jme_reset_phy_processor(jme);
3068
3069 jme_enable_shadow(jme);
3070 jme_start_irq(jme);
3071 netif_device_attach(netdev);
3072
3073 atomic_inc(&jme->link_changing);
3074
3075 jme_reset_link(jme);
3076
3077 return 0;
3078}
3079#endif
3080
3081static struct pci_device_id jme_pci_tbl[] = {
3082 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3083 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3084 { }
3085};
3086
3087static struct pci_driver jme_driver = {
3088 .name = DRV_NAME,
3089 .id_table = jme_pci_tbl,
3090 .probe = jme_init_one,
3091 .remove = __devexit_p(jme_remove_one),
3092#ifdef CONFIG_PM
3093 .suspend = jme_suspend,
3094 .resume = jme_resume,
3095#endif /* CONFIG_PM */
3096};
3097
3098static int __init
3099jme_init_module(void)
3100{
3101 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3102 "driver version %s\n", DRV_VERSION);
3103 return pci_register_driver(&jme_driver);
3104}
3105
3106static void __exit
3107jme_cleanup_module(void)
3108{
3109 pci_unregister_driver(&jme_driver);
3110}
3111
3112module_init(jme_init_module);
3113module_exit(jme_cleanup_module);
3114
3115MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3116MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3117MODULE_LICENSE("GPL");
3118MODULE_VERSION(DRV_VERSION);
3119MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3120
JMicron Ethernet Linux driver