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4330c2f2 GFT |
1 | /* |
2 | * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver | |
3 | * | |
4 | * Copyright 2008 JMicron Technology Corporation | |
5 | * http://www.jmicron.com/ | |
6 | * | |
3bf61c55 GFT |
7 | * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> |
8 | * | |
4330c2f2 GFT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/version.h> | |
d7699f87 GFT |
25 | |
26 | #define DRV_NAME "jme" | |
8d27293f | 27 | #define DRV_VERSION "0.9d" |
d7699f87 GFT |
28 | #define PFX DRV_NAME ": " |
29 | ||
8d27293f GFT |
30 | #define JME_GE_DEVICE 0x250 |
31 | #define JME_FE_DEVICE 0x260 | |
32 | ||
d7699f87 | 33 | #ifdef DEBUG |
4330c2f2 | 34 | #define dprintk(devname, fmt, args...) \ |
8c198884 | 35 | printk(KERN_DEBUG "%s: " fmt, devname, ## args) |
d7699f87 | 36 | #else |
4330c2f2 | 37 | #define dprintk(devname, fmt, args...) |
d7699f87 GFT |
38 | #endif |
39 | ||
3bf61c55 GFT |
40 | #ifdef TX_DEBUG |
41 | #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
42 | #else | |
43 | #define tx_dbg(args...) | |
44 | #endif | |
45 | ||
46 | #ifdef RX_DEBUG | |
47 | #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
48 | #else | |
49 | #define rx_dbg(args...) | |
50 | #endif | |
51 | ||
29bdd921 GFT |
52 | #ifdef QUEUE_DEBUG |
53 | #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
54 | #else | |
55 | #define queue_dbg(args...) | |
56 | #endif | |
57 | ||
79ce639c GFT |
58 | #ifdef CSUM_DEBUG |
59 | #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
60 | #else | |
61 | #define csum_dbg(args...) | |
62 | #endif | |
63 | ||
b3821cc5 GFT |
64 | #ifdef VLAN_DEBUG |
65 | #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
66 | #else | |
67 | #define vlan_dbg(args...) | |
68 | #endif | |
69 | ||
4330c2f2 | 70 | #define jprintk(devname, fmt, args...) \ |
8c198884 | 71 | printk(KERN_INFO "%s: " fmt, devname, ## args) |
4330c2f2 GFT |
72 | |
73 | #define jeprintk(devname, fmt, args...) \ | |
8c198884 | 74 | printk(KERN_ERR "%s: " fmt, devname, ## args) |
4330c2f2 | 75 | |
d7699f87 GFT |
76 | #define DEFAULT_MSG_ENABLE \ |
77 | (NETIF_MSG_DRV | \ | |
78 | NETIF_MSG_PROBE | \ | |
79 | NETIF_MSG_LINK | \ | |
80 | NETIF_MSG_TIMER | \ | |
81 | NETIF_MSG_RX_ERR | \ | |
82 | NETIF_MSG_TX_ERR) | |
83 | ||
4330c2f2 GFT |
84 | #define PCI_CONF_DCSR_MRRS 0x59 |
85 | #define PCI_CONF_DCSR_MRRS_MASK 0x70 | |
86 | enum pci_conf_dcsr_mrrs_vals { | |
87 | MRRS_128B = 0x00, | |
88 | MRRS_256B = 0x10, | |
89 | MRRS_512B = 0x20, | |
90 | MRRS_1024B = 0x30, | |
91 | MRRS_2048B = 0x40, | |
92 | MRRS_4096B = 0x50, | |
93 | }; | |
d7699f87 | 94 | |
79ce639c GFT |
95 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 |
96 | #define MIN_ETHERNET_PACKET_SIZE 60 | |
97 | ||
3bf61c55 | 98 | enum dynamic_pcc_values { |
192570e0 | 99 | PCC_OFF = 0, |
3bf61c55 GFT |
100 | PCC_P1 = 1, |
101 | PCC_P2 = 2, | |
102 | PCC_P3 = 3, | |
103 | ||
192570e0 | 104 | PCC_OFF_TO = 0, |
3bf61c55 | 105 | PCC_P1_TO = 1, |
192570e0 GFT |
106 | PCC_P2_TO = 64, |
107 | PCC_P3_TO = 128, | |
3bf61c55 | 108 | |
192570e0 | 109 | PCC_OFF_CNT = 0, |
3bf61c55 | 110 | PCC_P1_CNT = 1, |
192570e0 GFT |
111 | PCC_P2_CNT = 16, |
112 | PCC_P3_CNT = 32, | |
3bf61c55 GFT |
113 | }; |
114 | struct dynpcc_info { | |
3bf61c55 GFT |
115 | unsigned long last_bytes; |
116 | unsigned long last_pkts; | |
79ce639c | 117 | unsigned long intr_cnt; |
3bf61c55 GFT |
118 | unsigned char cur; |
119 | unsigned char attempt; | |
120 | unsigned char cnt; | |
121 | }; | |
79ce639c GFT |
122 | #define PCC_INTERVAL_US 100000 |
123 | #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) | |
cdcdc9eb | 124 | #define PCC_P3_THRESHOLD 2*1024*1024 |
79ce639c GFT |
125 | #define PCC_P2_THRESHOLD 800 |
126 | #define PCC_INTR_THRESHOLD 800 | |
b3821cc5 GFT |
127 | #define PCC_TX_TO 333 |
128 | #define PCC_TX_CNT 8 | |
3bf61c55 | 129 | |
d7699f87 GFT |
130 | /* |
131 | * TX/RX Descriptors | |
4330c2f2 GFT |
132 | * |
133 | * TX/RX Ring DESC Count Must be multiple of 16 | |
134 | * RX Ring DESC Count Must be <= 1024 | |
d7699f87 | 135 | */ |
4330c2f2 GFT |
136 | #define RING_DESC_ALIGN 16 /* Descriptor alignment */ |
137 | ||
d7699f87 GFT |
138 | #define TX_DESC_SIZE 16 |
139 | #define TX_RING_NR 8 | |
b3821cc5 | 140 | #define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN |
d7699f87 | 141 | |
3bf61c55 | 142 | struct txdesc { |
d7699f87 GFT |
143 | union { |
144 | __u8 all[16]; | |
145 | __u32 dw[4]; | |
146 | struct { | |
147 | /* DW0 */ | |
148 | __u16 vlan; | |
149 | __u8 rsv1; | |
150 | __u8 flags; | |
151 | ||
152 | /* DW1 */ | |
153 | __u16 datalen; | |
154 | __u16 mss; | |
155 | ||
156 | /* DW2 */ | |
157 | __u16 pktsize; | |
158 | __u16 rsv2; | |
159 | ||
160 | /* DW3 */ | |
161 | __u32 bufaddr; | |
162 | } desc1; | |
3bf61c55 GFT |
163 | struct { |
164 | /* DW0 */ | |
165 | __u16 rsv1; | |
166 | __u8 rsv2; | |
167 | __u8 flags; | |
168 | ||
169 | /* DW1 */ | |
170 | __u16 datalen; | |
171 | __u16 rsv3; | |
172 | ||
173 | /* DW2 */ | |
174 | __u32 bufaddrh; | |
175 | ||
176 | /* DW3 */ | |
177 | __u32 bufaddrl; | |
178 | } desc2; | |
8c198884 GFT |
179 | struct { |
180 | /* DW0 */ | |
181 | __u8 ehdrsz; | |
182 | __u8 rsv1; | |
183 | __u8 rsv2; | |
184 | __u8 flags; | |
185 | ||
186 | /* DW1 */ | |
187 | __u16 trycnt; | |
188 | __u16 segcnt; | |
189 | ||
190 | /* DW2 */ | |
191 | __u16 pktsz; | |
192 | __u16 rsv3; | |
193 | ||
194 | /* DW3 */ | |
195 | __u32 bufaddrl; | |
196 | } descwb; | |
d7699f87 GFT |
197 | }; |
198 | }; | |
8c198884 | 199 | enum jme_txdesc_flags_bits { |
d7699f87 GFT |
200 | TXFLAG_OWN = 0x80, |
201 | TXFLAG_INT = 0x40, | |
3bf61c55 | 202 | TXFLAG_64BIT = 0x20, |
d7699f87 GFT |
203 | TXFLAG_TCPCS = 0x10, |
204 | TXFLAG_UDPCS = 0x08, | |
205 | TXFLAG_IPCS = 0x04, | |
206 | TXFLAG_LSEN = 0x02, | |
207 | TXFLAG_TAGON = 0x01, | |
208 | }; | |
b3821cc5 | 209 | #define TXDESC_MSS_SHIFT 2 |
8c198884 GFT |
210 | enum jme_rxdescwb_flags_bits { |
211 | TXWBFLAG_OWN = 0x80, | |
212 | TXWBFLAG_INT = 0x40, | |
213 | TXWBFLAG_TMOUT = 0x20, | |
214 | TXWBFLAG_TRYOUT = 0x10, | |
215 | TXWBFLAG_COL = 0x08, | |
216 | ||
217 | TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | | |
218 | TXWBFLAG_TRYOUT | | |
219 | TXWBFLAG_COL, | |
220 | }; | |
d7699f87 GFT |
221 | |
222 | ||
223 | #define RX_DESC_SIZE 16 | |
224 | #define RX_RING_NR 4 | |
b3821cc5 | 225 | #define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN |
d7699f87 GFT |
226 | |
227 | #define RX_BUF_DMA_ALIGN 8 | |
3bf61c55 | 228 | #define RX_PREPAD_SIZE 10 |
79ce639c GFT |
229 | #define ETH_CRC_LEN 2 |
230 | #define RX_VLANHDR_LEN 2 | |
231 | #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ | |
232 | ETH_HLEN + \ | |
233 | ETH_CRC_LEN + \ | |
234 | RX_VLANHDR_LEN + \ | |
235 | RX_BUF_DMA_ALIGN) | |
d7699f87 | 236 | |
3bf61c55 | 237 | struct rxdesc { |
d7699f87 GFT |
238 | union { |
239 | __u8 all[16]; | |
240 | __le32 dw[4]; | |
241 | struct { | |
242 | /* DW0 */ | |
243 | __le16 rsv2; | |
244 | __u8 rsv1; | |
245 | __u8 flags; | |
246 | ||
247 | /* DW1 */ | |
248 | __le16 datalen; | |
249 | __le16 wbcpl; | |
250 | ||
251 | /* DW2 */ | |
252 | __le32 bufaddrh; | |
253 | ||
254 | /* DW3 */ | |
255 | __le32 bufaddrl; | |
256 | } desc1; | |
257 | struct { | |
258 | /* DW0 */ | |
259 | __le16 vlan; | |
260 | __le16 flags; | |
261 | ||
262 | /* DW1 */ | |
263 | __le16 framesize; | |
4330c2f2 | 264 | __u8 errstat; |
d7699f87 GFT |
265 | __u8 desccnt; |
266 | ||
267 | /* DW2 */ | |
268 | __le32 rsshash; | |
269 | ||
270 | /* DW3 */ | |
3bf61c55 GFT |
271 | __u8 hashfun; |
272 | __u8 hashtype; | |
d7699f87 GFT |
273 | __le16 resrv; |
274 | } descwb; | |
275 | }; | |
276 | }; | |
277 | enum jme_rxdesc_flags_bits { | |
278 | RXFLAG_OWN = 0x80, | |
279 | RXFLAG_INT = 0x40, | |
280 | RXFLAG_64BIT = 0x20, | |
281 | }; | |
282 | enum jme_rxwbdesc_flags_bits { | |
4330c2f2 GFT |
283 | RXWBFLAG_OWN = 0x8000, |
284 | RXWBFLAG_INT = 0x4000, | |
285 | RXWBFLAG_MF = 0x2000, | |
286 | RXWBFLAG_64BIT = 0x2000, | |
287 | RXWBFLAG_TCPON = 0x1000, | |
288 | RXWBFLAG_UDPON = 0x0800, | |
289 | RXWBFLAG_IPCS = 0x0400, | |
290 | RXWBFLAG_TCPCS = 0x0200, | |
291 | RXWBFLAG_UDPCS = 0x0100, | |
292 | RXWBFLAG_TAGON = 0x0080, | |
293 | RXWBFLAG_IPV4 = 0x0040, | |
294 | RXWBFLAG_IPV6 = 0x0020, | |
295 | RXWBFLAG_PAUSE = 0x0010, | |
296 | RXWBFLAG_MAGIC = 0x0008, | |
297 | RXWBFLAG_WAKEUP = 0x0004, | |
298 | RXWBFLAG_DEST = 0x0003, | |
299 | RXWBFLAG_DEST_UNI = 0x0001, | |
300 | RXWBFLAG_DEST_MUL = 0x0002, | |
301 | RXWBFLAG_DEST_BRO = 0x0003, | |
d7699f87 GFT |
302 | }; |
303 | enum jme_rxwbdesc_desccnt_mask { | |
304 | RXWBDCNT_WBCPL = 0x80, | |
305 | RXWBDCNT_DCNT = 0x7F, | |
306 | }; | |
4330c2f2 GFT |
307 | enum jme_rxwbdesc_errstat_bits { |
308 | RXWBERR_LIMIT = 0x80, | |
309 | RXWBERR_MIIER = 0x40, | |
310 | RXWBERR_NIBON = 0x20, | |
311 | RXWBERR_COLON = 0x10, | |
312 | RXWBERR_ABORT = 0x08, | |
313 | RXWBERR_SHORT = 0x04, | |
314 | RXWBERR_OVERUN = 0x02, | |
315 | RXWBERR_CRCERR = 0x01, | |
316 | RXWBERR_ALLERR = 0xFF, | |
317 | }; | |
318 | ||
319 | struct jme_buffer_info { | |
320 | struct sk_buff *skb; | |
321 | dma_addr_t mapping; | |
322 | int len; | |
3bf61c55 | 323 | int nr_desc; |
cdcdc9eb | 324 | unsigned long start_xmit; |
4330c2f2 | 325 | }; |
d7699f87 | 326 | |
b3821cc5 | 327 | #define MAX_RING_DESC_NR 1024 |
d7699f87 | 328 | struct jme_ring { |
4330c2f2 | 329 | void* alloc; /* pointer to allocated memory */ |
3bf61c55 | 330 | volatile void* desc; /* pointer to ring memory */ |
d7699f87 GFT |
331 | dma_addr_t dmaalloc; /* phys address of ring alloc */ |
332 | dma_addr_t dma; /* phys address for ring dma */ | |
333 | ||
4330c2f2 | 334 | /* Buffer information corresponding to each descriptor */ |
b3821cc5 | 335 | struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; |
d7699f87 | 336 | |
b3821cc5 | 337 | int next_to_use; |
cdcdc9eb | 338 | atomic_t next_to_clean; |
79ce639c | 339 | atomic_t nr_free; |
d7699f87 GFT |
340 | }; |
341 | ||
3bf61c55 GFT |
342 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) |
343 | #define NET_STAT(priv) priv->stats | |
344 | #define NETDEV_GET_STATS(netdev, fun_ptr) \ | |
345 | netdev->get_stats = fun_ptr | |
346 | #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; | |
347 | #else | |
348 | #define NET_STAT(priv) priv->dev->stats | |
349 | #define NETDEV_GET_STATS(netdev, fun_ptr) | |
350 | #define DECLARE_NET_DEVICE_STATS | |
351 | #endif | |
352 | ||
cdcdc9eb GFT |
353 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
354 | #define DECLARE_NAPI_STRUCT | |
355 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
356 | dev->poll = pollfn; \ | |
357 | dev->weight = q; | |
358 | #define JME_NAPI_HOLDER(holder) struct net_device *holder | |
359 | #define JME_NAPI_WEIGHT(w) int *w | |
360 | #define JME_NAPI_WEIGHT_VAL(w) *w | |
361 | #define JME_NAPI_WEIGHT_SET(w, r) *w = r | |
362 | #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) | |
363 | #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); | |
364 | #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); | |
365 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
366 | netif_rx_schedule_prep(priv->dev) | |
367 | #define JME_RX_SCHEDULE(priv) \ | |
368 | __netif_rx_schedule(priv->dev); | |
369 | #else | |
370 | #define DECLARE_NAPI_STRUCT struct napi_struct napi; | |
371 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
372 | netif_napi_add(dev, napis, pollfn, q); | |
373 | #define JME_NAPI_HOLDER(holder) struct napi_struct *holder | |
374 | #define JME_NAPI_WEIGHT(w) int w | |
375 | #define JME_NAPI_WEIGHT_VAL(w) w | |
376 | #define JME_NAPI_WEIGHT_SET(w, r) | |
377 | #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis) | |
378 | #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); | |
379 | #define JME_NAPI_DISABLE(priv) \ | |
380 | if(!napi_disable_pending(&priv->napi)) \ | |
381 | napi_disable(&priv->napi); | |
382 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
383 | netif_rx_schedule_prep(priv->dev, &priv->napi) | |
384 | #define JME_RX_SCHEDULE(priv) \ | |
385 | __netif_rx_schedule(priv->dev, &priv->napi); | |
386 | #endif | |
387 | ||
d7699f87 GFT |
388 | /* |
389 | * Jmac Adapter Private data | |
390 | */ | |
4330c2f2 | 391 | #define SHADOW_REG_NR 8 |
d7699f87 GFT |
392 | struct jme_adapter { |
393 | struct pci_dev *pdev; | |
394 | struct net_device *dev; | |
395 | void __iomem *regs; | |
4330c2f2 GFT |
396 | dma_addr_t shadow_dma; |
397 | __u32 *shadow_regs; | |
d7699f87 GFT |
398 | struct mii_if_info mii_if; |
399 | struct jme_ring rxring[RX_RING_NR]; | |
400 | struct jme_ring txring[TX_RING_NR]; | |
d7699f87 | 401 | spinlock_t phy_lock; |
fcf45b4c | 402 | spinlock_t macaddr_lock; |
8c198884 | 403 | spinlock_t rxmcs_lock; |
fcf45b4c | 404 | struct tasklet_struct rxempty_task; |
4330c2f2 GFT |
405 | struct tasklet_struct rxclean_task; |
406 | struct tasklet_struct txclean_task; | |
407 | struct tasklet_struct linkch_task; | |
79ce639c GFT |
408 | struct tasklet_struct pcc_task; |
409 | __u32 flags; | |
4330c2f2 | 410 | __u32 reg_txcs; |
8c198884 | 411 | __u32 reg_txpfc; |
79ce639c | 412 | __u32 reg_rxcs; |
3bf61c55 GFT |
413 | __u32 reg_rxmcs; |
414 | __u32 reg_ghc; | |
29bdd921 | 415 | __u32 reg_pmcs; |
fcf45b4c | 416 | __u32 phylink; |
b3821cc5 GFT |
417 | __u32 tx_ring_size; |
418 | __u32 tx_ring_mask; | |
419 | __u32 tx_wake_threshold; | |
420 | __u32 rx_ring_size; | |
421 | __u32 rx_ring_mask; | |
fcf45b4c | 422 | __u8 mrrs; |
cdcdc9eb GFT |
423 | __u32 fpgaver; |
424 | __u32 chipver; | |
29bdd921 GFT |
425 | struct ethtool_cmd old_ecmd; |
426 | unsigned int old_mtu; | |
42b1055e | 427 | struct vlan_group* vlgrp; |
3bf61c55 GFT |
428 | struct dynpcc_info dpi; |
429 | atomic_t intr_sem; | |
fcf45b4c GFT |
430 | atomic_t link_changing; |
431 | atomic_t tx_cleaning; | |
432 | atomic_t rx_cleaning; | |
192570e0 | 433 | atomic_t rx_empty; |
cdcdc9eb GFT |
434 | int (*jme_rx)(struct sk_buff *skb); |
435 | int (*jme_vlan_rx)(struct sk_buff *skb, | |
436 | struct vlan_group *grp, | |
437 | unsigned short vlan_tag); | |
438 | DECLARE_NAPI_STRUCT | |
3bf61c55 | 439 | DECLARE_NET_DEVICE_STATS |
d7699f87 | 440 | }; |
4330c2f2 GFT |
441 | enum shadow_reg_val { |
442 | SHADOW_IEVE = 0, | |
443 | }; | |
79ce639c GFT |
444 | enum jme_flags_bits { |
445 | JME_FLAG_MSI = 0x00000001, | |
29bdd921 | 446 | JME_FLAG_SSET = 0x00000002, |
b3821cc5 GFT |
447 | JME_FLAG_TXCSUM = 0x00000004, |
448 | JME_FLAG_TSO = 0x00000008, | |
192570e0 | 449 | JME_FLAG_POLL = 0x00000010, |
8c198884 | 450 | }; |
fcf45b4c | 451 | #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ |
8c198884 | 452 | #define TX_TIMEOUT (5*HZ) |
186fc259 | 453 | #define JME_REG_LEN 0x500 |
8c198884 | 454 | |
cdcdc9eb GFT |
455 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
456 | __always_inline static struct jme_adapter* | |
457 | jme_napi_priv(struct net_device *holder) | |
458 | { | |
459 | struct jme_adapter* jme; | |
460 | jme = netdev_priv(holder); | |
461 | return jme; | |
462 | } | |
463 | #else | |
464 | __always_inline static struct jme_adapter* | |
465 | jme_napi_priv(struct napi_struct *napi) | |
466 | { | |
467 | struct jme_adapter* jme; | |
468 | jme = container_of(napi, struct jme_adapter, napi); | |
469 | return jme; | |
470 | } | |
471 | #endif | |
d7699f87 GFT |
472 | |
473 | /* | |
474 | * MMaped I/O Resters | |
475 | */ | |
476 | enum jme_iomap_offsets { | |
4330c2f2 GFT |
477 | JME_MAC = 0x0000, |
478 | JME_PHY = 0x0400, | |
d7699f87 | 479 | JME_MISC = 0x0800, |
4330c2f2 | 480 | JME_RSS = 0x0C00, |
d7699f87 GFT |
481 | }; |
482 | ||
8c198884 GFT |
483 | enum jme_iomap_lens { |
484 | JME_MAC_LEN = 0x80, | |
485 | JME_PHY_LEN = 0x58, | |
486 | JME_MISC_LEN = 0x98, | |
487 | JME_RSS_LEN = 0xFF, | |
488 | }; | |
489 | ||
d7699f87 GFT |
490 | enum jme_iomap_regs { |
491 | JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ | |
3bf61c55 GFT |
492 | JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ |
493 | JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */ | |
d7699f87 GFT |
494 | JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */ |
495 | JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */ | |
496 | JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */ | |
497 | JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */ | |
498 | JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */ | |
499 | ||
500 | JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */ | |
3bf61c55 GFT |
501 | JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */ |
502 | JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */ | |
d7699f87 GFT |
503 | JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */ |
504 | JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */ | |
505 | JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */ | |
4330c2f2 GFT |
506 | JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */ |
507 | JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */ | |
3bf61c55 GFT |
508 | JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */ |
509 | JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */ | |
d7699f87 GFT |
510 | JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */ |
511 | JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */ | |
512 | ||
513 | JME_SMI = JME_MAC | 0x50, /* Station Management Interface */ | |
514 | JME_GHC = JME_MAC | 0x54, /* Global Host Control */ | |
515 | JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */ | |
516 | ||
517 | ||
3bf61c55 | 518 | JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ |
d7699f87 GFT |
519 | JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ |
520 | JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ | |
186fc259 | 521 | JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ |
d7699f87 GFT |
522 | |
523 | ||
79ce639c | 524 | JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ |
4330c2f2 GFT |
525 | JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */ |
526 | JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */ | |
d7699f87 | 527 | JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */ |
3bf61c55 | 528 | JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */ |
d7699f87 | 529 | JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */ |
3bf61c55 GFT |
530 | JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */ |
531 | JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */ | |
532 | JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */ | |
cdcdc9eb | 533 | JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */ |
4330c2f2 GFT |
534 | JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */ |
535 | JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */ | |
3bf61c55 | 536 | JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */ |
d7699f87 GFT |
537 | }; |
538 | ||
539 | /* | |
540 | * TX Control/Status Bits | |
541 | */ | |
542 | enum jme_txcs_bits { | |
543 | TXCS_QUEUE7S = 0x00008000, | |
544 | TXCS_QUEUE6S = 0x00004000, | |
545 | TXCS_QUEUE5S = 0x00002000, | |
546 | TXCS_QUEUE4S = 0x00001000, | |
547 | TXCS_QUEUE3S = 0x00000800, | |
548 | TXCS_QUEUE2S = 0x00000400, | |
549 | TXCS_QUEUE1S = 0x00000200, | |
550 | TXCS_QUEUE0S = 0x00000100, | |
551 | TXCS_FIFOTH = 0x000000C0, | |
552 | TXCS_DMASIZE = 0x00000030, | |
553 | TXCS_BURST = 0x00000004, | |
554 | TXCS_ENABLE = 0x00000001, | |
555 | }; | |
556 | enum jme_txcs_value { | |
557 | TXCS_FIFOTH_16QW = 0x000000C0, | |
558 | TXCS_FIFOTH_12QW = 0x00000080, | |
559 | TXCS_FIFOTH_8QW = 0x00000040, | |
560 | TXCS_FIFOTH_4QW = 0x00000000, | |
561 | ||
562 | TXCS_DMASIZE_64B = 0x00000000, | |
563 | TXCS_DMASIZE_128B = 0x00000010, | |
564 | TXCS_DMASIZE_256B = 0x00000020, | |
565 | TXCS_DMASIZE_512B = 0x00000030, | |
566 | ||
567 | TXCS_SELECT_QUEUE0 = 0x00000000, | |
568 | TXCS_SELECT_QUEUE1 = 0x00010000, | |
569 | TXCS_SELECT_QUEUE2 = 0x00020000, | |
570 | TXCS_SELECT_QUEUE3 = 0x00030000, | |
571 | TXCS_SELECT_QUEUE4 = 0x00040000, | |
572 | TXCS_SELECT_QUEUE5 = 0x00050000, | |
573 | TXCS_SELECT_QUEUE6 = 0x00060000, | |
574 | TXCS_SELECT_QUEUE7 = 0x00070000, | |
575 | ||
576 | TXCS_DEFAULT = TXCS_FIFOTH_4QW | | |
d7699f87 GFT |
577 | TXCS_BURST, |
578 | }; | |
29bdd921 | 579 | #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
580 | |
581 | /* | |
582 | * TX MAC Control/Status Bits | |
583 | */ | |
584 | enum jme_txmcs_bit_masks { | |
585 | TXMCS_IFG2 = 0xC0000000, | |
586 | TXMCS_IFG1 = 0x30000000, | |
587 | TXMCS_TTHOLD = 0x00000300, | |
588 | TXMCS_FBURST = 0x00000080, | |
589 | TXMCS_CARRIEREXT = 0x00000040, | |
590 | TXMCS_DEFER = 0x00000020, | |
591 | TXMCS_BACKOFF = 0x00000010, | |
592 | TXMCS_CARRIERSENSE = 0x00000008, | |
593 | TXMCS_COLLISION = 0x00000004, | |
594 | TXMCS_CRC = 0x00000002, | |
595 | TXMCS_PADDING = 0x00000001, | |
596 | }; | |
597 | enum jme_txmcs_values { | |
598 | TXMCS_IFG2_6_4 = 0x00000000, | |
599 | TXMCS_IFG2_8_5 = 0x40000000, | |
600 | TXMCS_IFG2_10_6 = 0x80000000, | |
601 | TXMCS_IFG2_12_7 = 0xC0000000, | |
602 | ||
603 | TXMCS_IFG1_8_4 = 0x00000000, | |
604 | TXMCS_IFG1_12_6 = 0x10000000, | |
605 | TXMCS_IFG1_16_8 = 0x20000000, | |
606 | TXMCS_IFG1_20_10 = 0x30000000, | |
607 | ||
608 | TXMCS_TTHOLD_1_8 = 0x00000000, | |
609 | TXMCS_TTHOLD_1_4 = 0x00000100, | |
610 | TXMCS_TTHOLD_1_2 = 0x00000200, | |
611 | TXMCS_TTHOLD_FULL = 0x00000300, | |
612 | ||
613 | TXMCS_DEFAULT = TXMCS_IFG2_8_5 | | |
614 | TXMCS_IFG1_16_8 | | |
615 | TXMCS_TTHOLD_FULL | | |
616 | TXMCS_DEFER | | |
617 | TXMCS_CRC | | |
618 | TXMCS_PADDING, | |
619 | }; | |
620 | ||
8c198884 GFT |
621 | enum jme_txpfc_bits_masks { |
622 | TXPFC_VLAN_TAG = 0xFFFF0000, | |
623 | TXPFC_VLAN_EN = 0x00008000, | |
624 | TXPFC_PF_EN = 0x00000001, | |
625 | }; | |
626 | ||
627 | enum jme_txtrhd_bits_masks { | |
628 | TXTRHD_TXPEN = 0x80000000, | |
629 | TXTRHD_TXP = 0x7FFFFF00, | |
630 | TXTRHD_TXREN = 0x00000080, | |
631 | TXTRHD_TXRL = 0x0000007F, | |
632 | }; | |
633 | enum jme_txtrhd_shifts { | |
634 | TXTRHD_TXP_SHIFT = 8, | |
635 | TXTRHD_TXRL_SHIFT = 0, | |
636 | }; | |
637 | ||
d7699f87 GFT |
638 | |
639 | /* | |
640 | * RX Control/Status Bits | |
641 | */ | |
4330c2f2 | 642 | enum jme_rxcs_bit_masks { |
3bf61c55 GFT |
643 | /* FIFO full threshold for transmitting Tx Pause Packet */ |
644 | RXCS_FIFOTHTP = 0x30000000, | |
645 | /* FIFO threshold for processing next packet */ | |
646 | RXCS_FIFOTHNP = 0x0C000000, | |
4330c2f2 GFT |
647 | RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */ |
648 | RXCS_QUEUESEL = 0x00030000, /* Queue selection */ | |
649 | RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */ | |
650 | RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */ | |
651 | RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */ | |
652 | RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */ | |
653 | RXCS_SHORT = 0x00000010, /* Enable receive short packet */ | |
654 | RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */ | |
655 | RXCS_QST = 0x00000004, /* Receive queue start */ | |
656 | RXCS_SUSPEND = 0x00000002, | |
d7699f87 GFT |
657 | RXCS_ENABLE = 0x00000001, |
658 | }; | |
4330c2f2 GFT |
659 | enum jme_rxcs_values { |
660 | RXCS_FIFOTHTP_16T = 0x00000000, | |
661 | RXCS_FIFOTHTP_32T = 0x10000000, | |
662 | RXCS_FIFOTHTP_64T = 0x20000000, | |
663 | RXCS_FIFOTHTP_128T = 0x30000000, | |
664 | ||
665 | RXCS_FIFOTHNP_16QW = 0x00000000, | |
666 | RXCS_FIFOTHNP_32QW = 0x04000000, | |
667 | RXCS_FIFOTHNP_64QW = 0x08000000, | |
668 | RXCS_FIFOTHNP_128QW = 0x0C000000, | |
669 | ||
670 | RXCS_DMAREQSZ_16B = 0x00000000, | |
671 | RXCS_DMAREQSZ_32B = 0x01000000, | |
672 | RXCS_DMAREQSZ_64B = 0x02000000, | |
673 | RXCS_DMAREQSZ_128B = 0x03000000, | |
674 | ||
675 | RXCS_QUEUESEL_Q0 = 0x00000000, | |
676 | RXCS_QUEUESEL_Q1 = 0x00010000, | |
677 | RXCS_QUEUESEL_Q2 = 0x00020000, | |
678 | RXCS_QUEUESEL_Q3 = 0x00030000, | |
679 | ||
680 | RXCS_RETRYGAP_256ns = 0x00000000, | |
681 | RXCS_RETRYGAP_512ns = 0x00001000, | |
682 | RXCS_RETRYGAP_1024ns = 0x00002000, | |
683 | RXCS_RETRYGAP_2048ns = 0x00003000, | |
684 | RXCS_RETRYGAP_4096ns = 0x00004000, | |
685 | RXCS_RETRYGAP_8192ns = 0x00005000, | |
686 | RXCS_RETRYGAP_16384ns = 0x00006000, | |
687 | RXCS_RETRYGAP_32768ns = 0x00007000, | |
688 | ||
689 | RXCS_RETRYCNT_0 = 0x00000000, | |
690 | RXCS_RETRYCNT_4 = 0x00000100, | |
691 | RXCS_RETRYCNT_8 = 0x00000200, | |
692 | RXCS_RETRYCNT_12 = 0x00000300, | |
693 | RXCS_RETRYCNT_16 = 0x00000400, | |
694 | RXCS_RETRYCNT_20 = 0x00000500, | |
695 | RXCS_RETRYCNT_24 = 0x00000600, | |
696 | RXCS_RETRYCNT_28 = 0x00000700, | |
697 | RXCS_RETRYCNT_32 = 0x00000800, | |
698 | RXCS_RETRYCNT_36 = 0x00000900, | |
699 | RXCS_RETRYCNT_40 = 0x00000A00, | |
700 | RXCS_RETRYCNT_44 = 0x00000B00, | |
701 | RXCS_RETRYCNT_48 = 0x00000C00, | |
702 | RXCS_RETRYCNT_52 = 0x00000D00, | |
703 | RXCS_RETRYCNT_56 = 0x00000E00, | |
704 | RXCS_RETRYCNT_60 = 0x00000F00, | |
705 | ||
706 | RXCS_DEFAULT = RXCS_FIFOTHTP_128T | | |
79ce639c | 707 | RXCS_FIFOTHNP_128QW | |
4330c2f2 GFT |
708 | RXCS_DMAREQSZ_128B | |
709 | RXCS_RETRYGAP_256ns | | |
710 | RXCS_RETRYCNT_32, | |
711 | }; | |
29bdd921 | 712 | #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
713 | |
714 | /* | |
715 | * RX MAC Control/Status Bits | |
716 | */ | |
717 | enum jme_rxmcs_bits { | |
718 | RXMCS_ALLFRAME = 0x00000800, | |
719 | RXMCS_BRDFRAME = 0x00000400, | |
720 | RXMCS_MULFRAME = 0x00000200, | |
721 | RXMCS_UNIFRAME = 0x00000100, | |
722 | RXMCS_ALLMULFRAME = 0x00000080, | |
723 | RXMCS_MULFILTERED = 0x00000040, | |
3bf61c55 GFT |
724 | RXMCS_RXCOLLDEC = 0x00000020, |
725 | RXMCS_FLOWCTRL = 0x00000008, | |
726 | RXMCS_VTAGRM = 0x00000004, | |
727 | RXMCS_PREPAD = 0x00000002, | |
728 | RXMCS_CHECKSUM = 0x00000001, | |
b3821cc5 | 729 | |
8c198884 GFT |
730 | RXMCS_DEFAULT = RXMCS_VTAGRM | |
731 | RXMCS_PREPAD | | |
732 | RXMCS_FLOWCTRL | | |
733 | RXMCS_CHECKSUM, | |
d7699f87 GFT |
734 | }; |
735 | ||
b3821cc5 GFT |
736 | /* |
737 | * Wakeup Frame setup interface registers | |
738 | */ | |
739 | #define WAKEUP_FRAME_NR 8 | |
740 | #define WAKEUP_FRAME_MASK_DWNR 4 | |
741 | enum jme_wfoi_bit_masks { | |
742 | WFOI_MASK_SEL = 0x00000070, | |
743 | WFOI_CRC_SEL = 0x00000008, | |
744 | WFOI_FRAME_SEL = 0x00000007, | |
745 | }; | |
746 | enum jme_wfoi_shifts { | |
747 | WFOI_MASK_SHIFT = 4, | |
748 | }; | |
749 | ||
d7699f87 GFT |
750 | /* |
751 | * SMI Related definitions | |
752 | */ | |
753 | enum jme_smi_bit_mask | |
754 | { | |
755 | SMI_DATA_MASK = 0xFFFF0000, | |
756 | SMI_REG_ADDR_MASK = 0x0000F800, | |
757 | SMI_PHY_ADDR_MASK = 0x000007C0, | |
758 | SMI_OP_WRITE = 0x00000020, | |
3bf61c55 GFT |
759 | /* Set to 1, after req done it'll be cleared to 0 */ |
760 | SMI_OP_REQ = 0x00000010, | |
d7699f87 GFT |
761 | SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */ |
762 | SMI_OP_MDOE = 0x00000004, /* Software Output Enable */ | |
763 | SMI_OP_MDC = 0x00000002, /* Software CLK Control */ | |
764 | SMI_OP_MDEN = 0x00000001, /* Software access Enable */ | |
765 | }; | |
766 | enum jme_smi_bit_shift | |
767 | { | |
768 | SMI_DATA_SHIFT = 16, | |
769 | SMI_REG_ADDR_SHIFT = 11, | |
770 | SMI_PHY_ADDR_SHIFT = 6, | |
771 | }; | |
772 | __always_inline __u32 smi_reg_addr(int x) | |
773 | { | |
774 | return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK); | |
775 | } | |
776 | __always_inline __u32 smi_phy_addr(int x) | |
777 | { | |
778 | return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK); | |
779 | } | |
8d27293f | 780 | #define JME_PHY_TIMEOUT 100 /* 100 msec */ |
186fc259 | 781 | #define JME_PHY_REG_NR 32 |
d7699f87 GFT |
782 | |
783 | /* | |
784 | * Global Host Control | |
785 | */ | |
786 | enum jme_ghc_bit_mask { | |
787 | GHC_SWRST = 0x40000000, | |
788 | GHC_DPX = 0x00000040, | |
789 | GHC_SPEED = 0x00000030, | |
790 | GHC_LINK_POLL = 0x00000001, | |
791 | }; | |
792 | enum jme_ghc_speed_val { | |
793 | GHC_SPEED_10M = 0x00000010, | |
794 | GHC_SPEED_100M = 0x00000020, | |
795 | GHC_SPEED_1000M = 0x00000030, | |
796 | }; | |
797 | ||
29bdd921 GFT |
798 | /* |
799 | * Power management control and status register | |
800 | */ | |
801 | enum jme_pmcs_bit_masks { | |
802 | PMCS_WF7DET = 0x80000000, | |
803 | PMCS_WF6DET = 0x40000000, | |
804 | PMCS_WF5DET = 0x20000000, | |
805 | PMCS_WF4DET = 0x10000000, | |
806 | PMCS_WF3DET = 0x08000000, | |
807 | PMCS_WF2DET = 0x04000000, | |
808 | PMCS_WF1DET = 0x02000000, | |
809 | PMCS_WF0DET = 0x01000000, | |
810 | PMCS_LFDET = 0x00040000, | |
811 | PMCS_LRDET = 0x00020000, | |
812 | PMCS_MFDET = 0x00010000, | |
813 | PMCS_WF7EN = 0x00008000, | |
814 | PMCS_WF6EN = 0x00004000, | |
815 | PMCS_WF5EN = 0x00002000, | |
816 | PMCS_WF4EN = 0x00001000, | |
817 | PMCS_WF3EN = 0x00000800, | |
818 | PMCS_WF2EN = 0x00000400, | |
819 | PMCS_WF1EN = 0x00000200, | |
820 | PMCS_WF0EN = 0x00000100, | |
821 | PMCS_LFEN = 0x00000004, | |
822 | PMCS_LREN = 0x00000002, | |
823 | PMCS_MFEN = 0x00000001, | |
824 | }; | |
825 | ||
d7699f87 | 826 | /* |
3bf61c55 | 827 | * Giga PHY Status Registers |
d7699f87 GFT |
828 | */ |
829 | enum jme_phy_link_bit_mask { | |
830 | PHY_LINK_SPEED_MASK = 0x0000C000, | |
831 | PHY_LINK_DUPLEX = 0x00002000, | |
832 | PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, | |
833 | PHY_LINK_UP = 0x00000400, | |
834 | PHY_LINK_AUTONEG_COMPLETE = 0x00000200, | |
fcf45b4c | 835 | PHY_LINK_MDI_STAT = 0x00000040, |
d7699f87 GFT |
836 | }; |
837 | enum jme_phy_link_speed_val { | |
838 | PHY_LINK_SPEED_10M = 0x00000000, | |
839 | PHY_LINK_SPEED_100M = 0x00004000, | |
840 | PHY_LINK_SPEED_1000M = 0x00008000, | |
841 | }; | |
fcf45b4c | 842 | #define JME_SPDRSV_TIMEOUT 500 /* 500 us */ |
d7699f87 GFT |
843 | |
844 | /* | |
845 | * SMB Control and Status | |
846 | */ | |
79ce639c | 847 | enum jme_smbcsr_bit_mask { |
d7699f87 GFT |
848 | SMBCSR_CNACK = 0x00020000, |
849 | SMBCSR_RELOAD = 0x00010000, | |
850 | SMBCSR_EEPROMD = 0x00000020, | |
186fc259 GFT |
851 | SMBCSR_INITDONE = 0x00000010, |
852 | SMBCSR_BUSY = 0x0000000F, | |
853 | }; | |
854 | enum jme_smbintf_bit_mask { | |
855 | SMBINTF_HWDATR = 0xFF000000, | |
856 | SMBINTF_HWDATW = 0x00FF0000, | |
857 | SMBINTF_HWADDR = 0x0000FF00, | |
858 | SMBINTF_HWRWN = 0x00000020, | |
859 | SMBINTF_HWCMD = 0x00000010, | |
860 | SMBINTF_FASTM = 0x00000008, | |
861 | SMBINTF_GPIOSCL = 0x00000004, | |
862 | SMBINTF_GPIOSDA = 0x00000002, | |
863 | SMBINTF_GPIOEN = 0x00000001, | |
864 | }; | |
865 | enum jme_smbintf_vals { | |
866 | SMBINTF_HWRWN_READ = 0x00000020, | |
867 | SMBINTF_HWRWN_WRITE = 0x00000000, | |
868 | }; | |
869 | enum jme_smbintf_shifts { | |
870 | SMBINTF_HWDATR_SHIFT = 24, | |
871 | SMBINTF_HWDATW_SHIFT = 16, | |
872 | SMBINTF_HWADDR_SHIFT = 8, | |
873 | }; | |
874 | #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ | |
875 | #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ | |
876 | #define JME_SMB_LEN 256 | |
877 | #define JME_EEPROM_MAGIC 0x250 | |
d7699f87 | 878 | |
79ce639c GFT |
879 | /* |
880 | * Timer Control/Status Register | |
881 | */ | |
882 | enum jme_tmcsr_bit_masks { | |
883 | TMCSR_SWIT = 0x80000000, | |
884 | TMCSR_EN = 0x01000000, | |
885 | TMCSR_CNT = 0x00FFFFFF, | |
886 | }; | |
887 | ||
d7699f87 | 888 | |
4330c2f2 GFT |
889 | /* |
890 | * General Purpost REG-0 | |
891 | */ | |
892 | enum jme_gpreg0_masks { | |
3bf61c55 GFT |
893 | GPREG0_DISSH = 0xFF000000, |
894 | GPREG0_PCIRLMT = 0x00300000, | |
895 | GPREG0_PCCNOMUTCLR = 0x00040000, | |
cdcdc9eb | 896 | GPREG0_LNKINTPOLL = 0x00001000, |
3bf61c55 GFT |
897 | GPREG0_PCCTMR = 0x00000300, |
898 | GPREG0_PHYADDR = 0x0000001F, | |
4330c2f2 GFT |
899 | }; |
900 | enum jme_gpreg0_vals { | |
901 | GPREG0_DISSH_DW7 = 0x80000000, | |
902 | GPREG0_DISSH_DW6 = 0x40000000, | |
903 | GPREG0_DISSH_DW5 = 0x20000000, | |
904 | GPREG0_DISSH_DW4 = 0x10000000, | |
905 | GPREG0_DISSH_DW3 = 0x08000000, | |
906 | GPREG0_DISSH_DW2 = 0x04000000, | |
907 | GPREG0_DISSH_DW1 = 0x02000000, | |
908 | GPREG0_DISSH_DW0 = 0x01000000, | |
909 | GPREG0_DISSH_ALL = 0xFF000000, | |
910 | ||
911 | GPREG0_PCIRLMT_8 = 0x00000000, | |
912 | GPREG0_PCIRLMT_6 = 0x00100000, | |
913 | GPREG0_PCIRLMT_5 = 0x00200000, | |
914 | GPREG0_PCIRLMT_4 = 0x00300000, | |
915 | ||
916 | GPREG0_PCCTMR_16ns = 0x00000000, | |
3bf61c55 GFT |
917 | GPREG0_PCCTMR_256ns = 0x00000100, |
918 | GPREG0_PCCTMR_1us = 0x00000200, | |
919 | GPREG0_PCCTMR_1ms = 0x00000300, | |
4330c2f2 GFT |
920 | |
921 | GPREG0_PHYADDR_1 = 0x00000001, | |
922 | ||
923 | GPREG0_DEFAULT = GPREG0_PCIRLMT_4 | | |
3bf61c55 GFT |
924 | GPREG0_PCCNOMUTCLR | |
925 | GPREG0_PCCTMR_1us | | |
926 | GPREG0_PHYADDR_1, | |
4330c2f2 GFT |
927 | }; |
928 | ||
d7699f87 GFT |
929 | /* |
930 | * Interrupt Status Bits | |
931 | */ | |
932 | enum jme_interrupt_bits | |
933 | { | |
934 | INTR_SWINTR = 0x80000000, | |
935 | INTR_TMINTR = 0x40000000, | |
936 | INTR_LINKCH = 0x20000000, | |
937 | INTR_PAUSERCV = 0x10000000, | |
938 | INTR_MAGICRCV = 0x08000000, | |
939 | INTR_WAKERCV = 0x04000000, | |
940 | INTR_PCCRX0TO = 0x02000000, | |
941 | INTR_PCCRX1TO = 0x01000000, | |
942 | INTR_PCCRX2TO = 0x00800000, | |
943 | INTR_PCCRX3TO = 0x00400000, | |
944 | INTR_PCCTXTO = 0x00200000, | |
945 | INTR_PCCRX0 = 0x00100000, | |
946 | INTR_PCCRX1 = 0x00080000, | |
947 | INTR_PCCRX2 = 0x00040000, | |
948 | INTR_PCCRX3 = 0x00020000, | |
949 | INTR_PCCTX = 0x00010000, | |
950 | INTR_RX3EMP = 0x00008000, | |
951 | INTR_RX2EMP = 0x00004000, | |
952 | INTR_RX1EMP = 0x00002000, | |
953 | INTR_RX0EMP = 0x00001000, | |
954 | INTR_RX3 = 0x00000800, | |
955 | INTR_RX2 = 0x00000400, | |
956 | INTR_RX1 = 0x00000200, | |
957 | INTR_RX0 = 0x00000100, | |
958 | INTR_TX7 = 0x00000080, | |
959 | INTR_TX6 = 0x00000040, | |
960 | INTR_TX5 = 0x00000020, | |
961 | INTR_TX4 = 0x00000010, | |
962 | INTR_TX3 = 0x00000008, | |
963 | INTR_TX2 = 0x00000004, | |
964 | INTR_TX1 = 0x00000002, | |
965 | INTR_TX0 = 0x00000001, | |
966 | }; | |
79ce639c GFT |
967 | static const __u32 INTR_ENABLE = INTR_SWINTR | |
968 | INTR_TMINTR | | |
969 | INTR_LINKCH | | |
3bf61c55 GFT |
970 | INTR_PCCRX0TO | |
971 | INTR_PCCRX0 | | |
972 | INTR_PCCTXTO | | |
cdcdc9eb GFT |
973 | INTR_PCCTX | |
974 | INTR_RX0EMP; | |
3bf61c55 GFT |
975 | |
976 | /* | |
977 | * PCC Control Registers | |
978 | */ | |
979 | enum jme_pccrx_masks { | |
980 | PCCRXTO_MASK = 0xFFFF0000, | |
981 | PCCRX_MASK = 0x0000FF00, | |
982 | }; | |
983 | enum jme_pcctx_masks { | |
984 | PCCTXTO_MASK = 0xFFFF0000, | |
985 | PCCTX_MASK = 0x0000FF00, | |
986 | PCCTX_QS_MASK = 0x000000FF, | |
987 | }; | |
988 | enum jme_pccrx_shifts { | |
989 | PCCRXTO_SHIFT = 16, | |
990 | PCCRX_SHIFT = 8, | |
991 | }; | |
992 | enum jme_pcctx_shifts { | |
993 | PCCTXTO_SHIFT = 16, | |
994 | PCCTX_SHIFT = 8, | |
995 | }; | |
996 | enum jme_pcctx_bits { | |
997 | PCCTXQ0_EN = 0x00000001, | |
998 | PCCTXQ1_EN = 0x00000002, | |
999 | PCCTXQ2_EN = 0x00000004, | |
1000 | PCCTXQ3_EN = 0x00000008, | |
1001 | PCCTXQ4_EN = 0x00000010, | |
1002 | PCCTXQ5_EN = 0x00000020, | |
1003 | PCCTXQ6_EN = 0x00000040, | |
1004 | PCCTXQ7_EN = 0x00000080, | |
1005 | }; | |
1006 | ||
cdcdc9eb GFT |
1007 | /* |
1008 | * Chip Mode Register | |
1009 | */ | |
1010 | enum jme_chipmode_bit_masks { | |
1011 | CM_FPGAVER_MASK = 0xFFFF0000, | |
1012 | CM_CHIPVER_MASK = 0x0000FF00, | |
1013 | CM_CHIPMODE_MASK = 0x0000000F, | |
1014 | }; | |
1015 | enum jme_chipmode_shifts { | |
1016 | CM_FPGAVER_SHIFT = 16, | |
1017 | CM_CHIPVER_SHIFT = 8, | |
1018 | }; | |
d7699f87 | 1019 | |
4330c2f2 GFT |
1020 | /* |
1021 | * Shadow base address register bits | |
1022 | */ | |
1023 | enum jme_shadow_base_address_bits { | |
1024 | SHBA_POSTEN = 0x1, | |
1025 | }; | |
1026 | ||
d7699f87 GFT |
1027 | /* |
1028 | * Read/Write MMaped I/O Registers | |
1029 | */ | |
1030 | __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg) | |
1031 | { | |
79ce639c | 1032 | return le32_to_cpu(readl((__u8*)jme->regs + reg)); |
d7699f87 GFT |
1033 | } |
1034 | __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val) | |
1035 | { | |
79ce639c | 1036 | writel(cpu_to_le32(val), (__u8*)jme->regs + reg); |
d7699f87 GFT |
1037 | } |
1038 | __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) | |
1039 | { | |
1040 | /* | |
1041 | * Read after write should cause flush | |
1042 | */ | |
79ce639c GFT |
1043 | writel(cpu_to_le32(val), (__u8*)jme->regs + reg); |
1044 | readl((__u8*)jme->regs + reg); | |
d7699f87 GFT |
1045 | } |
1046 | ||
cdcdc9eb GFT |
1047 | /* |
1048 | * PHY Regs | |
1049 | */ | |
1050 | enum jme_phy_reg17_bit_masks { | |
1051 | PREG17_SPEED = 0xC000, | |
1052 | PREG17_DUPLEX = 0x2000, | |
1053 | PREG17_SPDRSV = 0x0800, | |
1054 | PREG17_LNKUP = 0x0400, | |
1055 | PREG17_MDI = 0x0040, | |
1056 | }; | |
1057 | enum jme_phy_reg17_vals { | |
1058 | PREG17_SPEED_10M = 0x0000, | |
1059 | PREG17_SPEED_100M = 0x4000, | |
1060 | PREG17_SPEED_1000M = 0x8000, | |
1061 | }; | |
8d27293f | 1062 | #define BMSR_ANCOMP 0x0020 |
cdcdc9eb | 1063 | |
d7699f87 GFT |
1064 | /* |
1065 | * Function prototypes for ethtool | |
1066 | */ | |
1067 | static void jme_get_drvinfo(struct net_device *netdev, | |
1068 | struct ethtool_drvinfo *info); | |
1069 | static int jme_get_settings(struct net_device *netdev, | |
1070 | struct ethtool_cmd *ecmd); | |
1071 | static int jme_set_settings(struct net_device *netdev, | |
1072 | struct ethtool_cmd *ecmd); | |
1073 | static u32 jme_get_link(struct net_device *netdev); | |
1074 | ||
1075 | ||
1076 | /* | |
1077 | * Function prototypes for netdev | |
1078 | */ | |
1079 | static int jme_open(struct net_device *netdev); | |
1080 | static int jme_close(struct net_device *netdev); | |
1081 | static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev); | |
1082 | static int jme_set_macaddr(struct net_device *netdev, void *p); | |
1083 | static void jme_set_multi(struct net_device *netdev); | |
1084 |