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4330c2f2 GFT |
1 | /* |
2 | * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver | |
3 | * | |
4 | * Copyright 2008 JMicron Technology Corporation | |
5 | * http://www.jmicron.com/ | |
6 | * | |
3bf61c55 GFT |
7 | * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> |
8 | * | |
4330c2f2 GFT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/version.h> | |
d7699f87 GFT |
25 | |
26 | #define DRV_NAME "jme" | |
186fc259 | 27 | #define DRV_VERSION "0.9c" |
d7699f87 GFT |
28 | #define PFX DRV_NAME ": " |
29 | ||
30 | #ifdef DEBUG | |
4330c2f2 | 31 | #define dprintk(devname, fmt, args...) \ |
8c198884 | 32 | printk(KERN_DEBUG "%s: " fmt, devname, ## args) |
d7699f87 | 33 | #else |
4330c2f2 | 34 | #define dprintk(devname, fmt, args...) |
d7699f87 GFT |
35 | #endif |
36 | ||
3bf61c55 GFT |
37 | #ifdef TX_DEBUG |
38 | #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
39 | #else | |
40 | #define tx_dbg(args...) | |
41 | #endif | |
42 | ||
43 | #ifdef RX_DEBUG | |
44 | #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
45 | #else | |
46 | #define rx_dbg(args...) | |
47 | #endif | |
48 | ||
29bdd921 GFT |
49 | #ifdef QUEUE_DEBUG |
50 | #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
51 | #else | |
52 | #define queue_dbg(args...) | |
53 | #endif | |
54 | ||
79ce639c GFT |
55 | #ifdef CSUM_DEBUG |
56 | #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
57 | #else | |
58 | #define csum_dbg(args...) | |
59 | #endif | |
60 | ||
b3821cc5 GFT |
61 | #ifdef VLAN_DEBUG |
62 | #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) | |
63 | #else | |
64 | #define vlan_dbg(args...) | |
65 | #endif | |
66 | ||
4330c2f2 | 67 | #define jprintk(devname, fmt, args...) \ |
8c198884 | 68 | printk(KERN_INFO "%s: " fmt, devname, ## args) |
4330c2f2 GFT |
69 | |
70 | #define jeprintk(devname, fmt, args...) \ | |
8c198884 | 71 | printk(KERN_ERR "%s: " fmt, devname, ## args) |
4330c2f2 | 72 | |
d7699f87 GFT |
73 | #define DEFAULT_MSG_ENABLE \ |
74 | (NETIF_MSG_DRV | \ | |
75 | NETIF_MSG_PROBE | \ | |
76 | NETIF_MSG_LINK | \ | |
77 | NETIF_MSG_TIMER | \ | |
78 | NETIF_MSG_RX_ERR | \ | |
79 | NETIF_MSG_TX_ERR) | |
80 | ||
4330c2f2 GFT |
81 | #define PCI_CONF_DCSR_MRRS 0x59 |
82 | #define PCI_CONF_DCSR_MRRS_MASK 0x70 | |
83 | enum pci_conf_dcsr_mrrs_vals { | |
84 | MRRS_128B = 0x00, | |
85 | MRRS_256B = 0x10, | |
86 | MRRS_512B = 0x20, | |
87 | MRRS_1024B = 0x30, | |
88 | MRRS_2048B = 0x40, | |
89 | MRRS_4096B = 0x50, | |
90 | }; | |
d7699f87 | 91 | |
79ce639c GFT |
92 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 |
93 | #define MIN_ETHERNET_PACKET_SIZE 60 | |
94 | ||
3bf61c55 | 95 | enum dynamic_pcc_values { |
192570e0 | 96 | PCC_OFF = 0, |
3bf61c55 GFT |
97 | PCC_P1 = 1, |
98 | PCC_P2 = 2, | |
99 | PCC_P3 = 3, | |
100 | ||
192570e0 | 101 | PCC_OFF_TO = 0, |
3bf61c55 | 102 | PCC_P1_TO = 1, |
192570e0 GFT |
103 | PCC_P2_TO = 64, |
104 | PCC_P3_TO = 128, | |
3bf61c55 | 105 | |
192570e0 | 106 | PCC_OFF_CNT = 0, |
3bf61c55 | 107 | PCC_P1_CNT = 1, |
192570e0 GFT |
108 | PCC_P2_CNT = 16, |
109 | PCC_P3_CNT = 32, | |
3bf61c55 GFT |
110 | }; |
111 | struct dynpcc_info { | |
3bf61c55 GFT |
112 | unsigned long last_bytes; |
113 | unsigned long last_pkts; | |
79ce639c | 114 | unsigned long intr_cnt; |
3bf61c55 GFT |
115 | unsigned char cur; |
116 | unsigned char attempt; | |
117 | unsigned char cnt; | |
118 | }; | |
79ce639c GFT |
119 | #define PCC_INTERVAL_US 100000 |
120 | #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) | |
cdcdc9eb | 121 | #define PCC_P3_THRESHOLD 2*1024*1024 |
79ce639c GFT |
122 | #define PCC_P2_THRESHOLD 800 |
123 | #define PCC_INTR_THRESHOLD 800 | |
b3821cc5 GFT |
124 | #define PCC_TX_TO 333 |
125 | #define PCC_TX_CNT 8 | |
3bf61c55 | 126 | |
d7699f87 GFT |
127 | /* |
128 | * TX/RX Descriptors | |
4330c2f2 GFT |
129 | * |
130 | * TX/RX Ring DESC Count Must be multiple of 16 | |
131 | * RX Ring DESC Count Must be <= 1024 | |
d7699f87 | 132 | */ |
4330c2f2 GFT |
133 | #define RING_DESC_ALIGN 16 /* Descriptor alignment */ |
134 | ||
d7699f87 GFT |
135 | #define TX_DESC_SIZE 16 |
136 | #define TX_RING_NR 8 | |
b3821cc5 | 137 | #define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN |
d7699f87 | 138 | |
3bf61c55 | 139 | struct txdesc { |
d7699f87 GFT |
140 | union { |
141 | __u8 all[16]; | |
142 | __u32 dw[4]; | |
143 | struct { | |
144 | /* DW0 */ | |
145 | __u16 vlan; | |
146 | __u8 rsv1; | |
147 | __u8 flags; | |
148 | ||
149 | /* DW1 */ | |
150 | __u16 datalen; | |
151 | __u16 mss; | |
152 | ||
153 | /* DW2 */ | |
154 | __u16 pktsize; | |
155 | __u16 rsv2; | |
156 | ||
157 | /* DW3 */ | |
158 | __u32 bufaddr; | |
159 | } desc1; | |
3bf61c55 GFT |
160 | struct { |
161 | /* DW0 */ | |
162 | __u16 rsv1; | |
163 | __u8 rsv2; | |
164 | __u8 flags; | |
165 | ||
166 | /* DW1 */ | |
167 | __u16 datalen; | |
168 | __u16 rsv3; | |
169 | ||
170 | /* DW2 */ | |
171 | __u32 bufaddrh; | |
172 | ||
173 | /* DW3 */ | |
174 | __u32 bufaddrl; | |
175 | } desc2; | |
8c198884 GFT |
176 | struct { |
177 | /* DW0 */ | |
178 | __u8 ehdrsz; | |
179 | __u8 rsv1; | |
180 | __u8 rsv2; | |
181 | __u8 flags; | |
182 | ||
183 | /* DW1 */ | |
184 | __u16 trycnt; | |
185 | __u16 segcnt; | |
186 | ||
187 | /* DW2 */ | |
188 | __u16 pktsz; | |
189 | __u16 rsv3; | |
190 | ||
191 | /* DW3 */ | |
192 | __u32 bufaddrl; | |
193 | } descwb; | |
d7699f87 GFT |
194 | }; |
195 | }; | |
8c198884 | 196 | enum jme_txdesc_flags_bits { |
d7699f87 GFT |
197 | TXFLAG_OWN = 0x80, |
198 | TXFLAG_INT = 0x40, | |
3bf61c55 | 199 | TXFLAG_64BIT = 0x20, |
d7699f87 GFT |
200 | TXFLAG_TCPCS = 0x10, |
201 | TXFLAG_UDPCS = 0x08, | |
202 | TXFLAG_IPCS = 0x04, | |
203 | TXFLAG_LSEN = 0x02, | |
204 | TXFLAG_TAGON = 0x01, | |
205 | }; | |
b3821cc5 | 206 | #define TXDESC_MSS_SHIFT 2 |
8c198884 GFT |
207 | enum jme_rxdescwb_flags_bits { |
208 | TXWBFLAG_OWN = 0x80, | |
209 | TXWBFLAG_INT = 0x40, | |
210 | TXWBFLAG_TMOUT = 0x20, | |
211 | TXWBFLAG_TRYOUT = 0x10, | |
212 | TXWBFLAG_COL = 0x08, | |
213 | ||
214 | TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | | |
215 | TXWBFLAG_TRYOUT | | |
216 | TXWBFLAG_COL, | |
217 | }; | |
d7699f87 GFT |
218 | |
219 | ||
220 | #define RX_DESC_SIZE 16 | |
221 | #define RX_RING_NR 4 | |
b3821cc5 | 222 | #define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN |
d7699f87 GFT |
223 | |
224 | #define RX_BUF_DMA_ALIGN 8 | |
3bf61c55 | 225 | #define RX_PREPAD_SIZE 10 |
79ce639c GFT |
226 | #define ETH_CRC_LEN 2 |
227 | #define RX_VLANHDR_LEN 2 | |
228 | #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ | |
229 | ETH_HLEN + \ | |
230 | ETH_CRC_LEN + \ | |
231 | RX_VLANHDR_LEN + \ | |
232 | RX_BUF_DMA_ALIGN) | |
d7699f87 | 233 | |
3bf61c55 | 234 | struct rxdesc { |
d7699f87 GFT |
235 | union { |
236 | __u8 all[16]; | |
237 | __le32 dw[4]; | |
238 | struct { | |
239 | /* DW0 */ | |
240 | __le16 rsv2; | |
241 | __u8 rsv1; | |
242 | __u8 flags; | |
243 | ||
244 | /* DW1 */ | |
245 | __le16 datalen; | |
246 | __le16 wbcpl; | |
247 | ||
248 | /* DW2 */ | |
249 | __le32 bufaddrh; | |
250 | ||
251 | /* DW3 */ | |
252 | __le32 bufaddrl; | |
253 | } desc1; | |
254 | struct { | |
255 | /* DW0 */ | |
256 | __le16 vlan; | |
257 | __le16 flags; | |
258 | ||
259 | /* DW1 */ | |
260 | __le16 framesize; | |
4330c2f2 | 261 | __u8 errstat; |
d7699f87 GFT |
262 | __u8 desccnt; |
263 | ||
264 | /* DW2 */ | |
265 | __le32 rsshash; | |
266 | ||
267 | /* DW3 */ | |
3bf61c55 GFT |
268 | __u8 hashfun; |
269 | __u8 hashtype; | |
d7699f87 GFT |
270 | __le16 resrv; |
271 | } descwb; | |
272 | }; | |
273 | }; | |
274 | enum jme_rxdesc_flags_bits { | |
275 | RXFLAG_OWN = 0x80, | |
276 | RXFLAG_INT = 0x40, | |
277 | RXFLAG_64BIT = 0x20, | |
278 | }; | |
279 | enum jme_rxwbdesc_flags_bits { | |
4330c2f2 GFT |
280 | RXWBFLAG_OWN = 0x8000, |
281 | RXWBFLAG_INT = 0x4000, | |
282 | RXWBFLAG_MF = 0x2000, | |
283 | RXWBFLAG_64BIT = 0x2000, | |
284 | RXWBFLAG_TCPON = 0x1000, | |
285 | RXWBFLAG_UDPON = 0x0800, | |
286 | RXWBFLAG_IPCS = 0x0400, | |
287 | RXWBFLAG_TCPCS = 0x0200, | |
288 | RXWBFLAG_UDPCS = 0x0100, | |
289 | RXWBFLAG_TAGON = 0x0080, | |
290 | RXWBFLAG_IPV4 = 0x0040, | |
291 | RXWBFLAG_IPV6 = 0x0020, | |
292 | RXWBFLAG_PAUSE = 0x0010, | |
293 | RXWBFLAG_MAGIC = 0x0008, | |
294 | RXWBFLAG_WAKEUP = 0x0004, | |
295 | RXWBFLAG_DEST = 0x0003, | |
296 | RXWBFLAG_DEST_UNI = 0x0001, | |
297 | RXWBFLAG_DEST_MUL = 0x0002, | |
298 | RXWBFLAG_DEST_BRO = 0x0003, | |
d7699f87 GFT |
299 | }; |
300 | enum jme_rxwbdesc_desccnt_mask { | |
301 | RXWBDCNT_WBCPL = 0x80, | |
302 | RXWBDCNT_DCNT = 0x7F, | |
303 | }; | |
4330c2f2 GFT |
304 | enum jme_rxwbdesc_errstat_bits { |
305 | RXWBERR_LIMIT = 0x80, | |
306 | RXWBERR_MIIER = 0x40, | |
307 | RXWBERR_NIBON = 0x20, | |
308 | RXWBERR_COLON = 0x10, | |
309 | RXWBERR_ABORT = 0x08, | |
310 | RXWBERR_SHORT = 0x04, | |
311 | RXWBERR_OVERUN = 0x02, | |
312 | RXWBERR_CRCERR = 0x01, | |
313 | RXWBERR_ALLERR = 0xFF, | |
314 | }; | |
315 | ||
316 | struct jme_buffer_info { | |
317 | struct sk_buff *skb; | |
318 | dma_addr_t mapping; | |
319 | int len; | |
3bf61c55 | 320 | int nr_desc; |
cdcdc9eb | 321 | unsigned long start_xmit; |
4330c2f2 | 322 | }; |
d7699f87 | 323 | |
b3821cc5 | 324 | #define MAX_RING_DESC_NR 1024 |
d7699f87 | 325 | struct jme_ring { |
4330c2f2 | 326 | void* alloc; /* pointer to allocated memory */ |
3bf61c55 | 327 | volatile void* desc; /* pointer to ring memory */ |
d7699f87 GFT |
328 | dma_addr_t dmaalloc; /* phys address of ring alloc */ |
329 | dma_addr_t dma; /* phys address for ring dma */ | |
330 | ||
4330c2f2 | 331 | /* Buffer information corresponding to each descriptor */ |
b3821cc5 | 332 | struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; |
d7699f87 | 333 | |
b3821cc5 | 334 | int next_to_use; |
cdcdc9eb | 335 | atomic_t next_to_clean; |
79ce639c | 336 | atomic_t nr_free; |
d7699f87 GFT |
337 | }; |
338 | ||
3bf61c55 GFT |
339 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) |
340 | #define NET_STAT(priv) priv->stats | |
341 | #define NETDEV_GET_STATS(netdev, fun_ptr) \ | |
342 | netdev->get_stats = fun_ptr | |
343 | #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; | |
344 | #else | |
345 | #define NET_STAT(priv) priv->dev->stats | |
346 | #define NETDEV_GET_STATS(netdev, fun_ptr) | |
347 | #define DECLARE_NET_DEVICE_STATS | |
348 | #endif | |
349 | ||
cdcdc9eb GFT |
350 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
351 | #define DECLARE_NAPI_STRUCT | |
352 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
353 | dev->poll = pollfn; \ | |
354 | dev->weight = q; | |
355 | #define JME_NAPI_HOLDER(holder) struct net_device *holder | |
356 | #define JME_NAPI_WEIGHT(w) int *w | |
357 | #define JME_NAPI_WEIGHT_VAL(w) *w | |
358 | #define JME_NAPI_WEIGHT_SET(w, r) *w = r | |
359 | #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) | |
360 | #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); | |
361 | #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); | |
362 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
363 | netif_rx_schedule_prep(priv->dev) | |
364 | #define JME_RX_SCHEDULE(priv) \ | |
365 | __netif_rx_schedule(priv->dev); | |
366 | #else | |
367 | #define DECLARE_NAPI_STRUCT struct napi_struct napi; | |
368 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
369 | netif_napi_add(dev, napis, pollfn, q); | |
370 | #define JME_NAPI_HOLDER(holder) struct napi_struct *holder | |
371 | #define JME_NAPI_WEIGHT(w) int w | |
372 | #define JME_NAPI_WEIGHT_VAL(w) w | |
373 | #define JME_NAPI_WEIGHT_SET(w, r) | |
374 | #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis) | |
375 | #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); | |
376 | #define JME_NAPI_DISABLE(priv) \ | |
377 | if(!napi_disable_pending(&priv->napi)) \ | |
378 | napi_disable(&priv->napi); | |
379 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
380 | netif_rx_schedule_prep(priv->dev, &priv->napi) | |
381 | #define JME_RX_SCHEDULE(priv) \ | |
382 | __netif_rx_schedule(priv->dev, &priv->napi); | |
383 | #endif | |
384 | ||
d7699f87 GFT |
385 | /* |
386 | * Jmac Adapter Private data | |
387 | */ | |
4330c2f2 | 388 | #define SHADOW_REG_NR 8 |
d7699f87 GFT |
389 | struct jme_adapter { |
390 | struct pci_dev *pdev; | |
391 | struct net_device *dev; | |
392 | void __iomem *regs; | |
4330c2f2 GFT |
393 | dma_addr_t shadow_dma; |
394 | __u32 *shadow_regs; | |
d7699f87 GFT |
395 | struct mii_if_info mii_if; |
396 | struct jme_ring rxring[RX_RING_NR]; | |
397 | struct jme_ring txring[TX_RING_NR]; | |
d7699f87 | 398 | spinlock_t phy_lock; |
fcf45b4c | 399 | spinlock_t macaddr_lock; |
8c198884 | 400 | spinlock_t rxmcs_lock; |
fcf45b4c | 401 | struct tasklet_struct rxempty_task; |
4330c2f2 GFT |
402 | struct tasklet_struct rxclean_task; |
403 | struct tasklet_struct txclean_task; | |
404 | struct tasklet_struct linkch_task; | |
79ce639c GFT |
405 | struct tasklet_struct pcc_task; |
406 | __u32 flags; | |
4330c2f2 | 407 | __u32 reg_txcs; |
8c198884 | 408 | __u32 reg_txpfc; |
79ce639c | 409 | __u32 reg_rxcs; |
3bf61c55 GFT |
410 | __u32 reg_rxmcs; |
411 | __u32 reg_ghc; | |
29bdd921 | 412 | __u32 reg_pmcs; |
fcf45b4c | 413 | __u32 phylink; |
b3821cc5 GFT |
414 | __u32 tx_ring_size; |
415 | __u32 tx_ring_mask; | |
416 | __u32 tx_wake_threshold; | |
417 | __u32 rx_ring_size; | |
418 | __u32 rx_ring_mask; | |
fcf45b4c | 419 | __u8 mrrs; |
cdcdc9eb GFT |
420 | __u32 fpgaver; |
421 | __u32 chipver; | |
29bdd921 GFT |
422 | struct ethtool_cmd old_ecmd; |
423 | unsigned int old_mtu; | |
42b1055e | 424 | struct vlan_group* vlgrp; |
3bf61c55 GFT |
425 | struct dynpcc_info dpi; |
426 | atomic_t intr_sem; | |
fcf45b4c GFT |
427 | atomic_t link_changing; |
428 | atomic_t tx_cleaning; | |
429 | atomic_t rx_cleaning; | |
192570e0 | 430 | atomic_t rx_empty; |
cdcdc9eb GFT |
431 | int (*jme_rx)(struct sk_buff *skb); |
432 | int (*jme_vlan_rx)(struct sk_buff *skb, | |
433 | struct vlan_group *grp, | |
434 | unsigned short vlan_tag); | |
435 | DECLARE_NAPI_STRUCT | |
3bf61c55 | 436 | DECLARE_NET_DEVICE_STATS |
d7699f87 | 437 | }; |
4330c2f2 GFT |
438 | enum shadow_reg_val { |
439 | SHADOW_IEVE = 0, | |
440 | }; | |
79ce639c GFT |
441 | enum jme_flags_bits { |
442 | JME_FLAG_MSI = 0x00000001, | |
29bdd921 | 443 | JME_FLAG_SSET = 0x00000002, |
b3821cc5 GFT |
444 | JME_FLAG_TXCSUM = 0x00000004, |
445 | JME_FLAG_TSO = 0x00000008, | |
192570e0 | 446 | JME_FLAG_POLL = 0x00000010, |
8c198884 | 447 | }; |
fcf45b4c | 448 | #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ |
8c198884 | 449 | #define TX_TIMEOUT (5*HZ) |
186fc259 | 450 | #define JME_REG_LEN 0x500 |
8c198884 | 451 | |
cdcdc9eb GFT |
452 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
453 | __always_inline static struct jme_adapter* | |
454 | jme_napi_priv(struct net_device *holder) | |
455 | { | |
456 | struct jme_adapter* jme; | |
457 | jme = netdev_priv(holder); | |
458 | return jme; | |
459 | } | |
460 | #else | |
461 | __always_inline static struct jme_adapter* | |
462 | jme_napi_priv(struct napi_struct *napi) | |
463 | { | |
464 | struct jme_adapter* jme; | |
465 | jme = container_of(napi, struct jme_adapter, napi); | |
466 | return jme; | |
467 | } | |
468 | #endif | |
d7699f87 GFT |
469 | |
470 | /* | |
471 | * MMaped I/O Resters | |
472 | */ | |
473 | enum jme_iomap_offsets { | |
4330c2f2 GFT |
474 | JME_MAC = 0x0000, |
475 | JME_PHY = 0x0400, | |
d7699f87 | 476 | JME_MISC = 0x0800, |
4330c2f2 | 477 | JME_RSS = 0x0C00, |
d7699f87 GFT |
478 | }; |
479 | ||
8c198884 GFT |
480 | enum jme_iomap_lens { |
481 | JME_MAC_LEN = 0x80, | |
482 | JME_PHY_LEN = 0x58, | |
483 | JME_MISC_LEN = 0x98, | |
484 | JME_RSS_LEN = 0xFF, | |
485 | }; | |
486 | ||
d7699f87 GFT |
487 | enum jme_iomap_regs { |
488 | JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ | |
3bf61c55 GFT |
489 | JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ |
490 | JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */ | |
d7699f87 GFT |
491 | JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */ |
492 | JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */ | |
493 | JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */ | |
494 | JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */ | |
495 | JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */ | |
496 | ||
497 | JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */ | |
3bf61c55 GFT |
498 | JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */ |
499 | JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */ | |
d7699f87 GFT |
500 | JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */ |
501 | JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */ | |
502 | JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */ | |
4330c2f2 GFT |
503 | JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */ |
504 | JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */ | |
3bf61c55 GFT |
505 | JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */ |
506 | JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */ | |
d7699f87 GFT |
507 | JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */ |
508 | JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */ | |
509 | ||
510 | JME_SMI = JME_MAC | 0x50, /* Station Management Interface */ | |
511 | JME_GHC = JME_MAC | 0x54, /* Global Host Control */ | |
512 | JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */ | |
513 | ||
514 | ||
3bf61c55 | 515 | JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ |
d7699f87 GFT |
516 | JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ |
517 | JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ | |
186fc259 | 518 | JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ |
d7699f87 GFT |
519 | |
520 | ||
79ce639c | 521 | JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ |
4330c2f2 GFT |
522 | JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */ |
523 | JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */ | |
d7699f87 | 524 | JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */ |
3bf61c55 | 525 | JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */ |
d7699f87 | 526 | JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */ |
3bf61c55 GFT |
527 | JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */ |
528 | JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */ | |
529 | JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */ | |
cdcdc9eb | 530 | JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */ |
4330c2f2 GFT |
531 | JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */ |
532 | JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */ | |
3bf61c55 | 533 | JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */ |
d7699f87 GFT |
534 | }; |
535 | ||
536 | /* | |
537 | * TX Control/Status Bits | |
538 | */ | |
539 | enum jme_txcs_bits { | |
540 | TXCS_QUEUE7S = 0x00008000, | |
541 | TXCS_QUEUE6S = 0x00004000, | |
542 | TXCS_QUEUE5S = 0x00002000, | |
543 | TXCS_QUEUE4S = 0x00001000, | |
544 | TXCS_QUEUE3S = 0x00000800, | |
545 | TXCS_QUEUE2S = 0x00000400, | |
546 | TXCS_QUEUE1S = 0x00000200, | |
547 | TXCS_QUEUE0S = 0x00000100, | |
548 | TXCS_FIFOTH = 0x000000C0, | |
549 | TXCS_DMASIZE = 0x00000030, | |
550 | TXCS_BURST = 0x00000004, | |
551 | TXCS_ENABLE = 0x00000001, | |
552 | }; | |
553 | enum jme_txcs_value { | |
554 | TXCS_FIFOTH_16QW = 0x000000C0, | |
555 | TXCS_FIFOTH_12QW = 0x00000080, | |
556 | TXCS_FIFOTH_8QW = 0x00000040, | |
557 | TXCS_FIFOTH_4QW = 0x00000000, | |
558 | ||
559 | TXCS_DMASIZE_64B = 0x00000000, | |
560 | TXCS_DMASIZE_128B = 0x00000010, | |
561 | TXCS_DMASIZE_256B = 0x00000020, | |
562 | TXCS_DMASIZE_512B = 0x00000030, | |
563 | ||
564 | TXCS_SELECT_QUEUE0 = 0x00000000, | |
565 | TXCS_SELECT_QUEUE1 = 0x00010000, | |
566 | TXCS_SELECT_QUEUE2 = 0x00020000, | |
567 | TXCS_SELECT_QUEUE3 = 0x00030000, | |
568 | TXCS_SELECT_QUEUE4 = 0x00040000, | |
569 | TXCS_SELECT_QUEUE5 = 0x00050000, | |
570 | TXCS_SELECT_QUEUE6 = 0x00060000, | |
571 | TXCS_SELECT_QUEUE7 = 0x00070000, | |
572 | ||
573 | TXCS_DEFAULT = TXCS_FIFOTH_4QW | | |
d7699f87 GFT |
574 | TXCS_BURST, |
575 | }; | |
29bdd921 | 576 | #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
577 | |
578 | /* | |
579 | * TX MAC Control/Status Bits | |
580 | */ | |
581 | enum jme_txmcs_bit_masks { | |
582 | TXMCS_IFG2 = 0xC0000000, | |
583 | TXMCS_IFG1 = 0x30000000, | |
584 | TXMCS_TTHOLD = 0x00000300, | |
585 | TXMCS_FBURST = 0x00000080, | |
586 | TXMCS_CARRIEREXT = 0x00000040, | |
587 | TXMCS_DEFER = 0x00000020, | |
588 | TXMCS_BACKOFF = 0x00000010, | |
589 | TXMCS_CARRIERSENSE = 0x00000008, | |
590 | TXMCS_COLLISION = 0x00000004, | |
591 | TXMCS_CRC = 0x00000002, | |
592 | TXMCS_PADDING = 0x00000001, | |
593 | }; | |
594 | enum jme_txmcs_values { | |
595 | TXMCS_IFG2_6_4 = 0x00000000, | |
596 | TXMCS_IFG2_8_5 = 0x40000000, | |
597 | TXMCS_IFG2_10_6 = 0x80000000, | |
598 | TXMCS_IFG2_12_7 = 0xC0000000, | |
599 | ||
600 | TXMCS_IFG1_8_4 = 0x00000000, | |
601 | TXMCS_IFG1_12_6 = 0x10000000, | |
602 | TXMCS_IFG1_16_8 = 0x20000000, | |
603 | TXMCS_IFG1_20_10 = 0x30000000, | |
604 | ||
605 | TXMCS_TTHOLD_1_8 = 0x00000000, | |
606 | TXMCS_TTHOLD_1_4 = 0x00000100, | |
607 | TXMCS_TTHOLD_1_2 = 0x00000200, | |
608 | TXMCS_TTHOLD_FULL = 0x00000300, | |
609 | ||
610 | TXMCS_DEFAULT = TXMCS_IFG2_8_5 | | |
611 | TXMCS_IFG1_16_8 | | |
612 | TXMCS_TTHOLD_FULL | | |
613 | TXMCS_DEFER | | |
614 | TXMCS_CRC | | |
615 | TXMCS_PADDING, | |
616 | }; | |
617 | ||
8c198884 GFT |
618 | enum jme_txpfc_bits_masks { |
619 | TXPFC_VLAN_TAG = 0xFFFF0000, | |
620 | TXPFC_VLAN_EN = 0x00008000, | |
621 | TXPFC_PF_EN = 0x00000001, | |
622 | }; | |
623 | ||
624 | enum jme_txtrhd_bits_masks { | |
625 | TXTRHD_TXPEN = 0x80000000, | |
626 | TXTRHD_TXP = 0x7FFFFF00, | |
627 | TXTRHD_TXREN = 0x00000080, | |
628 | TXTRHD_TXRL = 0x0000007F, | |
629 | }; | |
630 | enum jme_txtrhd_shifts { | |
631 | TXTRHD_TXP_SHIFT = 8, | |
632 | TXTRHD_TXRL_SHIFT = 0, | |
633 | }; | |
634 | ||
d7699f87 GFT |
635 | |
636 | /* | |
637 | * RX Control/Status Bits | |
638 | */ | |
4330c2f2 | 639 | enum jme_rxcs_bit_masks { |
3bf61c55 GFT |
640 | /* FIFO full threshold for transmitting Tx Pause Packet */ |
641 | RXCS_FIFOTHTP = 0x30000000, | |
642 | /* FIFO threshold for processing next packet */ | |
643 | RXCS_FIFOTHNP = 0x0C000000, | |
4330c2f2 GFT |
644 | RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */ |
645 | RXCS_QUEUESEL = 0x00030000, /* Queue selection */ | |
646 | RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */ | |
647 | RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */ | |
648 | RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */ | |
649 | RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */ | |
650 | RXCS_SHORT = 0x00000010, /* Enable receive short packet */ | |
651 | RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */ | |
652 | RXCS_QST = 0x00000004, /* Receive queue start */ | |
653 | RXCS_SUSPEND = 0x00000002, | |
d7699f87 GFT |
654 | RXCS_ENABLE = 0x00000001, |
655 | }; | |
4330c2f2 GFT |
656 | enum jme_rxcs_values { |
657 | RXCS_FIFOTHTP_16T = 0x00000000, | |
658 | RXCS_FIFOTHTP_32T = 0x10000000, | |
659 | RXCS_FIFOTHTP_64T = 0x20000000, | |
660 | RXCS_FIFOTHTP_128T = 0x30000000, | |
661 | ||
662 | RXCS_FIFOTHNP_16QW = 0x00000000, | |
663 | RXCS_FIFOTHNP_32QW = 0x04000000, | |
664 | RXCS_FIFOTHNP_64QW = 0x08000000, | |
665 | RXCS_FIFOTHNP_128QW = 0x0C000000, | |
666 | ||
667 | RXCS_DMAREQSZ_16B = 0x00000000, | |
668 | RXCS_DMAREQSZ_32B = 0x01000000, | |
669 | RXCS_DMAREQSZ_64B = 0x02000000, | |
670 | RXCS_DMAREQSZ_128B = 0x03000000, | |
671 | ||
672 | RXCS_QUEUESEL_Q0 = 0x00000000, | |
673 | RXCS_QUEUESEL_Q1 = 0x00010000, | |
674 | RXCS_QUEUESEL_Q2 = 0x00020000, | |
675 | RXCS_QUEUESEL_Q3 = 0x00030000, | |
676 | ||
677 | RXCS_RETRYGAP_256ns = 0x00000000, | |
678 | RXCS_RETRYGAP_512ns = 0x00001000, | |
679 | RXCS_RETRYGAP_1024ns = 0x00002000, | |
680 | RXCS_RETRYGAP_2048ns = 0x00003000, | |
681 | RXCS_RETRYGAP_4096ns = 0x00004000, | |
682 | RXCS_RETRYGAP_8192ns = 0x00005000, | |
683 | RXCS_RETRYGAP_16384ns = 0x00006000, | |
684 | RXCS_RETRYGAP_32768ns = 0x00007000, | |
685 | ||
686 | RXCS_RETRYCNT_0 = 0x00000000, | |
687 | RXCS_RETRYCNT_4 = 0x00000100, | |
688 | RXCS_RETRYCNT_8 = 0x00000200, | |
689 | RXCS_RETRYCNT_12 = 0x00000300, | |
690 | RXCS_RETRYCNT_16 = 0x00000400, | |
691 | RXCS_RETRYCNT_20 = 0x00000500, | |
692 | RXCS_RETRYCNT_24 = 0x00000600, | |
693 | RXCS_RETRYCNT_28 = 0x00000700, | |
694 | RXCS_RETRYCNT_32 = 0x00000800, | |
695 | RXCS_RETRYCNT_36 = 0x00000900, | |
696 | RXCS_RETRYCNT_40 = 0x00000A00, | |
697 | RXCS_RETRYCNT_44 = 0x00000B00, | |
698 | RXCS_RETRYCNT_48 = 0x00000C00, | |
699 | RXCS_RETRYCNT_52 = 0x00000D00, | |
700 | RXCS_RETRYCNT_56 = 0x00000E00, | |
701 | RXCS_RETRYCNT_60 = 0x00000F00, | |
702 | ||
703 | RXCS_DEFAULT = RXCS_FIFOTHTP_128T | | |
79ce639c | 704 | RXCS_FIFOTHNP_128QW | |
4330c2f2 GFT |
705 | RXCS_DMAREQSZ_128B | |
706 | RXCS_RETRYGAP_256ns | | |
707 | RXCS_RETRYCNT_32, | |
708 | }; | |
29bdd921 | 709 | #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
710 | |
711 | /* | |
712 | * RX MAC Control/Status Bits | |
713 | */ | |
714 | enum jme_rxmcs_bits { | |
715 | RXMCS_ALLFRAME = 0x00000800, | |
716 | RXMCS_BRDFRAME = 0x00000400, | |
717 | RXMCS_MULFRAME = 0x00000200, | |
718 | RXMCS_UNIFRAME = 0x00000100, | |
719 | RXMCS_ALLMULFRAME = 0x00000080, | |
720 | RXMCS_MULFILTERED = 0x00000040, | |
3bf61c55 GFT |
721 | RXMCS_RXCOLLDEC = 0x00000020, |
722 | RXMCS_FLOWCTRL = 0x00000008, | |
723 | RXMCS_VTAGRM = 0x00000004, | |
724 | RXMCS_PREPAD = 0x00000002, | |
725 | RXMCS_CHECKSUM = 0x00000001, | |
b3821cc5 | 726 | |
8c198884 GFT |
727 | RXMCS_DEFAULT = RXMCS_VTAGRM | |
728 | RXMCS_PREPAD | | |
729 | RXMCS_FLOWCTRL | | |
730 | RXMCS_CHECKSUM, | |
d7699f87 GFT |
731 | }; |
732 | ||
b3821cc5 GFT |
733 | /* |
734 | * Wakeup Frame setup interface registers | |
735 | */ | |
736 | #define WAKEUP_FRAME_NR 8 | |
737 | #define WAKEUP_FRAME_MASK_DWNR 4 | |
738 | enum jme_wfoi_bit_masks { | |
739 | WFOI_MASK_SEL = 0x00000070, | |
740 | WFOI_CRC_SEL = 0x00000008, | |
741 | WFOI_FRAME_SEL = 0x00000007, | |
742 | }; | |
743 | enum jme_wfoi_shifts { | |
744 | WFOI_MASK_SHIFT = 4, | |
745 | }; | |
746 | ||
d7699f87 GFT |
747 | /* |
748 | * SMI Related definitions | |
749 | */ | |
750 | enum jme_smi_bit_mask | |
751 | { | |
752 | SMI_DATA_MASK = 0xFFFF0000, | |
753 | SMI_REG_ADDR_MASK = 0x0000F800, | |
754 | SMI_PHY_ADDR_MASK = 0x000007C0, | |
755 | SMI_OP_WRITE = 0x00000020, | |
3bf61c55 GFT |
756 | /* Set to 1, after req done it'll be cleared to 0 */ |
757 | SMI_OP_REQ = 0x00000010, | |
d7699f87 GFT |
758 | SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */ |
759 | SMI_OP_MDOE = 0x00000004, /* Software Output Enable */ | |
760 | SMI_OP_MDC = 0x00000002, /* Software CLK Control */ | |
761 | SMI_OP_MDEN = 0x00000001, /* Software access Enable */ | |
762 | }; | |
763 | enum jme_smi_bit_shift | |
764 | { | |
765 | SMI_DATA_SHIFT = 16, | |
766 | SMI_REG_ADDR_SHIFT = 11, | |
767 | SMI_PHY_ADDR_SHIFT = 6, | |
768 | }; | |
769 | __always_inline __u32 smi_reg_addr(int x) | |
770 | { | |
771 | return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK); | |
772 | } | |
773 | __always_inline __u32 smi_phy_addr(int x) | |
774 | { | |
775 | return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK); | |
776 | } | |
cdcdc9eb | 777 | #define JME_PHY_TIMEOUT 1000 /* 1000 msec */ |
186fc259 | 778 | #define JME_PHY_REG_NR 32 |
d7699f87 GFT |
779 | |
780 | /* | |
781 | * Global Host Control | |
782 | */ | |
783 | enum jme_ghc_bit_mask { | |
784 | GHC_SWRST = 0x40000000, | |
785 | GHC_DPX = 0x00000040, | |
786 | GHC_SPEED = 0x00000030, | |
787 | GHC_LINK_POLL = 0x00000001, | |
788 | }; | |
789 | enum jme_ghc_speed_val { | |
790 | GHC_SPEED_10M = 0x00000010, | |
791 | GHC_SPEED_100M = 0x00000020, | |
792 | GHC_SPEED_1000M = 0x00000030, | |
793 | }; | |
794 | ||
29bdd921 GFT |
795 | /* |
796 | * Power management control and status register | |
797 | */ | |
798 | enum jme_pmcs_bit_masks { | |
799 | PMCS_WF7DET = 0x80000000, | |
800 | PMCS_WF6DET = 0x40000000, | |
801 | PMCS_WF5DET = 0x20000000, | |
802 | PMCS_WF4DET = 0x10000000, | |
803 | PMCS_WF3DET = 0x08000000, | |
804 | PMCS_WF2DET = 0x04000000, | |
805 | PMCS_WF1DET = 0x02000000, | |
806 | PMCS_WF0DET = 0x01000000, | |
807 | PMCS_LFDET = 0x00040000, | |
808 | PMCS_LRDET = 0x00020000, | |
809 | PMCS_MFDET = 0x00010000, | |
810 | PMCS_WF7EN = 0x00008000, | |
811 | PMCS_WF6EN = 0x00004000, | |
812 | PMCS_WF5EN = 0x00002000, | |
813 | PMCS_WF4EN = 0x00001000, | |
814 | PMCS_WF3EN = 0x00000800, | |
815 | PMCS_WF2EN = 0x00000400, | |
816 | PMCS_WF1EN = 0x00000200, | |
817 | PMCS_WF0EN = 0x00000100, | |
818 | PMCS_LFEN = 0x00000004, | |
819 | PMCS_LREN = 0x00000002, | |
820 | PMCS_MFEN = 0x00000001, | |
821 | }; | |
822 | ||
d7699f87 | 823 | /* |
3bf61c55 | 824 | * Giga PHY Status Registers |
d7699f87 GFT |
825 | */ |
826 | enum jme_phy_link_bit_mask { | |
827 | PHY_LINK_SPEED_MASK = 0x0000C000, | |
828 | PHY_LINK_DUPLEX = 0x00002000, | |
829 | PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, | |
830 | PHY_LINK_UP = 0x00000400, | |
831 | PHY_LINK_AUTONEG_COMPLETE = 0x00000200, | |
fcf45b4c | 832 | PHY_LINK_MDI_STAT = 0x00000040, |
d7699f87 GFT |
833 | }; |
834 | enum jme_phy_link_speed_val { | |
835 | PHY_LINK_SPEED_10M = 0x00000000, | |
836 | PHY_LINK_SPEED_100M = 0x00004000, | |
837 | PHY_LINK_SPEED_1000M = 0x00008000, | |
838 | }; | |
fcf45b4c | 839 | #define JME_SPDRSV_TIMEOUT 500 /* 500 us */ |
d7699f87 GFT |
840 | |
841 | /* | |
842 | * SMB Control and Status | |
843 | */ | |
79ce639c | 844 | enum jme_smbcsr_bit_mask { |
d7699f87 GFT |
845 | SMBCSR_CNACK = 0x00020000, |
846 | SMBCSR_RELOAD = 0x00010000, | |
847 | SMBCSR_EEPROMD = 0x00000020, | |
186fc259 GFT |
848 | SMBCSR_INITDONE = 0x00000010, |
849 | SMBCSR_BUSY = 0x0000000F, | |
850 | }; | |
851 | enum jme_smbintf_bit_mask { | |
852 | SMBINTF_HWDATR = 0xFF000000, | |
853 | SMBINTF_HWDATW = 0x00FF0000, | |
854 | SMBINTF_HWADDR = 0x0000FF00, | |
855 | SMBINTF_HWRWN = 0x00000020, | |
856 | SMBINTF_HWCMD = 0x00000010, | |
857 | SMBINTF_FASTM = 0x00000008, | |
858 | SMBINTF_GPIOSCL = 0x00000004, | |
859 | SMBINTF_GPIOSDA = 0x00000002, | |
860 | SMBINTF_GPIOEN = 0x00000001, | |
861 | }; | |
862 | enum jme_smbintf_vals { | |
863 | SMBINTF_HWRWN_READ = 0x00000020, | |
864 | SMBINTF_HWRWN_WRITE = 0x00000000, | |
865 | }; | |
866 | enum jme_smbintf_shifts { | |
867 | SMBINTF_HWDATR_SHIFT = 24, | |
868 | SMBINTF_HWDATW_SHIFT = 16, | |
869 | SMBINTF_HWADDR_SHIFT = 8, | |
870 | }; | |
871 | #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ | |
872 | #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ | |
873 | #define JME_SMB_LEN 256 | |
874 | #define JME_EEPROM_MAGIC 0x250 | |
d7699f87 | 875 | |
79ce639c GFT |
876 | /* |
877 | * Timer Control/Status Register | |
878 | */ | |
879 | enum jme_tmcsr_bit_masks { | |
880 | TMCSR_SWIT = 0x80000000, | |
881 | TMCSR_EN = 0x01000000, | |
882 | TMCSR_CNT = 0x00FFFFFF, | |
883 | }; | |
884 | ||
d7699f87 | 885 | |
4330c2f2 GFT |
886 | /* |
887 | * General Purpost REG-0 | |
888 | */ | |
889 | enum jme_gpreg0_masks { | |
3bf61c55 GFT |
890 | GPREG0_DISSH = 0xFF000000, |
891 | GPREG0_PCIRLMT = 0x00300000, | |
892 | GPREG0_PCCNOMUTCLR = 0x00040000, | |
cdcdc9eb | 893 | GPREG0_LNKINTPOLL = 0x00001000, |
3bf61c55 GFT |
894 | GPREG0_PCCTMR = 0x00000300, |
895 | GPREG0_PHYADDR = 0x0000001F, | |
4330c2f2 GFT |
896 | }; |
897 | enum jme_gpreg0_vals { | |
898 | GPREG0_DISSH_DW7 = 0x80000000, | |
899 | GPREG0_DISSH_DW6 = 0x40000000, | |
900 | GPREG0_DISSH_DW5 = 0x20000000, | |
901 | GPREG0_DISSH_DW4 = 0x10000000, | |
902 | GPREG0_DISSH_DW3 = 0x08000000, | |
903 | GPREG0_DISSH_DW2 = 0x04000000, | |
904 | GPREG0_DISSH_DW1 = 0x02000000, | |
905 | GPREG0_DISSH_DW0 = 0x01000000, | |
906 | GPREG0_DISSH_ALL = 0xFF000000, | |
907 | ||
908 | GPREG0_PCIRLMT_8 = 0x00000000, | |
909 | GPREG0_PCIRLMT_6 = 0x00100000, | |
910 | GPREG0_PCIRLMT_5 = 0x00200000, | |
911 | GPREG0_PCIRLMT_4 = 0x00300000, | |
912 | ||
913 | GPREG0_PCCTMR_16ns = 0x00000000, | |
3bf61c55 GFT |
914 | GPREG0_PCCTMR_256ns = 0x00000100, |
915 | GPREG0_PCCTMR_1us = 0x00000200, | |
916 | GPREG0_PCCTMR_1ms = 0x00000300, | |
4330c2f2 GFT |
917 | |
918 | GPREG0_PHYADDR_1 = 0x00000001, | |
919 | ||
920 | GPREG0_DEFAULT = GPREG0_PCIRLMT_4 | | |
3bf61c55 GFT |
921 | GPREG0_PCCNOMUTCLR | |
922 | GPREG0_PCCTMR_1us | | |
923 | GPREG0_PHYADDR_1, | |
4330c2f2 GFT |
924 | }; |
925 | ||
d7699f87 GFT |
926 | /* |
927 | * Interrupt Status Bits | |
928 | */ | |
929 | enum jme_interrupt_bits | |
930 | { | |
931 | INTR_SWINTR = 0x80000000, | |
932 | INTR_TMINTR = 0x40000000, | |
933 | INTR_LINKCH = 0x20000000, | |
934 | INTR_PAUSERCV = 0x10000000, | |
935 | INTR_MAGICRCV = 0x08000000, | |
936 | INTR_WAKERCV = 0x04000000, | |
937 | INTR_PCCRX0TO = 0x02000000, | |
938 | INTR_PCCRX1TO = 0x01000000, | |
939 | INTR_PCCRX2TO = 0x00800000, | |
940 | INTR_PCCRX3TO = 0x00400000, | |
941 | INTR_PCCTXTO = 0x00200000, | |
942 | INTR_PCCRX0 = 0x00100000, | |
943 | INTR_PCCRX1 = 0x00080000, | |
944 | INTR_PCCRX2 = 0x00040000, | |
945 | INTR_PCCRX3 = 0x00020000, | |
946 | INTR_PCCTX = 0x00010000, | |
947 | INTR_RX3EMP = 0x00008000, | |
948 | INTR_RX2EMP = 0x00004000, | |
949 | INTR_RX1EMP = 0x00002000, | |
950 | INTR_RX0EMP = 0x00001000, | |
951 | INTR_RX3 = 0x00000800, | |
952 | INTR_RX2 = 0x00000400, | |
953 | INTR_RX1 = 0x00000200, | |
954 | INTR_RX0 = 0x00000100, | |
955 | INTR_TX7 = 0x00000080, | |
956 | INTR_TX6 = 0x00000040, | |
957 | INTR_TX5 = 0x00000020, | |
958 | INTR_TX4 = 0x00000010, | |
959 | INTR_TX3 = 0x00000008, | |
960 | INTR_TX2 = 0x00000004, | |
961 | INTR_TX1 = 0x00000002, | |
962 | INTR_TX0 = 0x00000001, | |
963 | }; | |
79ce639c GFT |
964 | static const __u32 INTR_ENABLE = INTR_SWINTR | |
965 | INTR_TMINTR | | |
966 | INTR_LINKCH | | |
3bf61c55 GFT |
967 | INTR_PCCRX0TO | |
968 | INTR_PCCRX0 | | |
969 | INTR_PCCTXTO | | |
cdcdc9eb GFT |
970 | INTR_PCCTX | |
971 | INTR_RX0EMP; | |
3bf61c55 GFT |
972 | |
973 | /* | |
974 | * PCC Control Registers | |
975 | */ | |
976 | enum jme_pccrx_masks { | |
977 | PCCRXTO_MASK = 0xFFFF0000, | |
978 | PCCRX_MASK = 0x0000FF00, | |
979 | }; | |
980 | enum jme_pcctx_masks { | |
981 | PCCTXTO_MASK = 0xFFFF0000, | |
982 | PCCTX_MASK = 0x0000FF00, | |
983 | PCCTX_QS_MASK = 0x000000FF, | |
984 | }; | |
985 | enum jme_pccrx_shifts { | |
986 | PCCRXTO_SHIFT = 16, | |
987 | PCCRX_SHIFT = 8, | |
988 | }; | |
989 | enum jme_pcctx_shifts { | |
990 | PCCTXTO_SHIFT = 16, | |
991 | PCCTX_SHIFT = 8, | |
992 | }; | |
993 | enum jme_pcctx_bits { | |
994 | PCCTXQ0_EN = 0x00000001, | |
995 | PCCTXQ1_EN = 0x00000002, | |
996 | PCCTXQ2_EN = 0x00000004, | |
997 | PCCTXQ3_EN = 0x00000008, | |
998 | PCCTXQ4_EN = 0x00000010, | |
999 | PCCTXQ5_EN = 0x00000020, | |
1000 | PCCTXQ6_EN = 0x00000040, | |
1001 | PCCTXQ7_EN = 0x00000080, | |
1002 | }; | |
1003 | ||
cdcdc9eb GFT |
1004 | /* |
1005 | * Chip Mode Register | |
1006 | */ | |
1007 | enum jme_chipmode_bit_masks { | |
1008 | CM_FPGAVER_MASK = 0xFFFF0000, | |
1009 | CM_CHIPVER_MASK = 0x0000FF00, | |
1010 | CM_CHIPMODE_MASK = 0x0000000F, | |
1011 | }; | |
1012 | enum jme_chipmode_shifts { | |
1013 | CM_FPGAVER_SHIFT = 16, | |
1014 | CM_CHIPVER_SHIFT = 8, | |
1015 | }; | |
d7699f87 | 1016 | |
4330c2f2 GFT |
1017 | /* |
1018 | * Shadow base address register bits | |
1019 | */ | |
1020 | enum jme_shadow_base_address_bits { | |
1021 | SHBA_POSTEN = 0x1, | |
1022 | }; | |
1023 | ||
d7699f87 GFT |
1024 | /* |
1025 | * Read/Write MMaped I/O Registers | |
1026 | */ | |
1027 | __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg) | |
1028 | { | |
79ce639c | 1029 | return le32_to_cpu(readl((__u8*)jme->regs + reg)); |
d7699f87 GFT |
1030 | } |
1031 | __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val) | |
1032 | { | |
79ce639c | 1033 | writel(cpu_to_le32(val), (__u8*)jme->regs + reg); |
d7699f87 GFT |
1034 | } |
1035 | __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) | |
1036 | { | |
1037 | /* | |
1038 | * Read after write should cause flush | |
1039 | */ | |
79ce639c GFT |
1040 | writel(cpu_to_le32(val), (__u8*)jme->regs + reg); |
1041 | readl((__u8*)jme->regs + reg); | |
d7699f87 GFT |
1042 | } |
1043 | ||
cdcdc9eb GFT |
1044 | /* |
1045 | * PHY Regs | |
1046 | */ | |
1047 | enum jme_phy_reg17_bit_masks { | |
1048 | PREG17_SPEED = 0xC000, | |
1049 | PREG17_DUPLEX = 0x2000, | |
1050 | PREG17_SPDRSV = 0x0800, | |
1051 | PREG17_LNKUP = 0x0400, | |
1052 | PREG17_MDI = 0x0040, | |
1053 | }; | |
1054 | enum jme_phy_reg17_vals { | |
1055 | PREG17_SPEED_10M = 0x0000, | |
1056 | PREG17_SPEED_100M = 0x4000, | |
1057 | PREG17_SPEED_1000M = 0x8000, | |
1058 | }; | |
1059 | #define BMCR_ANCOMP 0x0020 | |
1060 | ||
d7699f87 GFT |
1061 | /* |
1062 | * Function prototypes for ethtool | |
1063 | */ | |
1064 | static void jme_get_drvinfo(struct net_device *netdev, | |
1065 | struct ethtool_drvinfo *info); | |
1066 | static int jme_get_settings(struct net_device *netdev, | |
1067 | struct ethtool_cmd *ecmd); | |
1068 | static int jme_set_settings(struct net_device *netdev, | |
1069 | struct ethtool_cmd *ecmd); | |
1070 | static u32 jme_get_link(struct net_device *netdev); | |
1071 | ||
1072 | ||
1073 | /* | |
1074 | * Function prototypes for netdev | |
1075 | */ | |
1076 | static int jme_open(struct net_device *netdev); | |
1077 | static int jme_close(struct net_device *netdev); | |
1078 | static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev); | |
1079 | static int jme_set_macaddr(struct net_device *netdev, void *p); | |
1080 | static void jme_set_multi(struct net_device *netdev); | |
1081 |