jme: Support WoL after shutdown
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
52a46ba8
JP
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
d7699f87
GFT
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
4330c2f2 35#include <linux/delay.h>
29bdd921 36#include <linux/spinlock.h>
8c198884
GFT
37#include <linux/in.h>
38#include <linux/ip.h>
79ce639c
GFT
39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42b1055e 42#include <linux/if_vlan.h>
6d641c63 43#include <linux/slab.h>
94c5ea02 44#include <net/ip6_checksum.h>
d7699f87
GFT
45#include "jme.h"
46
cd0ff491
GFT
47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 58
3bf61c55
GFT
59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
61{
62 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 64
186fc259 65read_again:
cd0ff491 66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
d7699f87
GFT
69
70 wmb();
cd0ff491 71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 72 udelay(20);
b3821cc5
GFT
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
3bf61c55 75 break;
cd0ff491 76 }
d7699f87 77
cd0ff491 78 if (i == 0) {
52a46ba8 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 80 return 0;
cd0ff491 81 }
d7699f87 82
cd0ff491 83 if (again--)
186fc259
GFT
84 goto read_again;
85
cd0ff491 86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
87}
88
3bf61c55
GFT
89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
d7699f87
GFT
92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
3bf61c55
GFT
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
99
100 wmb();
cdcdc9eb
GFT
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
8d27293f 103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
104 break;
105 }
d7699f87 106
3bf61c55 107 if (i == 0)
52a46ba8 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
109}
110
cd0ff491 111static inline void
3bf61c55 112jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 113{
cd0ff491 114 u32 val;
3bf61c55
GFT
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
8c198884
GFT
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 120
cd0ff491 121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 126
fcf45b4c
GFT
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
134}
135
b3821cc5
GFT
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 138 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
cd0ff491 163static inline void
3bf61c55
GFT
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
cd0ff491
GFT
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
b3821cc5
GFT
169 int i;
170
3bf61c55 171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 172 udelay(2);
3bf61c55 173 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
4330c2f2
GFT
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 187 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 188 if (jme->fpgaver)
cdcdc9eb
GFT
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
9b9d55de 193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
194}
195
cd0ff491
GFT
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
3bf61c55 204jme_clear_pm(struct jme_adapter *jme)
d7699f87 205{
29bdd921 206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 207 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 208 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
209}
210
3bf61c55
GFT
211static int
212jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 213{
cd0ff491 214 u32 val;
d7699f87
GFT
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
cd0ff491 219 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
cd0ff491 226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
cd0ff491 232 if (i == 0) {
52a46ba8 233 pr_err("eeprom reload timeout\n");
d7699f87
GFT
234 return -EIO;
235 }
236 }
3bf61c55 237
d7699f87
GFT
238 return 0;
239}
240
3bf61c55
GFT
241static void
242jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
cd0ff491 246 u32 val;
d7699f87 247
cd0ff491 248 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 249 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 254 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
259}
260
cd0ff491 261static inline void
3bf61c55
GFT
262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
cd0ff491 264 switch (p) {
192570e0
GFT
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
3bf61c55
GFT
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
192570e0 288 wmb();
3bf61c55 289
cd0ff491 290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
292}
293
fcf45b4c 294static void
3bf61c55 295jme_start_irq(struct jme_adapter *jme)
d7699f87 296{
3bf61c55
GFT
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
8c198884
GFT
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
307 PCCTXQ0_EN
308 );
309
d7699f87
GFT
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
cd0ff491 316static inline void
3bf61c55 317jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
318{
319 /*
320 * Disable Interrupts
321 */
cd0ff491 322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
323}
324
cd0ff491 325static u32
cdcdc9eb
GFT
326jme_linkstat_from_phy(struct jme_adapter *jme)
327{
cd0ff491 328 u32 phylink, bmsr;
cdcdc9eb
GFT
329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 332 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336}
337
cd0ff491 338static inline void
e882564f 339jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
340{
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342}
343
344static inline void
e882564f 345jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
346{
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348}
349
fcf45b4c
GFT
350static int
351jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
352{
353 struct jme_adapter *jme = netdev_priv(netdev);
9b9d55de 354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 355 char linkmsg[64];
fcf45b4c 356 int rc = 0;
d7699f87 357
b3821cc5 358 linkmsg[0] = '\0';
cdcdc9eb 359
cd0ff491 360 if (jme->fpgaver)
cdcdc9eb
GFT
361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 364
cd0ff491
GFT
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
79ce639c 386
b3821cc5 387 strcat(linkmsg, "Forced: ");
cd0ff491 388 } else {
8c198884
GFT
389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
cd0ff491 392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
393 --cnt) {
394
395 udelay(1);
8c198884 396
cd0ff491 397 if (jme->fpgaver)
cdcdc9eb
GFT
398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
8c198884 401 }
cd0ff491 402 if (!cnt)
52a46ba8 403 pr_err("Waiting speed resolve timeout\n");
79ce639c 404
b3821cc5 405 strcat(linkmsg, "ANed: ");
d7699f87
GFT
406 }
407
cd0ff491 408 if (jme->phylink == phylink) {
fcf45b4c
GFT
409 rc = 1;
410 goto out;
411 }
cd0ff491 412 if (testonly)
fcf45b4c
GFT
413 goto out;
414
415 jme->phylink = phylink;
416
94c5ea02
GFT
417 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
418 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
419 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT
420 switch (phylink & PHY_LINK_SPEED_MASK) {
421 case PHY_LINK_SPEED_10M:
94c5ea02
GFT
422 ghc |= GHC_SPEED_10M |
423 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 424 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
425 break;
426 case PHY_LINK_SPEED_100M:
94c5ea02
GFT
427 ghc |= GHC_SPEED_100M |
428 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 429 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
430 break;
431 case PHY_LINK_SPEED_1000M:
94c5ea02
GFT
432 ghc |= GHC_SPEED_1000M |
433 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 434 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
435 break;
436 default:
437 break;
d7699f87 438 }
d7699f87 439
cd0ff491 440 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 441 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
9b9d55de 442 ghc |= GHC_DPX;
cd0ff491 443 } else {
d7699f87 444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
445 TXMCS_BACKOFF |
446 TXMCS_CARRIERSENSE |
447 TXMCS_COLLISION);
8c198884
GFT
448 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
449 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450 TXTRHD_TXREN |
451 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
452 }
9b9d55de
GFT
453
454 gpreg1 = GPREG1_DEFAULT;
455 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
456 if (!(phylink & PHY_LINK_DUPLEX))
457 gpreg1 |= GPREG1_HALFMODEPATCH;
458 switch (phylink & PHY_LINK_SPEED_MASK) {
459 case PHY_LINK_SPEED_10M:
460 jme_set_phyfifoa(jme);
461 gpreg1 |= GPREG1_RSSPATCH;
462 break;
463 case PHY_LINK_SPEED_100M:
464 jme_set_phyfifob(jme);
465 gpreg1 |= GPREG1_RSSPATCH;
466 break;
467 case PHY_LINK_SPEED_1000M:
468 jme_set_phyfifoa(jme);
469 break;
470 default:
471 break;
472 }
473 }
d7699f87 474
94c5ea02 475 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 476 jwrite32(jme, JME_GHC, ghc);
94c5ea02 477 jme->reg_ghc = ghc;
fcf45b4c 478
94c5ea02
GFT
479 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
480 "Full-Duplex, " :
481 "Half-Duplex, ");
482 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
483 "MDI-X" :
484 "MDI");
52a46ba8 485 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
486 netif_carrier_on(netdev);
487 } else {
488 if (testonly)
fcf45b4c
GFT
489 goto out;
490
52a46ba8 491 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 492 jme->phylink = 0;
cd0ff491 493 netif_carrier_off(netdev);
d7699f87 494 }
fcf45b4c
GFT
495
496out:
497 return rc;
d7699f87
GFT
498}
499
3bf61c55
GFT
500static int
501jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 502{
d7699f87
GFT
503 struct jme_ring *txring = &(jme->txring[0]);
504
505 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
506 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
507 &(txring->dmaalloc),
508 GFP_ATOMIC);
fcf45b4c 509
fa97b924
GFT
510 if (!txring->alloc)
511 goto err_set_null;
d7699f87
GFT
512
513 /*
514 * 16 Bytes align
515 */
cd0ff491 516 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 517 RING_DESC_ALIGN);
4330c2f2 518 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 519 txring->next_to_use = 0;
cdcdc9eb 520 atomic_set(&txring->next_to_clean, 0);
b3821cc5 521 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 522
fa97b924
GFT
523 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
524 jme->tx_ring_size, GFP_ATOMIC);
525 if (unlikely(!(txring->bufinf)))
526 goto err_free_txring;
527
d7699f87 528 /*
b3821cc5 529 * Initialize Transmit Descriptors
d7699f87 530 */
b3821cc5 531 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 532 memset(txring->bufinf, 0,
b3821cc5 533 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
534
535 return 0;
fa97b924
GFT
536
537err_free_txring:
538 dma_free_coherent(&(jme->pdev->dev),
539 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
540 txring->alloc,
541 txring->dmaalloc);
542
543err_set_null:
544 txring->desc = NULL;
545 txring->dmaalloc = 0;
546 txring->dma = 0;
547 txring->bufinf = NULL;
548
549 return -ENOMEM;
d7699f87
GFT
550}
551
3bf61c55
GFT
552static void
553jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
554{
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 557 struct jme_buffer_info *txbi;
d7699f87 558
cd0ff491 559 if (txring->alloc) {
fa97b924
GFT
560 if (txring->bufinf) {
561 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
562 txbi = txring->bufinf + i;
563 if (txbi->skb) {
564 dev_kfree_skb(txbi->skb);
565 txbi->skb = NULL;
566 }
567 txbi->mapping = 0;
568 txbi->len = 0;
569 txbi->nr_desc = 0;
570 txbi->start_xmit = 0;
d7699f87 571 }
fa97b924 572 kfree(txring->bufinf);
d7699f87
GFT
573 }
574
575 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 576 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
577 txring->alloc,
578 txring->dmaalloc);
3bf61c55
GFT
579
580 txring->alloc = NULL;
581 txring->desc = NULL;
582 txring->dmaalloc = 0;
583 txring->dma = 0;
fa97b924 584 txring->bufinf = NULL;
d7699f87 585 }
3bf61c55 586 txring->next_to_use = 0;
cdcdc9eb 587 atomic_set(&txring->next_to_clean, 0);
79ce639c 588 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
589}
590
cd0ff491 591static inline void
3bf61c55 592jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
593{
594 /*
595 * Select Queue 0
596 */
597 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 598 wmb();
d7699f87
GFT
599
600 /*
601 * Setup TX Queue 0 DMA Bass Address
602 */
fcf45b4c 603 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 604 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 605 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
606
607 /*
608 * Setup TX Descptor Count
609 */
b3821cc5 610 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
611
612 /*
613 * Enable TX Engine
614 */
615 wmb();
4330c2f2
GFT
616 jwrite32(jme, JME_TXCS, jme->reg_txcs |
617 TXCS_SELECT_QUEUE0 |
618 TXCS_ENABLE);
d7699f87
GFT
619
620}
621
cd0ff491 622static inline void
29bdd921
GFT
623jme_restart_tx_engine(struct jme_adapter *jme)
624{
625 /*
626 * Restart TX Engine
627 */
628 jwrite32(jme, JME_TXCS, jme->reg_txcs |
629 TXCS_SELECT_QUEUE0 |
630 TXCS_ENABLE);
631}
632
cd0ff491 633static inline void
3bf61c55 634jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
635{
636 int i;
cd0ff491 637 u32 val;
d7699f87
GFT
638
639 /*
640 * Disable TX Engine
641 */
fcf45b4c 642 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 643 wmb();
d7699f87
GFT
644
645 val = jread32(jme, JME_TXCS);
cd0ff491 646 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 647 mdelay(1);
d7699f87 648 val = jread32(jme, JME_TXCS);
cd0ff491 649 rmb();
d7699f87
GFT
650 }
651
cd0ff491 652 if (!i)
52a46ba8 653 pr_err("Disable TX engine timeout\n");
d7699f87
GFT
654}
655
3bf61c55
GFT
656static void
657jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 658{
fa97b924 659 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 660 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
661 struct jme_buffer_info *rxbi = rxring->bufinf;
662 rxdesc += i;
663 rxbi += i;
664
665 rxdesc->dw[0] = 0;
666 rxdesc->dw[1] = 0;
3bf61c55 667 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
668 rxdesc->desc1.bufaddrl = cpu_to_le32(
669 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 670 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 671 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 672 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 673 wmb();
3bf61c55 674 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
675}
676
3bf61c55
GFT
677static int
678jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
679{
680 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 681 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 682 struct sk_buff *skb;
4330c2f2 683
79ce639c
GFT
684 skb = netdev_alloc_skb(jme->dev,
685 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 686 if (unlikely(!skb))
4330c2f2 687 return -ENOMEM;
3bf61c55 688
4330c2f2 689 rxbi->skb = skb;
3bf61c55 690 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
691 rxbi->mapping = pci_map_page(jme->pdev,
692 virt_to_page(skb->data),
693 offset_in_page(skb->data),
694 rxbi->len,
695 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
696
697 return 0;
698}
699
3bf61c55
GFT
700static void
701jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
702{
703 struct jme_ring *rxring = &(jme->rxring[0]);
704 struct jme_buffer_info *rxbi = rxring->bufinf;
705 rxbi += i;
706
cd0ff491 707 if (rxbi->skb) {
b3821cc5 708 pci_unmap_page(jme->pdev,
4330c2f2 709 rxbi->mapping,
3bf61c55 710 rxbi->len,
4330c2f2
GFT
711 PCI_DMA_FROMDEVICE);
712 dev_kfree_skb(rxbi->skb);
713 rxbi->skb = NULL;
714 rxbi->mapping = 0;
3bf61c55 715 rxbi->len = 0;
4330c2f2
GFT
716 }
717}
718
3bf61c55
GFT
719static void
720jme_free_rx_resources(struct jme_adapter *jme)
721{
722 int i;
723 struct jme_ring *rxring = &(jme->rxring[0]);
724
cd0ff491 725 if (rxring->alloc) {
fa97b924
GFT
726 if (rxring->bufinf) {
727 for (i = 0 ; i < jme->rx_ring_size ; ++i)
728 jme_free_rx_buf(jme, i);
729 kfree(rxring->bufinf);
730 }
3bf61c55
GFT
731
732 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 733 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
734 rxring->alloc,
735 rxring->dmaalloc);
736 rxring->alloc = NULL;
737 rxring->desc = NULL;
738 rxring->dmaalloc = 0;
739 rxring->dma = 0;
fa97b924 740 rxring->bufinf = NULL;
3bf61c55
GFT
741 }
742 rxring->next_to_use = 0;
cdcdc9eb 743 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
744}
745
746static int
747jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
748{
749 int i;
750 struct jme_ring *rxring = &(jme->rxring[0]);
751
752 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
753 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
754 &(rxring->dmaalloc),
755 GFP_ATOMIC);
fa97b924
GFT
756 if (!rxring->alloc)
757 goto err_set_null;
d7699f87
GFT
758
759 /*
760 * 16 Bytes align
761 */
cd0ff491 762 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 763 RING_DESC_ALIGN);
4330c2f2 764 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 765 rxring->next_to_use = 0;
cdcdc9eb 766 atomic_set(&rxring->next_to_clean, 0);
d7699f87 767
fa97b924
GFT
768 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
769 jme->rx_ring_size, GFP_ATOMIC);
770 if (unlikely(!(rxring->bufinf)))
771 goto err_free_rxring;
772
d7699f87
GFT
773 /*
774 * Initiallize Receive Descriptors
775 */
fa97b924
GFT
776 memset(rxring->bufinf, 0,
777 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
778 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
779 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
780 jme_free_rx_resources(jme);
781 return -ENOMEM;
782 }
d7699f87
GFT
783
784 jme_set_clean_rxdesc(jme, i);
785 }
786
d7699f87 787 return 0;
fa97b924
GFT
788
789err_free_rxring:
790 dma_free_coherent(&(jme->pdev->dev),
791 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
792 rxring->alloc,
793 rxring->dmaalloc);
794err_set_null:
795 rxring->desc = NULL;
796 rxring->dmaalloc = 0;
797 rxring->dma = 0;
798 rxring->bufinf = NULL;
799
800 return -ENOMEM;
d7699f87
GFT
801}
802
cd0ff491 803static inline void
3bf61c55 804jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 805{
cd0ff491
GFT
806 /*
807 * Select Queue 0
808 */
809 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
810 RXCS_QUEUESEL_Q0);
811 wmb();
812
d7699f87
GFT
813 /*
814 * Setup RX DMA Bass Address
815 */
fa97b924 816 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 817 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 818 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
819
820 /*
b3821cc5 821 * Setup RX Descriptor Count
d7699f87 822 */
b3821cc5 823 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 824
3bf61c55 825 /*
d7699f87
GFT
826 * Setup Unicast Filter
827 */
828 jme_set_multi(jme->dev);
829
830 /*
831 * Enable RX Engine
832 */
833 wmb();
79ce639c 834 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
835 RXCS_QUEUESEL_Q0 |
836 RXCS_ENABLE |
837 RXCS_QST);
d7699f87
GFT
838}
839
cd0ff491 840static inline void
3bf61c55 841jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
842{
843 /*
3bf61c55 844 * Start RX Engine
4330c2f2 845 */
79ce639c 846 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
847 RXCS_QUEUESEL_Q0 |
848 RXCS_ENABLE |
849 RXCS_QST);
850}
851
cd0ff491 852static inline void
3bf61c55 853jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
854{
855 int i;
cd0ff491 856 u32 val;
d7699f87
GFT
857
858 /*
859 * Disable RX Engine
860 */
29bdd921 861 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 862 wmb();
d7699f87
GFT
863
864 val = jread32(jme, JME_RXCS);
cd0ff491 865 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 866 mdelay(1);
d7699f87 867 val = jread32(jme, JME_RXCS);
cd0ff491 868 rmb();
d7699f87
GFT
869 }
870
cd0ff491 871 if (!i)
52a46ba8 872 pr_err("Disable RX engine timeout\n");
d7699f87
GFT
873
874}
875
192570e0 876static int
cd0ff491 877jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 878{
cd0ff491 879 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
880 return false;
881
fa97b924
GFT
882 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
883 == RXWBFLAG_TCPON)) {
884 if (flags & RXWBFLAG_IPV4)
c97b5740 885 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 886 return false;
192570e0
GFT
887 }
888
fa97b924
GFT
889 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
890 == RXWBFLAG_UDPON)) {
891 if (flags & RXWBFLAG_IPV4)
52a46ba8 892 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
fa97b924 893 return false;
192570e0
GFT
894 }
895
fa97b924
GFT
896 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
897 == RXWBFLAG_IPV4)) {
52a46ba8 898 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
fa97b924 899 return false;
192570e0
GFT
900 }
901
902 return true;
903}
904
3bf61c55 905static void
42b1055e 906jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 907{
d7699f87 908 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 909 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 910 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 911 struct sk_buff *skb;
3bf61c55 912 int framesize;
d7699f87 913
3bf61c55
GFT
914 rxdesc += idx;
915 rxbi += idx;
d7699f87 916
3bf61c55
GFT
917 skb = rxbi->skb;
918 pci_dma_sync_single_for_cpu(jme->pdev,
919 rxbi->mapping,
920 rxbi->len,
921 PCI_DMA_FROMDEVICE);
922
cd0ff491 923 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
924 pci_dma_sync_single_for_device(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
929 ++(NET_STAT(jme).rx_dropped);
cd0ff491 930 } else {
3bf61c55
GFT
931 framesize = le16_to_cpu(rxdesc->descwb.framesize)
932 - RX_PREPAD_SIZE;
933
934 skb_reserve(skb, RX_PREPAD_SIZE);
935 skb_put(skb, framesize);
936 skb->protocol = eth_type_trans(skb, jme->dev);
937
94c5ea02 938 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 939 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 940 else
97984ab7 941 skb_checksum_none_assert(skb);
8c198884 942
94c5ea02 943 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 944 if (jme->vlgrp) {
cdcdc9eb 945 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 946 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 947 NET_STAT(jme).rx_bytes += 4;
c97b5740 948 } else {
c97b5740 949 dev_kfree_skb(skb);
b3821cc5 950 }
cd0ff491 951 } else {
cdcdc9eb 952 jme->jme_rx(skb);
b3821cc5 953 }
3bf61c55 954
94c5ea02
GFT
955 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
956 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
957 ++(NET_STAT(jme).multicast);
958
3bf61c55
GFT
959 NET_STAT(jme).rx_bytes += framesize;
960 ++(NET_STAT(jme).rx_packets);
961 }
962
963 jme_set_clean_rxdesc(jme, idx);
964
965}
966
967static int
968jme_process_receive(struct jme_adapter *jme, int limit)
969{
970 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 971 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 972 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 973
cd0ff491 974 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
975 goto out_inc;
976
cd0ff491 977 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
978 goto out_inc;
979
cd0ff491 980 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
981 goto out_inc;
982
cdcdc9eb 983 i = atomic_read(&rxring->next_to_clean);
fa97b924 984 while (limit > 0) {
3bf61c55
GFT
985 rxdesc = rxring->desc;
986 rxdesc += i;
987
94c5ea02 988 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
989 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
990 goto out;
fa97b924 991 --limit;
d7699f87 992
1a7a122d 993 rmb();
4330c2f2
GFT
994 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995
cd0ff491 996 if (unlikely(desccnt > 1 ||
192570e0 997 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 998
cd0ff491 999 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1000 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1001 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1002 ++(NET_STAT(jme).rx_fifo_errors);
1003 else
1004 ++(NET_STAT(jme).rx_errors);
4330c2f2 1005
cd0ff491 1006 if (desccnt > 1)
3bf61c55 1007 limit -= desccnt - 1;
4330c2f2 1008
cd0ff491 1009 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1010 jme_set_clean_rxdesc(jme, j);
b3821cc5 1011 j = (j + 1) & (mask);
4330c2f2 1012 }
3bf61c55 1013
cd0ff491 1014 } else {
42b1055e 1015 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1016 }
4330c2f2 1017
b3821cc5 1018 i = (i + desccnt) & (mask);
3bf61c55 1019 }
4330c2f2 1020
3bf61c55 1021out:
cdcdc9eb 1022 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1023
192570e0
GFT
1024out_inc:
1025 atomic_inc(&jme->rx_cleaning);
1026
3bf61c55 1027 return limit > 0 ? limit : 0;
4330c2f2 1028
3bf61c55 1029}
d7699f87 1030
79ce639c
GFT
1031static void
1032jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033{
cd0ff491 1034 if (likely(atmp == dpi->cur)) {
192570e0 1035 dpi->cnt = 0;
79ce639c 1036 return;
192570e0 1037 }
79ce639c 1038
cd0ff491 1039 if (dpi->attempt == atmp) {
79ce639c 1040 ++(dpi->cnt);
cd0ff491 1041 } else {
79ce639c
GFT
1042 dpi->attempt = atmp;
1043 dpi->cnt = 0;
1044 }
1045
1046}
1047
1048static void
1049jme_dynamic_pcc(struct jme_adapter *jme)
1050{
1051 register struct dynpcc_info *dpi = &(jme->dpi);
1052
cd0ff491 1053 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1054 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT
1055 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1056 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1057 jme_attempt_pcc(dpi, PCC_P2);
1058 else
1059 jme_attempt_pcc(dpi, PCC_P1);
1060
cd0ff491
GFT
1061 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062 if (dpi->attempt < dpi->cur)
1063 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1064 jme_set_rx_pcc(jme, dpi->attempt);
1065 dpi->cur = dpi->attempt;
1066 dpi->cnt = 0;
1067 }
1068}
1069
1070static void
1071jme_start_pcc_timer(struct jme_adapter *jme)
1072{
1073 struct dynpcc_info *dpi = &(jme->dpi);
1074 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1075 dpi->last_pkts = NET_STAT(jme).rx_packets;
1076 dpi->intr_cnt = 0;
1077 jwrite32(jme, JME_TMCSR,
1078 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1079}
1080
cd0ff491 1081static inline void
29bdd921
GFT
1082jme_stop_pcc_timer(struct jme_adapter *jme)
1083{
1084 jwrite32(jme, JME_TMCSR, 0);
1085}
1086
cd0ff491
GFT
1087static void
1088jme_shutdown_nic(struct jme_adapter *jme)
1089{
1090 u32 phylink;
1091
1092 phylink = jme_linkstat_from_phy(jme);
1093
1094 if (!(phylink & PHY_LINK_UP)) {
1095 /*
1096 * Disable all interrupt before issue timer
1097 */
1098 jme_stop_irq(jme);
1099 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1100 }
1101}
1102
79ce639c
GFT
1103static void
1104jme_pcc_tasklet(unsigned long arg)
1105{
cd0ff491 1106 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1107 struct net_device *netdev = jme->dev;
1108
cd0ff491
GFT
1109 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110 jme_shutdown_nic(jme);
1111 return;
1112 }
29bdd921 1113
cd0ff491 1114 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1115 (atomic_read(&jme->link_changing) != 1)
1116 )) {
1117 jme_stop_pcc_timer(jme);
79ce639c
GFT
1118 return;
1119 }
29bdd921 1120
cd0ff491 1121 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1122 jme_dynamic_pcc(jme);
1123
79ce639c
GFT
1124 jme_start_pcc_timer(jme);
1125}
1126
cd0ff491 1127static inline void
192570e0
GFT
1128jme_polling_mode(struct jme_adapter *jme)
1129{
1130 jme_set_rx_pcc(jme, PCC_OFF);
1131}
1132
cd0ff491 1133static inline void
192570e0
GFT
1134jme_interrupt_mode(struct jme_adapter *jme)
1135{
1136 jme_set_rx_pcc(jme, PCC_P1);
1137}
1138
cd0ff491
GFT
1139static inline int
1140jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141{
1142 u32 apmc;
1143 apmc = jread32(jme, JME_APMC);
1144 return apmc & JME_APMC_PSEUDO_HP_EN;
1145}
1146
1147static void
1148jme_start_shutdown_timer(struct jme_adapter *jme)
1149{
1150 u32 apmc;
1151
1152 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153 apmc &= ~JME_APMC_EPIEN_CTRL;
1154 if (!no_extplug) {
1155 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156 wmb();
1157 }
1158 jwrite32f(jme, JME_APMC, apmc);
1159
1160 jwrite32f(jme, JME_TIMER2, 0);
1161 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162 jwrite32(jme, JME_TMCSR,
1163 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1164}
1165
1166static void
1167jme_stop_shutdown_timer(struct jme_adapter *jme)
1168{
1169 u32 apmc;
1170
1171 jwrite32f(jme, JME_TMCSR, 0);
1172 jwrite32f(jme, JME_TIMER2, 0);
1173 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174
1175 apmc = jread32(jme, JME_APMC);
1176 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178 wmb();
1179 jwrite32f(jme, JME_APMC, apmc);
1180}
1181
3bf61c55
GFT
1182static void
1183jme_link_change_tasklet(unsigned long arg)
1184{
cd0ff491 1185 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1186 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1187 int rc;
1188
cd0ff491
GFT
1189 while (!atomic_dec_and_test(&jme->link_changing)) {
1190 atomic_inc(&jme->link_changing);
52a46ba8 1191 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
e882564f 1192 while (atomic_read(&jme->link_changing) != 1)
52a46ba8 1193 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1194 }
fcf45b4c 1195
cd0ff491 1196 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1197 goto out;
1198
29bdd921 1199 jme->old_mtu = netdev->mtu;
fcf45b4c 1200 netif_stop_queue(netdev);
cd0ff491
GFT
1201 if (jme_pseudo_hotplug_enabled(jme))
1202 jme_stop_shutdown_timer(jme);
1203
1204 jme_stop_pcc_timer(jme);
1205 tasklet_disable(&jme->txclean_task);
1206 tasklet_disable(&jme->rxclean_task);
1207 tasklet_disable(&jme->rxempty_task);
1208
1209 if (netif_carrier_ok(netdev)) {
1210 jme_reset_ghc_speed(jme);
1211 jme_disable_rx_engine(jme);
1212 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1213 jme_reset_mac_processor(jme);
1214 jme_free_rx_resources(jme);
1215 jme_free_tx_resources(jme);
192570e0 1216
cd0ff491 1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1218 jme_polling_mode(jme);
cd0ff491
GFT
1219
1220 netif_carrier_off(netdev);
fcf45b4c
GFT
1221 }
1222
1223 jme_check_link(netdev, 0);
cd0ff491 1224 if (netif_carrier_ok(netdev)) {
fcf45b4c 1225 rc = jme_setup_rx_resources(jme);
cd0ff491 1226 if (rc) {
52a46ba8 1227 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1228 goto out_enable_tasklet;
fcf45b4c
GFT
1229 }
1230
fcf45b4c 1231 rc = jme_setup_tx_resources(jme);
cd0ff491 1232 if (rc) {
52a46ba8 1233 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1234 goto err_out_free_rx_resources;
1235 }
1236
1237 jme_enable_rx_engine(jme);
1238 jme_enable_tx_engine(jme);
1239
1240 netif_start_queue(netdev);
192570e0 1241
cd0ff491 1242 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1243 jme_interrupt_mode(jme);
192570e0 1244
79ce639c 1245 jme_start_pcc_timer(jme);
cd0ff491
GFT
1246 } else if (jme_pseudo_hotplug_enabled(jme)) {
1247 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1248 }
1249
cd0ff491 1250 goto out_enable_tasklet;
fcf45b4c
GFT
1251
1252err_out_free_rx_resources:
1253 jme_free_rx_resources(jme);
cd0ff491
GFT
1254out_enable_tasklet:
1255 tasklet_enable(&jme->txclean_task);
1256 tasklet_hi_enable(&jme->rxclean_task);
1257 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1258out:
1259 atomic_inc(&jme->link_changing);
3bf61c55 1260}
d7699f87 1261
3bf61c55
GFT
1262static void
1263jme_rx_clean_tasklet(unsigned long arg)
1264{
cd0ff491 1265 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1266 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1267
192570e0
GFT
1268 jme_process_receive(jme, jme->rx_ring_size);
1269 ++(dpi->intr_cnt);
42b1055e 1270
192570e0 1271}
fcf45b4c 1272
192570e0 1273static int
cdcdc9eb 1274jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1275{
cdcdc9eb 1276 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1277 int rest;
fcf45b4c 1278
cdcdc9eb 1279 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1280
cd0ff491 1281 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1282 atomic_dec(&jme->rx_empty);
192570e0
GFT
1283 ++(NET_STAT(jme).rx_dropped);
1284 jme_restart_rx_engine(jme);
1285 }
1286 atomic_inc(&jme->rx_empty);
1287
cd0ff491 1288 if (rest) {
cdcdc9eb 1289 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1290 jme_interrupt_mode(jme);
1291 }
1292
cdcdc9eb
GFT
1293 JME_NAPI_WEIGHT_SET(budget, rest);
1294 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1295}
1296
1297static void
1298jme_rx_empty_tasklet(unsigned long arg)
1299{
cd0ff491 1300 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1301
cd0ff491 1302 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1303 return;
1304
cd0ff491 1305 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1306 return;
1307
c97b5740 1308 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1309
fcf45b4c 1310 jme_rx_clean_tasklet(arg);
cdcdc9eb 1311
cd0ff491 1312 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1313 atomic_dec(&jme->rx_empty);
1314 ++(NET_STAT(jme).rx_dropped);
1315 jme_restart_rx_engine(jme);
1316 }
1317 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1318}
1319
b3821cc5
GFT
1320static void
1321jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322{
fa97b924 1323 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1324
1325 smp_wmb();
cd0ff491 1326 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1327 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
52a46ba8 1328 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1329 netif_wake_queue(jme->dev);
b3821cc5
GFT
1330 }
1331
1332}
1333
3bf61c55
GFT
1334static void
1335jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1336{
cd0ff491 1337 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1338 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1339 struct txdesc *txdesc = txring->desc;
3bf61c55 1340 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1341 int i, j, cnt = 0, max, err, mask;
3bf61c55 1342
52a46ba8 1343 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1344
1345 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1346 goto out;
1347
cd0ff491 1348 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1349 goto out;
1350
cd0ff491 1351 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1352 goto out;
1353
b3821cc5
GFT
1354 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1355 mask = jme->tx_ring_mask;
3bf61c55 1356
cd0ff491 1357 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1358
1359 ctxbi = txbi + i;
1360
cd0ff491 1361 if (likely(ctxbi->skb &&
b3821cc5 1362 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1363
cd0ff491 1364 tx_dbg(jme, "txclean: %d+%d@%lu\n",
52a46ba8 1365 i, ctxbi->nr_desc, jiffies);
3bf61c55 1366
cd0ff491 1367 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1368
cd0ff491 1369 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1370 ttxbi = txbi + ((i + j) & (mask));
1371 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1372
b3821cc5 1373 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1374 ttxbi->mapping,
1375 ttxbi->len,
1376 PCI_DMA_TODEVICE);
1377
3bf61c55
GFT
1378 ttxbi->mapping = 0;
1379 ttxbi->len = 0;
1380 }
1381
1382 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1383
1384 cnt += ctxbi->nr_desc;
1385
cd0ff491 1386 if (unlikely(err)) {
8c198884 1387 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1388 } else {
8c198884 1389 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1390 NET_STAT(jme).tx_bytes += ctxbi->len;
1391 }
1392
1393 ctxbi->skb = NULL;
1394 ctxbi->len = 0;
cdcdc9eb 1395 ctxbi->start_xmit = 0;
cd0ff491
GFT
1396
1397 } else {
3bf61c55
GFT
1398 break;
1399 }
1400
b3821cc5 1401 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1402
1403 ctxbi->nr_desc = 0;
d7699f87
GFT
1404 }
1405
52a46ba8 1406 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1407 atomic_set(&txring->next_to_clean, i);
79ce639c 1408 atomic_add(cnt, &txring->nr_free);
3bf61c55 1409
b3821cc5
GFT
1410 jme_wake_queue_if_stopped(jme);
1411
fcf45b4c
GFT
1412out:
1413 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1414}
1415
79ce639c 1416static void
cd0ff491 1417jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1418{
3bf61c55
GFT
1419 /*
1420 * Disable interrupt
1421 */
1422 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1423
cd0ff491 1424 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1425 /*
1426 * Link change event is critical
1427 * all other events are ignored
1428 */
1429 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1430 tasklet_schedule(&jme->linkch_task);
29bdd921 1431 goto out_reenable;
fcf45b4c 1432 }
d7699f87 1433
cd0ff491 1434 if (intrstat & INTR_TMINTR) {
47220951 1435 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1436 tasklet_schedule(&jme->pcc_task);
47220951 1437 }
79ce639c 1438
cd0ff491 1439 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1440 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1441 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1442 }
1443
cd0ff491 1444 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1445 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1446 INTR_PCCRX0 |
1447 INTR_RX0EMP)) |
1448 INTR_RX0);
1449 }
d7699f87 1450
cd0ff491
GFT
1451 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1452 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1453 atomic_inc(&jme->rx_empty);
1454
cd0ff491
GFT
1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1457 jme_polling_mode(jme);
cdcdc9eb 1458 JME_RX_SCHEDULE(jme);
192570e0
GFT
1459 }
1460 }
cd0ff491
GFT
1461 } else {
1462 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1463 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1464 tasklet_hi_schedule(&jme->rxempty_task);
1465 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1466 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1467 }
4330c2f2 1468 }
d7699f87 1469
29bdd921 1470out_reenable:
3bf61c55 1471 /*
fcf45b4c 1472 * Re-enable interrupt
3bf61c55 1473 */
fcf45b4c 1474 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1475}
1476
1477static irqreturn_t
1478jme_intr(int irq, void *dev_id)
1479{
cd0ff491
GFT
1480 struct net_device *netdev = dev_id;
1481 struct jme_adapter *jme = netdev_priv(netdev);
1482 u32 intrstat;
79ce639c
GFT
1483
1484 intrstat = jread32(jme, JME_IEVE);
1485
1486 /*
1487 * Check if it's really an interrupt for us
1488 */
9b9d55de 1489 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1490 return IRQ_NONE;
79ce639c
GFT
1491
1492 /*
1493 * Check if the device still exist
1494 */
cd0ff491
GFT
1495 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1496 return IRQ_NONE;
79ce639c
GFT
1497
1498 jme_intr_msi(jme, intrstat);
1499
cd0ff491 1500 return IRQ_HANDLED;
d7699f87
GFT
1501}
1502
79ce639c
GFT
1503static irqreturn_t
1504jme_msi(int irq, void *dev_id)
1505{
cd0ff491
GFT
1506 struct net_device *netdev = dev_id;
1507 struct jme_adapter *jme = netdev_priv(netdev);
1508 u32 intrstat;
79ce639c 1509
fa97b924 1510 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1511
1512 jme_intr_msi(jme, intrstat);
1513
cd0ff491 1514 return IRQ_HANDLED;
79ce639c
GFT
1515}
1516
79ce639c
GFT
1517static void
1518jme_reset_link(struct jme_adapter *jme)
1519{
1520 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1521}
1522
fcf45b4c
GFT
1523static void
1524jme_restart_an(struct jme_adapter *jme)
1525{
cd0ff491 1526 u32 bmcr;
fcf45b4c 1527
cd0ff491 1528 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1529 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1530 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1531 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1532 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1533}
1534
1535static int
1536jme_request_irq(struct jme_adapter *jme)
1537{
1538 int rc;
cd0ff491
GFT
1539 struct net_device *netdev = jme->dev;
1540 irq_handler_t handler = jme_intr;
1541 int irq_flags = IRQF_SHARED;
1542
1543 if (!pci_enable_msi(jme->pdev)) {
1544 set_bit(JME_FLAG_MSI, &jme->flags);
1545 handler = jme_msi;
1546 irq_flags = 0;
1547 }
1548
1549 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1550 netdev);
1551 if (rc) {
52a46ba8
JP
1552 netdev_err(netdev,
1553 "Unable to request %s interrupt (return: %d)\n",
1554 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1555 rc);
79ce639c 1556
cd0ff491
GFT
1557 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1558 pci_disable_msi(jme->pdev);
1559 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1560 }
cd0ff491 1561 } else {
79ce639c
GFT
1562 netdev->irq = jme->pdev->irq;
1563 }
1564
cd0ff491 1565 return rc;
79ce639c
GFT
1566}
1567
1568static void
1569jme_free_irq(struct jme_adapter *jme)
1570{
cd0ff491
GFT
1571 free_irq(jme->pdev->irq, jme->dev);
1572 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1573 pci_disable_msi(jme->pdev);
1574 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1575 jme->dev->irq = jme->pdev->irq;
cd0ff491 1576 }
fcf45b4c
GFT
1577}
1578
48db98f7
GFT
1579static inline void
1580jme_phy_on(struct jme_adapter *jme)
1581{
1582 u32 bmcr;
1583
1584 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1585 bmcr &= ~BMCR_PDOWN;
1586 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1587}
1588
3bf61c55
GFT
1589static int
1590jme_open(struct net_device *netdev)
d7699f87
GFT
1591{
1592 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1593 int rc;
79ce639c 1594
42b1055e 1595 jme_clear_pm(jme);
cdcdc9eb 1596 JME_NAPI_ENABLE(jme);
d7699f87 1597
fa97b924 1598 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1599 tasklet_enable(&jme->txclean_task);
1600 tasklet_hi_enable(&jme->rxclean_task);
1601 tasklet_hi_enable(&jme->rxempty_task);
1602
79ce639c 1603 rc = jme_request_irq(jme);
cd0ff491 1604 if (rc)
4330c2f2 1605 goto err_out;
79ce639c 1606
d7699f87 1607 jme_start_irq(jme);
42b1055e 1608
48db98f7
GFT
1609 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1610 jme_phy_on(jme);
42b1055e 1611 jme_set_settings(netdev, &jme->old_ecmd);
48db98f7 1612 } else {
42b1055e 1613 jme_reset_phy_processor(jme);
48db98f7 1614 }
42b1055e 1615
29bdd921 1616 jme_reset_link(jme);
d7699f87
GFT
1617
1618 return 0;
1619
d7699f87
GFT
1620err_out:
1621 netif_stop_queue(netdev);
1622 netif_carrier_off(netdev);
4330c2f2 1623 return rc;
d7699f87
GFT
1624}
1625
42b1055e
GFT
1626static void
1627jme_set_100m_half(struct jme_adapter *jme)
1628{
cd0ff491 1629 u32 bmcr, tmp;
42b1055e 1630
fba4bc0c 1631 jme_phy_on(jme);
42b1055e
GFT
1632 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1633 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1634 BMCR_SPEED1000 | BMCR_FULLDPLX);
1635 tmp |= BMCR_SPEED100;
1636
1637 if (bmcr != tmp)
1638 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1639
cd0ff491 1640 if (jme->fpgaver)
cdcdc9eb
GFT
1641 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1642 else
1643 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1644}
1645
47220951
GFT
1646#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1647static void
1648jme_wait_link(struct jme_adapter *jme)
1649{
cd0ff491 1650 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1651
1652 mdelay(1000);
1653 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1654 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1655 mdelay(10);
1656 phylink = jme_linkstat_from_phy(jme);
1657 }
1658}
1659
cd0ff491 1660static inline void
42b1055e
GFT
1661jme_phy_off(struct jme_adapter *jme)
1662{
1663 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1664}
1665
fba4bc0c
GFT
1666static void
1667jme_powersave_phy(struct jme_adapter *jme)
1668{
1669 if (jme->reg_pmcs) {
1670 jme_set_100m_half(jme);
1671
1672 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1673 jme_wait_link(jme);
1674
1675 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1676 } else {
1677 jme_phy_off(jme);
1678 }
1679}
1680
3bf61c55
GFT
1681static int
1682jme_close(struct net_device *netdev)
d7699f87
GFT
1683{
1684 struct jme_adapter *jme = netdev_priv(netdev);
1685
1686 netif_stop_queue(netdev);
1687 netif_carrier_off(netdev);
1688
1689 jme_stop_irq(jme);
79ce639c 1690 jme_free_irq(jme);
d7699f87 1691
cdcdc9eb 1692 JME_NAPI_DISABLE(jme);
192570e0 1693
fa97b924
GFT
1694 tasklet_disable(&jme->linkch_task);
1695 tasklet_disable(&jme->txclean_task);
1696 tasklet_disable(&jme->rxclean_task);
1697 tasklet_disable(&jme->rxempty_task);
8c198884 1698
cd0ff491
GFT
1699 jme_reset_ghc_speed(jme);
1700 jme_disable_rx_engine(jme);
1701 jme_disable_tx_engine(jme);
8c198884 1702 jme_reset_mac_processor(jme);
d7699f87
GFT
1703 jme_free_rx_resources(jme);
1704 jme_free_tx_resources(jme);
42b1055e 1705 jme->phylink = 0;
b3821cc5
GFT
1706 jme_phy_off(jme);
1707
1708 return 0;
1709}
1710
1711static int
1712jme_alloc_txdesc(struct jme_adapter *jme,
1713 struct sk_buff *skb)
1714{
fa97b924 1715 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1716 int idx, nr_alloc, mask = jme->tx_ring_mask;
1717
1718 idx = txring->next_to_use;
1719 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1720
cd0ff491 1721 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1722 return -1;
1723
1724 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1725
b3821cc5
GFT
1726 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1727
1728 return idx;
1729}
1730
1731static void
1732jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1733 struct txdesc *txdesc,
b3821cc5
GFT
1734 struct jme_buffer_info *txbi,
1735 struct page *page,
cd0ff491
GFT
1736 u32 page_offset,
1737 u32 len,
1738 u8 hidma)
b3821cc5
GFT
1739{
1740 dma_addr_t dmaaddr;
1741
1742 dmaaddr = pci_map_page(pdev,
1743 page,
1744 page_offset,
1745 len,
1746 PCI_DMA_TODEVICE);
1747
1748 pci_dma_sync_single_for_device(pdev,
1749 dmaaddr,
1750 len,
1751 PCI_DMA_TODEVICE);
1752
1753 txdesc->dw[0] = 0;
1754 txdesc->dw[1] = 0;
1755 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1756 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1757 txdesc->desc2.datalen = cpu_to_le16(len);
1758 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1759 txdesc->desc2.bufaddrl = cpu_to_le32(
1760 (__u64)dmaaddr & 0xFFFFFFFFUL);
1761
1762 txbi->mapping = dmaaddr;
1763 txbi->len = len;
1764}
1765
1766static void
1767jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1768{
fa97b924 1769 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1770 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1771 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1772 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1773 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1774 int mask = jme->tx_ring_mask;
1775 struct skb_frag_struct *frag;
cd0ff491 1776 u32 len;
b3821cc5 1777
cd0ff491
GFT
1778 for (i = 0 ; i < nr_frags ; ++i) {
1779 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1780 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1781 ctxbi = txbi + ((idx + i + 2) & (mask));
1782
1783 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1784 frag->page_offset, frag->size, hidma);
42b1055e 1785 }
b3821cc5 1786
cd0ff491 1787 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1788 ctxdesc = txdesc + ((idx + 1) & (mask));
1789 ctxbi = txbi + ((idx + 1) & (mask));
1790 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1791 offset_in_page(skb->data), len, hidma);
1792
1793}
1794
1795static int
1796jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1797{
cd0ff491 1798 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT
1799 skb_header_cloned(skb) &&
1800 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1801 dev_kfree_skb(skb);
1802 return -1;
1803 }
1804
1805 return 0;
1806}
1807
1808static int
94c5ea02 1809jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1810{
94c5ea02 1811 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1812 if (*mss) {
b3821cc5
GFT
1813 *flags |= TXFLAG_LSEN;
1814
cd0ff491 1815 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1816 struct iphdr *iph = ip_hdr(skb);
1817
1818 iph->check = 0;
cd0ff491 1819 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1820 iph->daddr, 0,
1821 IPPROTO_TCP,
1822 0);
cd0ff491 1823 } else {
b3821cc5
GFT
1824 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1825
cd0ff491 1826 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1827 &ip6h->daddr, 0,
1828 IPPROTO_TCP,
1829 0);
1830 }
1831
1832 return 0;
1833 }
1834
1835 return 1;
1836}
1837
1838static void
cd0ff491 1839jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1840{
cd0ff491
GFT
1841 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1842 u8 ip_proto;
b3821cc5
GFT
1843
1844 switch (skb->protocol) {
cd0ff491 1845 case htons(ETH_P_IP):
b3821cc5
GFT
1846 ip_proto = ip_hdr(skb)->protocol;
1847 break;
cd0ff491 1848 case htons(ETH_P_IPV6):
b3821cc5
GFT
1849 ip_proto = ipv6_hdr(skb)->nexthdr;
1850 break;
1851 default:
1852 ip_proto = 0;
1853 break;
1854 }
1855
cd0ff491 1856 switch (ip_proto) {
b3821cc5
GFT
1857 case IPPROTO_TCP:
1858 *flags |= TXFLAG_TCPCS;
1859 break;
1860 case IPPROTO_UDP:
1861 *flags |= TXFLAG_UDPCS;
1862 break;
1863 default:
52a46ba8 1864 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
1865 break;
1866 }
1867 }
1868}
1869
cd0ff491 1870static inline void
94c5ea02 1871jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1872{
cd0ff491 1873 if (vlan_tx_tag_present(skb)) {
b3821cc5 1874 *flags |= TXFLAG_TAGON;
94c5ea02 1875 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1876 }
b3821cc5
GFT
1877}
1878
1879static int
94c5ea02 1880jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1881{
fa97b924 1882 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1883 struct txdesc *txdesc;
b3821cc5 1884 struct jme_buffer_info *txbi;
cd0ff491 1885 u8 flags;
b3821cc5 1886
cd0ff491 1887 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1888 txbi = txring->bufinf + idx;
1889
1890 txdesc->dw[0] = 0;
1891 txdesc->dw[1] = 0;
1892 txdesc->dw[2] = 0;
1893 txdesc->dw[3] = 0;
1894 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1895 /*
1896 * Set OWN bit at final.
1897 * When kernel transmit faster than NIC.
1898 * And NIC trying to send this descriptor before we tell
1899 * it to start sending this TX queue.
1900 * Other fields are already filled correctly.
1901 */
1902 wmb();
1903 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1904 /*
1905 * Set checksum flags while not tso
1906 */
1907 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1908 jme_tx_csum(jme, skb, &flags);
b3821cc5 1909 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 1910 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
1911 txdesc->desc1.flags = flags;
1912 /*
1913 * Set tx buffer info after telling NIC to send
1914 * For better tx_clean timing
1915 */
1916 wmb();
1917 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1918 txbi->skb = skb;
1919 txbi->len = skb->len;
cd0ff491
GFT
1920 txbi->start_xmit = jiffies;
1921 if (!txbi->start_xmit)
8d27293f 1922 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1923
1924 return 0;
1925}
1926
b3821cc5
GFT
1927static void
1928jme_stop_queue_if_full(struct jme_adapter *jme)
1929{
fa97b924 1930 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
1931 struct jme_buffer_info *txbi = txring->bufinf;
1932 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1933
cd0ff491 1934 txbi += idx;
b3821cc5
GFT
1935
1936 smp_wmb();
cd0ff491 1937 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1938 netif_stop_queue(jme->dev);
52a46ba8 1939 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 1940 smp_wmb();
cd0ff491
GFT
1941 if (atomic_read(&txring->nr_free)
1942 >= (jme->tx_wake_threshold)) {
b3821cc5 1943 netif_wake_queue(jme->dev);
52a46ba8 1944 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
1945 }
1946 }
1947
cd0ff491 1948 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
1949 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1950 txbi->skb)) {
1951 netif_stop_queue(jme->dev);
52a46ba8
JP
1952 netif_info(jme, tx_queued, jme->dev,
1953 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 1954 }
b3821cc5
GFT
1955}
1956
3bf61c55
GFT
1957/*
1958 * This function is already protected by netif_tx_lock()
1959 */
cd0ff491 1960
c97b5740 1961static netdev_tx_t
3bf61c55 1962jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 1963{
cd0ff491 1964 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1965 int idx;
d7699f87 1966
cd0ff491 1967 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
1968 ++(NET_STAT(jme).tx_dropped);
1969 return NETDEV_TX_OK;
1970 }
1971
1972 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1973
cd0ff491 1974 if (unlikely(idx < 0)) {
b3821cc5 1975 netif_stop_queue(netdev);
52a46ba8
JP
1976 netif_err(jme, tx_err, jme->dev,
1977 "BUG! Tx ring full when queue awake!\n");
d7699f87 1978
cd0ff491 1979 return NETDEV_TX_BUSY;
b3821cc5
GFT
1980 }
1981
94c5ea02 1982 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 1983
4330c2f2
GFT
1984 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1985 TXCS_SELECT_QUEUE0 |
1986 TXCS_QUEUE0S |
1987 TXCS_ENABLE);
d7699f87 1988
52a46ba8
JP
1989 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1990 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
1991 jme_stop_queue_if_full(jme);
1992
cd0ff491 1993 return NETDEV_TX_OK;
d7699f87
GFT
1994}
1995
3bf61c55
GFT
1996static int
1997jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 1998{
cd0ff491 1999 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2000 struct sockaddr *addr = p;
cd0ff491 2001 u32 val;
d7699f87 2002
cd0ff491 2003 if (netif_running(netdev))
d7699f87
GFT
2004 return -EBUSY;
2005
cd0ff491 2006 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
2007 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2008
186fc259
GFT
2009 val = (addr->sa_data[3] & 0xff) << 24 |
2010 (addr->sa_data[2] & 0xff) << 16 |
2011 (addr->sa_data[1] & 0xff) << 8 |
2012 (addr->sa_data[0] & 0xff);
4330c2f2 2013 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
2014 val = (addr->sa_data[5] & 0xff) << 8 |
2015 (addr->sa_data[4] & 0xff);
4330c2f2 2016 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 2017 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2018
2019 return 0;
2020}
2021
3bf61c55
GFT
2022static void
2023jme_set_multi(struct net_device *netdev)
d7699f87 2024{
3bf61c55 2025 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2026 u32 mc_hash[2] = {};
d7699f87 2027
cd0ff491 2028 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2029
2030 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2031
cd0ff491 2032 if (netdev->flags & IFF_PROMISC) {
8c198884 2033 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2034 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2035 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2036 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2037 struct netdev_hw_addr *ha;
3bf61c55 2038 int bit_nr;
d7699f87 2039
8c198884 2040 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP
2041 netdev_for_each_mc_addr(ha, netdev) {
2042 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT
2043 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2044 }
d7699f87 2045
4330c2f2
GFT
2046 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2047 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2048 }
2049
d7699f87 2050 wmb();
8c198884
GFT
2051 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2052
cd0ff491 2053 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2054}
2055
3bf61c55 2056static int
8c198884 2057jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2058{
cd0ff491 2059 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2060
cd0ff491 2061 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2062 return 0;
2063
cd0ff491
GFT
2064 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2065 ((new_mtu) < IPV6_MIN_MTU))
2066 return -EINVAL;
79ce639c 2067
cd0ff491 2068 if (new_mtu > 4000) {
79ce639c
GFT
2069 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2070 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2071 jme_restart_rx_engine(jme);
cd0ff491 2072 } else {
79ce639c
GFT
2073 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2074 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2075 jme_restart_rx_engine(jme);
2076 }
2077
cd0ff491 2078 if (new_mtu > 1900) {
b3821cc5
GFT
2079 netdev->features &= ~(NETIF_F_HW_CSUM |
2080 NETIF_F_TSO |
2081 NETIF_F_TSO6);
cd0ff491
GFT
2082 } else {
2083 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2084 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2085 if (test_bit(JME_FLAG_TSO, &jme->flags))
b3821cc5 2086 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
2087 }
2088
cd0ff491
GFT
2089 netdev->mtu = new_mtu;
2090 jme_reset_link(jme);
79ce639c
GFT
2091
2092 return 0;
d7699f87
GFT
2093}
2094
8c198884
GFT
2095static void
2096jme_tx_timeout(struct net_device *netdev)
2097{
cd0ff491 2098 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2099
cdcdc9eb
GFT
2100 jme->phylink = 0;
2101 jme_reset_phy_processor(jme);
cd0ff491 2102 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2103 jme_set_settings(netdev, &jme->old_ecmd);
2104
8c198884 2105 /*
cdcdc9eb 2106 * Force to Reset the link again
8c198884 2107 */
29bdd921 2108 jme_reset_link(jme);
8c198884
GFT
2109}
2110
f7f428e4
GFT
2111static inline void jme_pause_rx(struct jme_adapter *jme)
2112{
2113 atomic_dec(&jme->link_changing);
2114
2115 jme_set_rx_pcc(jme, PCC_OFF);
2116 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2117 JME_NAPI_DISABLE(jme);
2118 } else {
2119 tasklet_disable(&jme->rxclean_task);
2120 tasklet_disable(&jme->rxempty_task);
2121 }
2122}
2123
2124static inline void jme_resume_rx(struct jme_adapter *jme)
2125{
2126 struct dynpcc_info *dpi = &(jme->dpi);
2127
2128 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2129 JME_NAPI_ENABLE(jme);
2130 } else {
2131 tasklet_hi_enable(&jme->rxclean_task);
2132 tasklet_hi_enable(&jme->rxempty_task);
2133 }
2134 dpi->cur = PCC_P1;
2135 dpi->attempt = PCC_P1;
2136 dpi->cnt = 0;
2137 jme_set_rx_pcc(jme, PCC_P1);
2138
2139 atomic_inc(&jme->link_changing);
2140}
2141
42b1055e
GFT
2142static void
2143jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2144{
2145 struct jme_adapter *jme = netdev_priv(netdev);
2146
f7f428e4 2147 jme_pause_rx(jme);
42b1055e 2148 jme->vlgrp = grp;
f7f428e4 2149 jme_resume_rx(jme);
42b1055e
GFT
2150}
2151
3bf61c55
GFT
2152static void
2153jme_get_drvinfo(struct net_device *netdev,
2154 struct ethtool_drvinfo *info)
d7699f87 2155{
cd0ff491 2156 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2157
cd0ff491
GFT
2158 strcpy(info->driver, DRV_NAME);
2159 strcpy(info->version, DRV_VERSION);
2160 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2161}
2162
8c198884
GFT
2163static int
2164jme_get_regs_len(struct net_device *netdev)
2165{
cd0ff491 2166 return JME_REG_LEN;
8c198884
GFT
2167}
2168
2169static void
cd0ff491 2170mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2171{
2172 int i;
2173
cd0ff491 2174 for (i = 0 ; i < len ; i += 4)
79ce639c 2175 p[i >> 2] = jread32(jme, reg + i);
186fc259 2176}
8c198884 2177
186fc259 2178static void
cd0ff491 2179mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2180{
2181 int i;
cd0ff491 2182 u16 *p16 = (u16 *)p;
186fc259 2183
cd0ff491 2184 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2185 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2186}
2187
2188static void
2189jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2190{
cd0ff491
GFT
2191 struct jme_adapter *jme = netdev_priv(netdev);
2192 u32 *p32 = (u32 *)p;
8c198884 2193
186fc259 2194 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2195
2196 regs->version = 1;
2197 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2198
2199 p32 += 0x100 >> 2;
2200 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2201
2202 p32 += 0x100 >> 2;
2203 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2204
2205 p32 += 0x100 >> 2;
2206 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2207
186fc259
GFT
2208 p32 += 0x100 >> 2;
2209 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2210}
2211
2212static int
2213jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2214{
2215 struct jme_adapter *jme = netdev_priv(netdev);
2216
8c198884
GFT
2217 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2218 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2219
cd0ff491 2220 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2221 ecmd->use_adaptive_rx_coalesce = false;
2222 ecmd->rx_coalesce_usecs = 0;
2223 ecmd->rx_max_coalesced_frames = 0;
2224 return 0;
2225 }
2226
2227 ecmd->use_adaptive_rx_coalesce = true;
2228
cd0ff491 2229 switch (jme->dpi.cur) {
8c198884
GFT
2230 case PCC_P1:
2231 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2232 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2233 break;
2234 case PCC_P2:
2235 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2236 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2237 break;
2238 case PCC_P3:
2239 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2240 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2241 break;
2242 default:
2243 break;
2244 }
2245
2246 return 0;
2247}
2248
192570e0
GFT
2249static int
2250jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2251{
2252 struct jme_adapter *jme = netdev_priv(netdev);
2253 struct dynpcc_info *dpi = &(jme->dpi);
2254
cd0ff491 2255 if (netif_running(netdev))
cdcdc9eb
GFT
2256 return -EBUSY;
2257
c97b5740
GFT
2258 if (ecmd->use_adaptive_rx_coalesce &&
2259 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2260 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2261 jme->jme_rx = netif_rx;
2262 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2263 dpi->cur = PCC_P1;
2264 dpi->attempt = PCC_P1;
2265 dpi->cnt = 0;
2266 jme_set_rx_pcc(jme, PCC_P1);
2267 jme_interrupt_mode(jme);
c97b5740
GFT
2268 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2269 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2270 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2271 jme->jme_rx = netif_receive_skb;
2272 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2273 jme_interrupt_mode(jme);
2274 }
2275
2276 return 0;
2277}
2278
8c198884
GFT
2279static void
2280jme_get_pauseparam(struct net_device *netdev,
2281 struct ethtool_pauseparam *ecmd)
2282{
2283 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2284 u32 val;
8c198884
GFT
2285
2286 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2287 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2288
cd0ff491
GFT
2289 spin_lock_bh(&jme->phy_lock);
2290 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2291 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2292
2293 ecmd->autoneg =
2294 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2295}
2296
2297static int
2298jme_set_pauseparam(struct net_device *netdev,
2299 struct ethtool_pauseparam *ecmd)
2300{
2301 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2302 u32 val;
8c198884 2303
cd0ff491 2304 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2305 (ecmd->tx_pause != 0)) {
2306
cd0ff491 2307 if (ecmd->tx_pause)
8c198884
GFT
2308 jme->reg_txpfc |= TXPFC_PF_EN;
2309 else
2310 jme->reg_txpfc &= ~TXPFC_PF_EN;
2311
2312 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2313 }
2314
cd0ff491
GFT
2315 spin_lock_bh(&jme->rxmcs_lock);
2316 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2317 (ecmd->rx_pause != 0)) {
2318
cd0ff491 2319 if (ecmd->rx_pause)
8c198884
GFT
2320 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2321 else
2322 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2323
2324 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2325 }
cd0ff491 2326 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2327
cd0ff491
GFT
2328 spin_lock_bh(&jme->phy_lock);
2329 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2330 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2331 (ecmd->autoneg != 0)) {
2332
cd0ff491 2333 if (ecmd->autoneg)
8c198884
GFT
2334 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2335 else
2336 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2337
b3821cc5
GFT
2338 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2339 MII_ADVERTISE, val);
8c198884 2340 }
cd0ff491 2341 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2342
2343 return 0;
2344}
2345
29bdd921
GFT
2346static void
2347jme_get_wol(struct net_device *netdev,
2348 struct ethtool_wolinfo *wol)
2349{
2350 struct jme_adapter *jme = netdev_priv(netdev);
2351
2352 wol->supported = WAKE_MAGIC | WAKE_PHY;
2353
2354 wol->wolopts = 0;
2355
cd0ff491 2356 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2357 wol->wolopts |= WAKE_PHY;
2358
cd0ff491 2359 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2360 wol->wolopts |= WAKE_MAGIC;
2361
2362}
2363
2364static int
2365jme_set_wol(struct net_device *netdev,
2366 struct ethtool_wolinfo *wol)
2367{
2368 struct jme_adapter *jme = netdev_priv(netdev);
2369
cd0ff491 2370 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2371 WAKE_UCAST |
2372 WAKE_MCAST |
2373 WAKE_BCAST |
2374 WAKE_ARP))
2375 return -EOPNOTSUPP;
2376
2377 jme->reg_pmcs = 0;
2378
cd0ff491 2379 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2380 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2381
cd0ff491 2382 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2383 jme->reg_pmcs |= PMCS_MFEN;
2384
cd0ff491 2385 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2386
29bdd921
GFT
2387 return 0;
2388}
b3821cc5 2389
3bf61c55
GFT
2390static int
2391jme_get_settings(struct net_device *netdev,
2392 struct ethtool_cmd *ecmd)
d7699f87
GFT
2393{
2394 struct jme_adapter *jme = netdev_priv(netdev);
2395 int rc;
8c198884 2396
cd0ff491 2397 spin_lock_bh(&jme->phy_lock);
d7699f87 2398 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2399 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2400 return rc;
2401}
2402
3bf61c55
GFT
2403static int
2404jme_set_settings(struct net_device *netdev,
2405 struct ethtool_cmd *ecmd)
d7699f87
GFT
2406{
2407 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2408 int rc, fdc = 0;
fcf45b4c 2409
cd0ff491 2410 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2411 return -EINVAL;
2412
f79361a6
GFT
2413 /*
2414 * Check If user changed duplex only while force_media.
2415 * Hardware would not generate link change interrupt.
2416 */
cd0ff491 2417 if (jme->mii_if.force_media &&
79ce639c
GFT
2418 ecmd->autoneg != AUTONEG_ENABLE &&
2419 (jme->mii_if.full_duplex != ecmd->duplex))
2420 fdc = 1;
2421
cd0ff491 2422 spin_lock_bh(&jme->phy_lock);
d7699f87 2423 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2424 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2425
cd0ff491 2426 if (!rc) {
f79361a6
GFT
2427 if (fdc)
2428 jme_reset_link(jme);
29bdd921 2429 jme->old_ecmd = *ecmd;
43e4651b
GFT
2430 set_bit(JME_FLAG_SSET, &jme->flags);
2431 }
2432
2433 return rc;
2434}
2435
2436static int
2437jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2438{
2439 int rc;
2440 struct jme_adapter *jme = netdev_priv(netdev);
2441 struct mii_ioctl_data *mii_data = if_mii(rq);
2442 unsigned int duplex_chg;
2443
2444 if (cmd == SIOCSMIIREG) {
2445 u16 val = mii_data->val_in;
2446 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2447 (val & BMCR_SPEED1000))
2448 return -EINVAL;
2449 }
2450
2451 spin_lock_bh(&jme->phy_lock);
2452 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2453 spin_unlock_bh(&jme->phy_lock);
2454
2455 if (!rc && (cmd == SIOCSMIIREG)) {
2456 if (duplex_chg)
2457 jme_reset_link(jme);
2458 jme_get_settings(netdev, &jme->old_ecmd);
2459 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2460 }
2461
d7699f87
GFT
2462 return rc;
2463}
2464
cd0ff491 2465static u32
3bf61c55
GFT
2466jme_get_link(struct net_device *netdev)
2467{
d7699f87
GFT
2468 struct jme_adapter *jme = netdev_priv(netdev);
2469 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2470}
2471
8c198884 2472static u32
cd0ff491
GFT
2473jme_get_msglevel(struct net_device *netdev)
2474{
2475 struct jme_adapter *jme = netdev_priv(netdev);
2476 return jme->msg_enable;
2477}
2478
2479static void
2480jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2481{
cd0ff491
GFT
2482 struct jme_adapter *jme = netdev_priv(netdev);
2483 jme->msg_enable = value;
2484}
8c198884 2485
cd0ff491
GFT
2486static u32
2487jme_get_rx_csum(struct net_device *netdev)
2488{
2489 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2490 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2491}
2492
2493static int
2494jme_set_rx_csum(struct net_device *netdev, u32 on)
2495{
cd0ff491 2496 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2497
cd0ff491
GFT
2498 spin_lock_bh(&jme->rxmcs_lock);
2499 if (on)
8c198884
GFT
2500 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2501 else
2502 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2503 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2504 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2505
2506 return 0;
2507}
2508
2509static int
2510jme_set_tx_csum(struct net_device *netdev, u32 on)
2511{
cd0ff491 2512 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2513
cd0ff491
GFT
2514 if (on) {
2515 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2516 if (netdev->mtu <= 1900)
b3821cc5 2517 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT
2518 } else {
2519 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2520 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2521 }
8c198884
GFT
2522
2523 return 0;
2524}
2525
b3821cc5
GFT
2526static int
2527jme_set_tso(struct net_device *netdev, u32 on)
2528{
cd0ff491 2529 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2530
cd0ff491
GFT
2531 if (on) {
2532 set_bit(JME_FLAG_TSO, &jme->flags);
2533 if (netdev->mtu <= 1900)
b3821cc5 2534 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT
2535 } else {
2536 clear_bit(JME_FLAG_TSO, &jme->flags);
2537 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT
2538 }
2539
cd0ff491 2540 return 0;
b3821cc5
GFT
2541}
2542
8c198884
GFT
2543static int
2544jme_nway_reset(struct net_device *netdev)
2545{
cd0ff491 2546 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2547 jme_restart_an(jme);
2548 return 0;
2549}
2550
cd0ff491 2551static u8
186fc259
GFT
2552jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2553{
cd0ff491 2554 u32 val;
186fc259
GFT
2555 int to;
2556
2557 val = jread32(jme, JME_SMBCSR);
2558 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2559 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2560 msleep(1);
2561 val = jread32(jme, JME_SMBCSR);
2562 }
cd0ff491 2563 if (!to) {
52a46ba8 2564 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2565 return 0xFF;
2566 }
2567
2568 jwrite32(jme, JME_SMBINTF,
2569 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2570 SMBINTF_HWRWN_READ |
2571 SMBINTF_HWCMD);
2572
2573 val = jread32(jme, JME_SMBINTF);
2574 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2575 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2576 msleep(1);
2577 val = jread32(jme, JME_SMBINTF);
2578 }
cd0ff491 2579 if (!to) {
52a46ba8 2580 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2581 return 0xFF;
2582 }
2583
2584 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2585}
2586
2587static void
cd0ff491 2588jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2589{
cd0ff491 2590 u32 val;
186fc259
GFT
2591 int to;
2592
2593 val = jread32(jme, JME_SMBCSR);
2594 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2595 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2596 msleep(1);
2597 val = jread32(jme, JME_SMBCSR);
2598 }
cd0ff491 2599 if (!to) {
52a46ba8 2600 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2601 return;
2602 }
2603
2604 jwrite32(jme, JME_SMBINTF,
2605 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2606 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2607 SMBINTF_HWRWN_WRITE |
2608 SMBINTF_HWCMD);
2609
2610 val = jread32(jme, JME_SMBINTF);
2611 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2612 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2613 msleep(1);
2614 val = jread32(jme, JME_SMBINTF);
2615 }
cd0ff491 2616 if (!to) {
52a46ba8 2617 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2618 return;
2619 }
2620
2621 mdelay(2);
2622}
2623
2624static int
2625jme_get_eeprom_len(struct net_device *netdev)
2626{
cd0ff491
GFT
2627 struct jme_adapter *jme = netdev_priv(netdev);
2628 u32 val;
186fc259 2629 val = jread32(jme, JME_SMBCSR);
cd0ff491 2630 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2631}
2632
2633static int
2634jme_get_eeprom(struct net_device *netdev,
2635 struct ethtool_eeprom *eeprom, u8 *data)
2636{
cd0ff491 2637 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2638 int i, offset = eeprom->offset, len = eeprom->len;
2639
2640 /*
8d27293f 2641 * ethtool will check the boundary for us
186fc259
GFT
2642 */
2643 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2644 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2645 data[i] = jme_smb_read(jme, i + offset);
2646
2647 return 0;
2648}
2649
2650static int
2651jme_set_eeprom(struct net_device *netdev,
2652 struct ethtool_eeprom *eeprom, u8 *data)
2653{
cd0ff491 2654 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2655 int i, offset = eeprom->offset, len = eeprom->len;
2656
2657 if (eeprom->magic != JME_EEPROM_MAGIC)
2658 return -EINVAL;
2659
2660 /*
8d27293f 2661 * ethtool will check the boundary for us
186fc259 2662 */
cd0ff491 2663 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2664 jme_smb_write(jme, i + offset, data[i]);
2665
2666 return 0;
2667}
2668
d7699f87 2669static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2670 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2671 .get_regs_len = jme_get_regs_len,
2672 .get_regs = jme_get_regs,
2673 .get_coalesce = jme_get_coalesce,
192570e0 2674 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2675 .get_pauseparam = jme_get_pauseparam,
2676 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2677 .get_wol = jme_get_wol,
2678 .set_wol = jme_set_wol,
d7699f87
GFT
2679 .get_settings = jme_get_settings,
2680 .set_settings = jme_set_settings,
2681 .get_link = jme_get_link,
cd0ff491
GFT
2682 .get_msglevel = jme_get_msglevel,
2683 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2684 .get_rx_csum = jme_get_rx_csum,
2685 .set_rx_csum = jme_set_rx_csum,
2686 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2687 .set_tso = jme_set_tso,
2688 .set_sg = ethtool_op_set_sg,
8c198884 2689 .nway_reset = jme_nway_reset,
186fc259
GFT
2690 .get_eeprom_len = jme_get_eeprom_len,
2691 .get_eeprom = jme_get_eeprom,
2692 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2693};
2694
3bf61c55
GFT
2695static int
2696jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2697{
94c5ea02 2698 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2699 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2700 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT
2701 return 1;
2702
94c5ea02 2703 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2704 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2705 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT
2706 return 1;
2707
fa97b924
GFT
2708 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2709 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT
2710 return 0;
2711
2712 return -1;
2713}
2714
cd0ff491 2715static inline void
cdcdc9eb
GFT
2716jme_phy_init(struct jme_adapter *jme)
2717{
cd0ff491 2718 u16 reg26;
cdcdc9eb
GFT
2719
2720 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2721 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2722}
2723
cd0ff491 2724static inline void
cdcdc9eb 2725jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2726{
cd0ff491 2727 u32 chipmode;
cdcdc9eb
GFT
2728
2729 chipmode = jread32(jme, JME_CHIPMODE);
2730
2731 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2732 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT
2733}
2734
94c5ea02
GFT
2735static const struct net_device_ops jme_netdev_ops = {
2736 .ndo_open = jme_open,
2737 .ndo_stop = jme_close,
2738 .ndo_validate_addr = eth_validate_addr,
43e4651b 2739 .ndo_do_ioctl = jme_ioctl,
94c5ea02
GFT
2740 .ndo_start_xmit = jme_start_xmit,
2741 .ndo_set_mac_address = jme_set_macaddr,
2742 .ndo_set_multicast_list = jme_set_multi,
2743 .ndo_change_mtu = jme_change_mtu,
2744 .ndo_tx_timeout = jme_tx_timeout,
2745 .ndo_vlan_rx_register = jme_vlan_rx_register,
2746};
2747
3bf61c55
GFT
2748static int __devinit
2749jme_init_one(struct pci_dev *pdev,
2750 const struct pci_device_id *ent)
2751{
cdcdc9eb 2752 int rc = 0, using_dac, i;
d7699f87
GFT
2753 struct net_device *netdev;
2754 struct jme_adapter *jme;
cd0ff491
GFT
2755 u16 bmcr, bmsr;
2756 u32 apmc;
d7699f87
GFT
2757
2758 /*
2759 * set up PCI device basics
2760 */
4330c2f2 2761 rc = pci_enable_device(pdev);
cd0ff491 2762 if (rc) {
52a46ba8 2763 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
2764 goto err_out;
2765 }
d7699f87 2766
3bf61c55 2767 using_dac = jme_pci_dma64(pdev);
cd0ff491 2768 if (using_dac < 0) {
52a46ba8 2769 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
2770 rc = -EIO;
2771 goto err_out_disable_pdev;
2772 }
2773
cd0ff491 2774 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
52a46ba8 2775 pr_err("No PCI resource region found\n");
4330c2f2
GFT
2776 rc = -ENOMEM;
2777 goto err_out_disable_pdev;
2778 }
d7699f87 2779
4330c2f2 2780 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2781 if (rc) {
52a46ba8 2782 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
2783 goto err_out_disable_pdev;
2784 }
d7699f87
GFT
2785
2786 pci_set_master(pdev);
2787
2788 /*
2789 * alloc and init net device
2790 */
3bf61c55 2791 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2792 if (!netdev) {
52a46ba8 2793 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
2794 rc = -ENOMEM;
2795 goto err_out_release_regions;
d7699f87 2796 }
94c5ea02 2797 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2798 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2799 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2800 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2801 NETIF_F_SG |
2802 NETIF_F_TSO |
2803 NETIF_F_TSO6 |
42b1055e
GFT
2804 NETIF_F_HW_VLAN_TX |
2805 NETIF_F_HW_VLAN_RX;
cd0ff491 2806 if (using_dac)
8c198884 2807 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2808
2809 SET_NETDEV_DEV(netdev, &pdev->dev);
2810 pci_set_drvdata(pdev, netdev);
2811
2812 /*
2813 * init adapter info
2814 */
2815 jme = netdev_priv(netdev);
2816 jme->pdev = pdev;
2817 jme->dev = netdev;
cdcdc9eb
GFT
2818 jme->jme_rx = netif_rx;
2819 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2820 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2821 jme->phylink = 0;
b3821cc5
GFT
2822 jme->tx_ring_size = 1 << 10;
2823 jme->tx_ring_mask = jme->tx_ring_size - 1;
2824 jme->tx_wake_threshold = 1 << 9;
2825 jme->rx_ring_size = 1 << 9;
2826 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2827 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2828 jme->regs = ioremap(pci_resource_start(pdev, 0),
2829 pci_resource_len(pdev, 0));
4330c2f2 2830 if (!(jme->regs)) {
52a46ba8 2831 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
2832 rc = -ENOMEM;
2833 goto err_out_free_netdev;
2834 }
4330c2f2 2835
cd0ff491
GFT
2836 if (no_pseudohp) {
2837 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2838 jwrite32(jme, JME_APMC, apmc);
2839 } else if (force_pseudohp) {
2840 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2841 jwrite32(jme, JME_APMC, apmc);
2842 }
2843
cdcdc9eb 2844 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2845
d7699f87 2846 spin_lock_init(&jme->phy_lock);
fcf45b4c 2847 spin_lock_init(&jme->macaddr_lock);
8c198884 2848 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2849
fcf45b4c
GFT
2850 atomic_set(&jme->link_changing, 1);
2851 atomic_set(&jme->rx_cleaning, 1);
2852 atomic_set(&jme->tx_cleaning, 1);
192570e0 2853 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2854
79ce639c 2855 tasklet_init(&jme->pcc_task,
c97b5740 2856 jme_pcc_tasklet,
79ce639c 2857 (unsigned long) jme);
4330c2f2 2858 tasklet_init(&jme->linkch_task,
c97b5740 2859 jme_link_change_tasklet,
4330c2f2
GFT
2860 (unsigned long) jme);
2861 tasklet_init(&jme->txclean_task,
c97b5740 2862 jme_tx_clean_tasklet,
4330c2f2
GFT
2863 (unsigned long) jme);
2864 tasklet_init(&jme->rxclean_task,
c97b5740 2865 jme_rx_clean_tasklet,
4330c2f2 2866 (unsigned long) jme);
fcf45b4c 2867 tasklet_init(&jme->rxempty_task,
c97b5740 2868 jme_rx_empty_tasklet,
fcf45b4c 2869 (unsigned long) jme);
fa97b924 2870 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
2871 tasklet_disable_nosync(&jme->txclean_task);
2872 tasklet_disable_nosync(&jme->rxclean_task);
2873 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
2874 jme->dpi.cur = PCC_P1;
2875
cd0ff491 2876 jme->reg_ghc = 0;
79ce639c 2877 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2878 jme->reg_rxmcs = RXMCS_DEFAULT;
2879 jme->reg_txpfc = 0;
47220951 2880 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
2881 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2882 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2883
fcf45b4c
GFT
2884 /*
2885 * Get Max Read Req Size from PCI Config Space
2886 */
cd0ff491
GFT
2887 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2888 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2889 switch (jme->mrrs) {
2890 case MRRS_128B:
2891 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2892 break;
2893 case MRRS_256B:
2894 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2895 break;
2896 default:
2897 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2898 break;
06527f9b 2899 }
fcf45b4c 2900
d7699f87 2901 /*
cdcdc9eb 2902 * Must check before reset_mac_processor
d7699f87 2903 */
cdcdc9eb
GFT
2904 jme_check_hw_ver(jme);
2905 jme->mii_if.dev = netdev;
cd0ff491 2906 if (jme->fpgaver) {
cdcdc9eb 2907 jme->mii_if.phy_id = 0;
cd0ff491 2908 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
2909 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2910 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 2911 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
2912 jme->mii_if.phy_id = i;
2913 break;
2914 }
2915 }
2916
cd0ff491 2917 if (!jme->mii_if.phy_id) {
cdcdc9eb 2918 rc = -EIO;
52a46ba8
JP
2919 pr_err("Can not find phy_id\n");
2920 goto err_out_unmap;
cdcdc9eb
GFT
2921 }
2922
2923 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 2924 } else {
cdcdc9eb
GFT
2925 jme->mii_if.phy_id = 1;
2926 }
cd0ff491 2927 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
2928 jme->mii_if.supports_gmii = true;
2929 else
2930 jme->mii_if.supports_gmii = false;
43e4651b
GFT
2931 jme->mii_if.phy_id_mask = 0x1F;
2932 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT
2933 jme->mii_if.mdio_read = jme_mdio_read;
2934 jme->mii_if.mdio_write = jme_mdio_write;
2935
d7699f87 2936 jme_clear_pm(jme);
e882564f 2937 jme_set_phyfifoa(jme);
cd0ff491
GFT
2938 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2939 if (!jme->fpgaver)
cdcdc9eb 2940 jme_phy_init(jme);
42b1055e 2941 jme_phy_off(jme);
cdcdc9eb
GFT
2942
2943 /*
2944 * Reset MAC processor and reload EEPROM for MAC Address
2945 */
d7699f87 2946 jme_reset_mac_processor(jme);
4330c2f2 2947 rc = jme_reload_eeprom(jme);
cd0ff491 2948 if (rc) {
52a46ba8 2949 pr_err("Reload eeprom for reading MAC Address error\n");
fa97b924 2950 goto err_out_unmap;
4330c2f2 2951 }
d7699f87
GFT
2952 jme_load_macaddr(netdev);
2953
d7699f87
GFT
2954 /*
2955 * Tell stack that we are not ready to work until open()
2956 */
2957 netif_carrier_off(netdev);
2958 netif_stop_queue(netdev);
2959
2960 /*
2961 * Register netdev
2962 */
4330c2f2 2963 rc = register_netdev(netdev);
cd0ff491 2964 if (rc) {
52a46ba8 2965 pr_err("Cannot register net device\n");
fa97b924 2966 goto err_out_unmap;
4330c2f2 2967 }
d7699f87 2968
c97b5740
GFT
2969 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2970 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2971 "JMC250 Gigabit Ethernet" :
2972 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2973 "JMC260 Fast Ethernet" : "Unknown",
2974 (jme->fpgaver != 0) ? " (FPGA)" : "",
2975 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2976 jme->rev, netdev->dev_addr);
d7699f87
GFT
2977
2978 return 0;
2979
2980err_out_unmap:
2981 iounmap(jme->regs);
2982err_out_free_netdev:
2983 pci_set_drvdata(pdev, NULL);
2984 free_netdev(netdev);
4330c2f2
GFT
2985err_out_release_regions:
2986 pci_release_regions(pdev);
d7699f87 2987err_out_disable_pdev:
cd0ff491 2988 pci_disable_device(pdev);
d7699f87 2989err_out:
4330c2f2 2990 return rc;
d7699f87
GFT
2991}
2992
3bf61c55
GFT
2993static void __devexit
2994jme_remove_one(struct pci_dev *pdev)
2995{
d7699f87
GFT
2996 struct net_device *netdev = pci_get_drvdata(pdev);
2997 struct jme_adapter *jme = netdev_priv(netdev);
2998
2999 unregister_netdev(netdev);
3000 iounmap(jme->regs);
3001 pci_set_drvdata(pdev, NULL);
3002 free_netdev(netdev);
3003 pci_release_regions(pdev);
3004 pci_disable_device(pdev);
3005
3006}
3007
fba4bc0c
GFT
3008static void
3009jme_shutdown(struct pci_dev *pdev)
3010{
3011 struct net_device *netdev = pci_get_drvdata(pdev);
3012 struct jme_adapter *jme = netdev_priv(netdev);
3013
3014 jme_powersave_phy(jme);
3015 pci_pme_active(pdev, true);
3016}
3017
9b9d55de 3018#ifdef CONFIG_PM
29bdd921
GFT
3019static int
3020jme_suspend(struct pci_dev *pdev, pm_message_t state)
3021{
3022 struct net_device *netdev = pci_get_drvdata(pdev);
3023 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
3024
3025 atomic_dec(&jme->link_changing);
3026
3027 netif_device_detach(netdev);
3028 netif_stop_queue(netdev);
3029 jme_stop_irq(jme);
29bdd921 3030
cd0ff491
GFT
3031 tasklet_disable(&jme->txclean_task);
3032 tasklet_disable(&jme->rxclean_task);
3033 tasklet_disable(&jme->rxempty_task);
3034
cd0ff491
GFT
3035 if (netif_carrier_ok(netdev)) {
3036 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
3037 jme_polling_mode(jme);
3038
29bdd921 3039 jme_stop_pcc_timer(jme);
cd0ff491
GFT
3040 jme_reset_ghc_speed(jme);
3041 jme_disable_rx_engine(jme);
3042 jme_disable_tx_engine(jme);
29bdd921
GFT
3043 jme_reset_mac_processor(jme);
3044 jme_free_rx_resources(jme);
3045 jme_free_tx_resources(jme);
3046 netif_carrier_off(netdev);
3047 jme->phylink = 0;
3048 }
3049
cd0ff491
GFT
3050 tasklet_enable(&jme->txclean_task);
3051 tasklet_hi_enable(&jme->rxclean_task);
3052 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
3053
3054 pci_save_state(pdev);
fba4bc0c
GFT
3055 jme_powersave_phy(jme);
3056 pci_enable_wake(jme->pdev, PCI_D3hot, true);
3057 pci_set_power_state(pdev, PCI_D3hot);
29bdd921
GFT
3058
3059 return 0;
3060}
3061
3062static int
3063jme_resume(struct pci_dev *pdev)
3064{
3065 struct net_device *netdev = pci_get_drvdata(pdev);
3066 struct jme_adapter *jme = netdev_priv(netdev);
3067
3068 jme_clear_pm(jme);
3069 pci_restore_state(pdev);
3070
48db98f7
GFT
3071 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3072 jme_phy_on(jme);
29bdd921 3073 jme_set_settings(netdev, &jme->old_ecmd);
48db98f7 3074 } else {
29bdd921 3075 jme_reset_phy_processor(jme);
48db98f7 3076 }
29bdd921 3077
29bdd921
GFT
3078 jme_start_irq(jme);
3079 netif_device_attach(netdev);
3080
3081 atomic_inc(&jme->link_changing);
3082
3083 jme_reset_link(jme);
3084
3085 return 0;
3086}
9b9d55de 3087#endif
29bdd921 3088
c97b5740 3089static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT
3090 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3091 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3092 { }
3093};
3094
3095static struct pci_driver jme_driver = {
cd0ff491
GFT
3096 .name = DRV_NAME,
3097 .id_table = jme_pci_tbl,
3098 .probe = jme_init_one,
3099 .remove = __devexit_p(jme_remove_one),
d7699f87 3100#ifdef CONFIG_PM
cd0ff491
GFT
3101 .suspend = jme_suspend,
3102 .resume = jme_resume,
d7699f87 3103#endif /* CONFIG_PM */
fba4bc0c 3104 .shutdown = jme_shutdown,
d7699f87
GFT
3105};
3106
3bf61c55
GFT
3107static int __init
3108jme_init_module(void)
d7699f87 3109{
52a46ba8 3110 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3111 return pci_register_driver(&jme_driver);
3112}
3113
3bf61c55
GFT
3114static void __exit
3115jme_cleanup_module(void)
d7699f87
GFT
3116{
3117 pci_unregister_driver(&jme_driver);
3118}
3119
3120module_init(jme_init_module);
3121module_exit(jme_cleanup_module);
3122
3bf61c55 3123MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3124MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3125MODULE_LICENSE("GPL");
3126MODULE_VERSION(DRV_VERSION);
3127MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3128