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Import jme 1.0.6 source
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT		 7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
d7699f87
GFT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/mii.h>
31#include <linux/crc32.h>
4330c2f2 32#include <linux/delay.h>
29bdd921 33#include <linux/spinlock.h>
8c198884
GFT		 34#include <linux/in.h>
35#include <linux/ip.h>
79ce639c
GFT		 36#include <linux/ipv6.h>
37#include <linux/tcp.h>
38#include <linux/udp.h>
42b1055e 39#include <linux/if_vlan.h>
94c5ea02 40#include <net/ip6_checksum.h>
d7699f87
GFT		 41#include "jme.h"
42
cd0ff491
GFT		 43static int force_pseudohp = -1;
44static int no_pseudohp = -1;
45static int no_extplug = -1;
46module_param(force_pseudohp, int, 0);
47MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49module_param(no_pseudohp, int, 0);
50MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51module_param(no_extplug, int, 0);
52MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 54
3bf61c55
GFT		 55static int
56jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 57{
58 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 60
186fc259 61read_again:
cd0ff491 62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
d7699f87
GFT		 65
66 wmb();
cd0ff491 67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 68 udelay(20);
b3821cc5
GFT		 69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
3bf61c55 71 break;
cd0ff491 72 }
d7699f87 73
cd0ff491
GFT		 74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 76 return 0;
cd0ff491 77 }
d7699f87 78
cd0ff491 79 if (again--)
186fc259
GFT		 80 goto read_again;
81
cd0ff491 82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 83}
84
3bf61c55
GFT		 85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
d7699f87
GFT		 88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
3bf61c55
GFT		 92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 95
96 wmb();
cdcdc9eb
GFT		 97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
8d27293f 99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 100 break;
101 }
d7699f87 102
3bf61c55 103 if (i == 0)
cd0ff491 104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
d7699f87 105
3bf61c55 106 return;
d7699f87
GFT		 107}
108
cd0ff491 109static inline void
3bf61c55 110jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 111{
cd0ff491 112 u32 val;
3bf61c55
GFT		 113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
8c198884
GFT		 116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 118
cd0ff491 119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 124
fcf45b4c
GFT		 125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
3bf61c55
GFT		 133 return;
134}
135
b3821cc5
GFT		 136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 138 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
cd0ff491 163static inline void
3bf61c55
GFT		 164jme_reset_mac_processor(struct jme_adapter *jme)
165{
cd0ff491
GFT		 166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
b3821cc5
GFT		 169 int i;
170
3bf61c55 171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 172 udelay(2);
3bf61c55 173 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT		 174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
4330c2f2
GFT		 184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 187 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 188 if (jme->fpgaver)
cdcdc9eb
GFT		 189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
9b9d55de 193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT		 194}
195
cd0ff491
GFT		 196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
3bf61c55 204jme_clear_pm(struct jme_adapter *jme)
d7699f87 205{
29bdd921 206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 207 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 208 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT		 209}
210
3bf61c55
GFT		 211static int
212jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 213{
cd0ff491 214 u32 val;
d7699f87
GFT		 215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
cd0ff491 219 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
cd0ff491 226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
cd0ff491
GFT		 232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
d7699f87
GFT		 234 return -EIO;
235 }
236 }
3bf61c55 237
d7699f87
GFT		 238 return 0;
239}
240
3bf61c55
GFT		 241static void
242jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
cd0ff491 246 u32 val;
d7699f87 247
cd0ff491 248 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 249 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 254 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 259}
260
cd0ff491 261static inline void
3bf61c55
GFT		 262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
cd0ff491 264 switch (p) {
192570e0
GFT		 265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
3bf61c55
GFT		 270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
192570e0 288 wmb();
3bf61c55 289
cd0ff491 290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 292}
293
fcf45b4c 294static void
3bf61c55 295jme_start_irq(struct jme_adapter *jme)
d7699f87 296{
3bf61c55
GFT		 297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 307 PCCTXQ0_EN
308 );
309
d7699f87
GFT		 310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
cd0ff491 316static inline void
3bf61c55 317jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 318{
319 /*
320 * Disable Interrupts
321 */
cd0ff491 322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 323}
324
cd0ff491 325static u32
cdcdc9eb
GFT		 326jme_linkstat_from_phy(struct jme_adapter *jme)
327{
cd0ff491 328 u32 phylink, bmsr;
cdcdc9eb
GFT		 329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 332 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336}
337
cd0ff491 338static inline void
e882564f 339jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT		 340{
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342}
343
344static inline void
e882564f 345jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT		 346{
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348}
349
fcf45b4c
GFT		 350static int
351jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 352{
353 struct jme_adapter *jme = netdev_priv(netdev);
9b9d55de 354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 355 char linkmsg[64];
fcf45b4c 356 int rc = 0;
d7699f87 357
b3821cc5 358 linkmsg[0] = '\0';
cdcdc9eb 359
cd0ff491 360 if (jme->fpgaver)
cdcdc9eb
GFT		 361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 364
cd0ff491
GFT		 365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
79ce639c 386
b3821cc5 387 strcat(linkmsg, "Forced: ");
cd0ff491 388 } else {
8c198884
GFT		 389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
cd0ff491 392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 393 --cnt) {
394
395 udelay(1);
8c198884 396
cd0ff491 397 if (jme->fpgaver)
cdcdc9eb
GFT		 398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
8c198884 401 }
cd0ff491
GFT		 402 if (!cnt)
403 jeprintk(jme->pdev,
8c198884 404 "Waiting speed resolve timeout.\n");
79ce639c 405
b3821cc5 406 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 407 }
408
cd0ff491 409 if (jme->phylink == phylink) {
fcf45b4c
GFT		 410 rc = 1;
411 goto out;
412 }
cd0ff491 413 if (testonly)
fcf45b4c
GFT		 414 goto out;
415
416 jme->phylink = phylink;
417
94c5ea02
GFT		 418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT		 421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
94c5ea02
GFT		 423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 425 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 426 break;
427 case PHY_LINK_SPEED_100M:
94c5ea02
GFT		 428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 430 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 431 break;
432 case PHY_LINK_SPEED_1000M:
94c5ea02
GFT		 433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 435 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 436 break;
437 default:
438 break;
d7699f87 439 }
d7699f87 440
cd0ff491 441 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
9b9d55de 443 ghc |= GHC_DPX;
cd0ff491 444 } else {
d7699f87 445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 446 TXMCS_BACKOFF |
447 TXMCS_CARRIERSENSE |
448 TXMCS_COLLISION);
8c198884
GFT		 449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
451 TXTRHD_TXREN |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 }
9b9d55de
GFT		 454
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
463 break;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
467 break;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
470 break;
471 default:
472 break;
473 }
474 }
d7699f87 475
94c5ea02 476 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 477 jwrite32(jme, JME_GHC, ghc);
94c5ea02 478 jme->reg_ghc = ghc;
fcf45b4c 479
94c5ea02
GFT		 480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 "Full-Duplex, " :
482 "Half-Duplex, ");
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 "MDI-X" :
485 "MDI");
c97b5740 486 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
cd0ff491
GFT		 487 netif_carrier_on(netdev);
488 } else {
489 if (testonly)
fcf45b4c
GFT		 490 goto out;
491
c97b5740 492 netif_info(jme, link, jme->dev, "Link is down.\n");
fcf45b4c 493 jme->phylink = 0;
cd0ff491 494 netif_carrier_off(netdev);
d7699f87 495 }
fcf45b4c
GFT		 496
497out:
498 return rc;
d7699f87
GFT		 499}
500
3bf61c55
GFT		 501static int
502jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 503{
d7699f87
GFT		 504 struct jme_ring *txring = &(jme->txring[0]);
505
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
508 &(txring->dmaalloc),
509 GFP_ATOMIC);
fcf45b4c 510
fa97b924
GFT		 511 if (!txring->alloc)
512 goto err_set_null;
d7699f87
GFT		 513
514 /*
515 * 16 Bytes align
516 */
cd0ff491 517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 518 RING_DESC_ALIGN);
4330c2f2 519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 520 txring->next_to_use = 0;
cdcdc9eb 521 atomic_set(&txring->next_to_clean, 0);
b3821cc5 522 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 523
fa97b924
GFT		 524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
528
d7699f87 529 /*
b3821cc5 530 * Initialize Transmit Descriptors
d7699f87 531 */
b3821cc5 532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 533 memset(txring->bufinf, 0,
b3821cc5 534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 535
536 return 0;
fa97b924
GFT		 537
538err_free_txring:
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
541 txring->alloc,
542 txring->dmaalloc);
543
544err_set_null:
545 txring->desc = NULL;
546 txring->dmaalloc = 0;
547 txring->dma = 0;
548 txring->bufinf = NULL;
549
550 return -ENOMEM;
d7699f87
GFT		 551}
552
3bf61c55
GFT		 553static void
554jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 555{
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 558 struct jme_buffer_info *txbi;
d7699f87 559
cd0ff491 560 if (txring->alloc) {
fa97b924
GFT		 561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
564 if (txbi->skb) {
565 dev_kfree_skb(txbi->skb);
566 txbi->skb = NULL;
567 }
568 txbi->mapping = 0;
569 txbi->len = 0;
570 txbi->nr_desc = 0;
571 txbi->start_xmit = 0;
d7699f87 572 }
fa97b924 573 kfree(txring->bufinf);
d7699f87
GFT		 574 }
575
576 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 578 txring->alloc,
579 txring->dmaalloc);
3bf61c55
GFT		 580
581 txring->alloc = NULL;
582 txring->desc = NULL;
583 txring->dmaalloc = 0;
584 txring->dma = 0;
fa97b924 585 txring->bufinf = NULL;
d7699f87 586 }
3bf61c55 587 txring->next_to_use = 0;
cdcdc9eb 588 atomic_set(&txring->next_to_clean, 0);
79ce639c 589 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 590}
591
cd0ff491 592static inline void
3bf61c55 593jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 594{
595 /*
596 * Select Queue 0
597 */
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 599 wmb();
d7699f87
GFT		 600
601 /*
602 * Setup TX Queue 0 DMA Bass Address
603 */
fcf45b4c 604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 607
608 /*
609 * Setup TX Descptor Count
610 */
b3821cc5 611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 612
613 /*
614 * Enable TX Engine
615 */
616 wmb();
4330c2f2
GFT		 617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
618 TXCS_SELECT_QUEUE0 |
619 TXCS_ENABLE);
d7699f87
GFT		 620
621}
622
cd0ff491 623static inline void
29bdd921
GFT		 624jme_restart_tx_engine(struct jme_adapter *jme)
625{
626 /*
627 * Restart TX Engine
628 */
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
630 TXCS_SELECT_QUEUE0 |
631 TXCS_ENABLE);
632}
633
cd0ff491 634static inline void
3bf61c55 635jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 636{
637 int i;
cd0ff491 638 u32 val;
d7699f87
GFT		 639
640 /*
641 * Disable TX Engine
642 */
fcf45b4c 643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 644 wmb();
d7699f87
GFT		 645
646 val = jread32(jme, JME_TXCS);
cd0ff491 647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 648 mdelay(1);
d7699f87 649 val = jread32(jme, JME_TXCS);
cd0ff491 650 rmb();
d7699f87
GFT		 651 }
652
cd0ff491
GFT		 653 if (!i)
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
d7699f87
GFT		 655}
656
3bf61c55
GFT		 657static void
658jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 659{
fa97b924 660 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 661 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 662 struct jme_buffer_info *rxbi = rxring->bufinf;
663 rxdesc += i;
664 rxbi += i;
665
666 rxdesc->dw[0] = 0;
667 rxdesc->dw[1] = 0;
3bf61c55 668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 672 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 673 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 674 wmb();
3bf61c55 675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 676}
677
3bf61c55
GFT		 678static int
679jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 680{
681 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 683 struct sk_buff *skb;
4330c2f2 684
79ce639c
GFT		 685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 687 if (unlikely(!skb))
4330c2f2 688 return -ENOMEM;
3bf61c55 689
4330c2f2 690 rxbi->skb = skb;
3bf61c55 691 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 692 rxbi->mapping = pci_map_page(jme->pdev,
693 virt_to_page(skb->data),
694 offset_in_page(skb->data),
695 rxbi->len,
696 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 697
698 return 0;
699}
700
3bf61c55
GFT		 701static void
702jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 703{
704 struct jme_ring *rxring = &(jme->rxring[0]);
705 struct jme_buffer_info *rxbi = rxring->bufinf;
706 rxbi += i;
707
cd0ff491 708 if (rxbi->skb) {
b3821cc5 709 pci_unmap_page(jme->pdev,
4330c2f2 710 rxbi->mapping,
3bf61c55 711 rxbi->len,
4330c2f2
GFT		 712 PCI_DMA_FROMDEVICE);
713 dev_kfree_skb(rxbi->skb);
714 rxbi->skb = NULL;
715 rxbi->mapping = 0;
3bf61c55 716 rxbi->len = 0;
4330c2f2
GFT		 717 }
718}
719
3bf61c55
GFT		 720static void
721jme_free_rx_resources(struct jme_adapter *jme)
722{
723 int i;
724 struct jme_ring *rxring = &(jme->rxring[0]);
725
cd0ff491 726 if (rxring->alloc) {
fa97b924
GFT		 727 if (rxring->bufinf) {
728 for (i = 0 ; i < jme->rx_ring_size ; ++i)
729 jme_free_rx_buf(jme, i);
730 kfree(rxring->bufinf);
731 }
3bf61c55
GFT		 732
733 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 734 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 735 rxring->alloc,
736 rxring->dmaalloc);
737 rxring->alloc = NULL;
738 rxring->desc = NULL;
739 rxring->dmaalloc = 0;
740 rxring->dma = 0;
fa97b924 741 rxring->bufinf = NULL;
3bf61c55
GFT		 742 }
743 rxring->next_to_use = 0;
cdcdc9eb 744 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 745}
746
747static int
748jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 749{
750 int i;
751 struct jme_ring *rxring = &(jme->rxring[0]);
752
753 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 754 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
755 &(rxring->dmaalloc),
756 GFP_ATOMIC);
fa97b924
GFT		 757 if (!rxring->alloc)
758 goto err_set_null;
d7699f87
GFT		 759
760 /*
761 * 16 Bytes align
762 */
cd0ff491 763 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 764 RING_DESC_ALIGN);
4330c2f2 765 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 766 rxring->next_to_use = 0;
cdcdc9eb 767 atomic_set(&rxring->next_to_clean, 0);
d7699f87 768
fa97b924
GFT		 769 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
770 jme->rx_ring_size, GFP_ATOMIC);
771 if (unlikely(!(rxring->bufinf)))
772 goto err_free_rxring;
773
d7699f87
GFT		 774 /*
775 * Initiallize Receive Descriptors
776 */
fa97b924
GFT		 777 memset(rxring->bufinf, 0,
778 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 779 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
780 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 781 jme_free_rx_resources(jme);
782 return -ENOMEM;
783 }
d7699f87
GFT		 784
785 jme_set_clean_rxdesc(jme, i);
786 }
787
d7699f87 788 return 0;
fa97b924
GFT		 789
790err_free_rxring:
791 dma_free_coherent(&(jme->pdev->dev),
792 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
793 rxring->alloc,
794 rxring->dmaalloc);
795err_set_null:
796 rxring->desc = NULL;
797 rxring->dmaalloc = 0;
798 rxring->dma = 0;
799 rxring->bufinf = NULL;
800
801 return -ENOMEM;
d7699f87
GFT		 802}
803
cd0ff491 804static inline void
3bf61c55 805jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 806{
cd0ff491
GFT		 807 /*
808 * Select Queue 0
809 */
810 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
811 RXCS_QUEUESEL_Q0);
812 wmb();
813
d7699f87
GFT		 814 /*
815 * Setup RX DMA Bass Address
816 */
fa97b924 817 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 818 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 819 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 820
821 /*
b3821cc5 822 * Setup RX Descriptor Count
d7699f87 823 */
b3821cc5 824 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 825
3bf61c55 826 /*
d7699f87
GFT		 827 * Setup Unicast Filter
828 */
829 jme_set_multi(jme->dev);
830
831 /*
832 * Enable RX Engine
833 */
834 wmb();
79ce639c 835 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 836 RXCS_QUEUESEL_Q0 |
837 RXCS_ENABLE |
838 RXCS_QST);
d7699f87
GFT		 839}
840
cd0ff491 841static inline void
3bf61c55 842jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 843{
844 /*
3bf61c55 845 * Start RX Engine
4330c2f2 846 */
79ce639c 847 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 848 RXCS_QUEUESEL_Q0 |
849 RXCS_ENABLE |
850 RXCS_QST);
851}
852
cd0ff491 853static inline void
3bf61c55 854jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 855{
856 int i;
cd0ff491 857 u32 val;
d7699f87
GFT		 858
859 /*
860 * Disable RX Engine
861 */
29bdd921 862 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 863 wmb();
d7699f87
GFT		 864
865 val = jread32(jme, JME_RXCS);
cd0ff491 866 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 867 mdelay(1);
d7699f87 868 val = jread32(jme, JME_RXCS);
cd0ff491 869 rmb();
d7699f87
GFT		 870 }
871
cd0ff491
GFT		 872 if (!i)
873 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
d7699f87
GFT		 874
875}
876
192570e0 877static int
cd0ff491 878jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 879{
cd0ff491 880 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 881 return false;
882
fa97b924
GFT		 883 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
884 == RXWBFLAG_TCPON)) {
885 if (flags & RXWBFLAG_IPV4)
c97b5740 886 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 887 return false;
192570e0
GFT		 888 }
889
fa97b924
GFT		 890 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
891 == RXWBFLAG_UDPON)) {
892 if (flags & RXWBFLAG_IPV4)
c97b5740 893 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
fa97b924 894 return false;
192570e0
GFT		 895 }
896
fa97b924
GFT		 897 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
898 == RXWBFLAG_IPV4)) {
c97b5740 899 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
fa97b924 900 return false;
192570e0
GFT		 901 }
902
903 return true;
904}
905
3bf61c55 906static void
42b1055e 907jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 908{
d7699f87 909 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 910 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 911 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 912 struct sk_buff *skb;
3bf61c55 913 int framesize;
d7699f87 914
3bf61c55
GFT		 915 rxdesc += idx;
916 rxbi += idx;
d7699f87 917
3bf61c55
GFT		 918 skb = rxbi->skb;
919 pci_dma_sync_single_for_cpu(jme->pdev,
920 rxbi->mapping,
921 rxbi->len,
922 PCI_DMA_FROMDEVICE);
923
cd0ff491 924 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 925 pci_dma_sync_single_for_device(jme->pdev,
926 rxbi->mapping,
927 rxbi->len,
928 PCI_DMA_FROMDEVICE);
929
930 ++(NET_STAT(jme).rx_dropped);
cd0ff491 931 } else {
3bf61c55
GFT		 932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
933 - RX_PREPAD_SIZE;
934
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
938
94c5ea02 939 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 940 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921
GFT		 941 else
942 skb->ip_summed = CHECKSUM_NONE;
8c198884 943
94c5ea02 944 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
c97b5740 945 spin_lock(&jme->vlgrp_lock);
cd0ff491 946 if (jme->vlgrp) {
cdcdc9eb 947 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 948 le16_to_cpu(rxdesc->descwb.vlan));
c97b5740 949 spin_unlock(&jme->vlgrp_lock);
b3821cc5 950 NET_STAT(jme).rx_bytes += 4;
c97b5740
GFT		 951 } else {
952 spin_unlock(&jme->vlgrp_lock);
953 dev_kfree_skb(skb);
b3821cc5 954 }
cd0ff491 955 } else {
cdcdc9eb 956 jme->jme_rx(skb);
b3821cc5 957 }
3bf61c55 958
94c5ea02
GFT		 959 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
960 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 961 ++(NET_STAT(jme).multicast);
962
3bf61c55
GFT		 963 NET_STAT(jme).rx_bytes += framesize;
964 ++(NET_STAT(jme).rx_packets);
965 }
966
967 jme_set_clean_rxdesc(jme, idx);
968
969}
970
971static int
972jme_process_receive(struct jme_adapter *jme, int limit)
973{
974 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 975 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 976 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 977
cd0ff491 978 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 979 goto out_inc;
980
cd0ff491 981 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 982 goto out_inc;
983
cd0ff491 984 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 985 goto out_inc;
986
cdcdc9eb 987 i = atomic_read(&rxring->next_to_clean);
fa97b924 988 while (limit > 0) {
3bf61c55
GFT		 989 rxdesc = rxring->desc;
990 rxdesc += i;
991
94c5ea02 992 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 993 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
994 goto out;
fa97b924 995 --limit;
d7699f87 996
4330c2f2
GFT		 997 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
998
cd0ff491 999 if (unlikely(desccnt > 1 ||
192570e0 1000 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1001
cd0ff491 1002 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1003 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1004 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1005 ++(NET_STAT(jme).rx_fifo_errors);
1006 else
1007 ++(NET_STAT(jme).rx_errors);
4330c2f2 1008
cd0ff491 1009 if (desccnt > 1)
3bf61c55 1010 limit -= desccnt - 1;
4330c2f2 1011
cd0ff491 1012 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1013 jme_set_clean_rxdesc(jme, j);
b3821cc5 1014 j = (j + 1) & (mask);
4330c2f2 1015 }
3bf61c55 1016
cd0ff491 1017 } else {
42b1055e 1018 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1019 }
4330c2f2 1020
b3821cc5 1021 i = (i + desccnt) & (mask);
3bf61c55 1022 }
4330c2f2 1023
3bf61c55 1024out:
cdcdc9eb 1025 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1026
192570e0
GFT		 1027out_inc:
1028 atomic_inc(&jme->rx_cleaning);
1029
3bf61c55 1030 return limit > 0 ? limit : 0;
4330c2f2 1031
3bf61c55 1032}
d7699f87 1033
79ce639c
GFT		 1034static void
1035jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1036{
cd0ff491 1037 if (likely(atmp == dpi->cur)) {
192570e0 1038 dpi->cnt = 0;
79ce639c 1039 return;
192570e0 1040 }
79ce639c 1041
cd0ff491 1042 if (dpi->attempt == atmp) {
79ce639c 1043 ++(dpi->cnt);
cd0ff491 1044 } else {
79ce639c
GFT		 1045 dpi->attempt = atmp;
1046 dpi->cnt = 0;
1047 }
1048
1049}
1050
1051static void
1052jme_dynamic_pcc(struct jme_adapter *jme)
1053{
1054 register struct dynpcc_info *dpi = &(jme->dpi);
1055
cd0ff491 1056 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1057 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT		 1058 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1059 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1060 jme_attempt_pcc(dpi, PCC_P2);
1061 else
1062 jme_attempt_pcc(dpi, PCC_P1);
1063
cd0ff491
GFT		 1064 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1065 if (dpi->attempt < dpi->cur)
1066 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1067 jme_set_rx_pcc(jme, dpi->attempt);
1068 dpi->cur = dpi->attempt;
1069 dpi->cnt = 0;
1070 }
1071}
1072
1073static void
1074jme_start_pcc_timer(struct jme_adapter *jme)
1075{
1076 struct dynpcc_info *dpi = &(jme->dpi);
1077 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1078 dpi->last_pkts = NET_STAT(jme).rx_packets;
1079 dpi->intr_cnt = 0;
1080 jwrite32(jme, JME_TMCSR,
1081 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1082}
1083
cd0ff491 1084static inline void
29bdd921
GFT		 1085jme_stop_pcc_timer(struct jme_adapter *jme)
1086{
1087 jwrite32(jme, JME_TMCSR, 0);
1088}
1089
cd0ff491
GFT		 1090static void
1091jme_shutdown_nic(struct jme_adapter *jme)
1092{
1093 u32 phylink;
1094
1095 phylink = jme_linkstat_from_phy(jme);
1096
1097 if (!(phylink & PHY_LINK_UP)) {
1098 /*
1099 * Disable all interrupt before issue timer
1100 */
1101 jme_stop_irq(jme);
1102 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1103 }
1104}
1105
79ce639c
GFT		 1106static void
1107jme_pcc_tasklet(unsigned long arg)
1108{
cd0ff491 1109 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1110 struct net_device *netdev = jme->dev;
1111
cd0ff491
GFT		 1112 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1113 jme_shutdown_nic(jme);
1114 return;
1115 }
29bdd921 1116
cd0ff491 1117 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1118 (atomic_read(&jme->link_changing) != 1)
1119 )) {
1120 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1121 return;
1122 }
29bdd921 1123
cd0ff491 1124 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1125 jme_dynamic_pcc(jme);
1126
79ce639c
GFT		 1127 jme_start_pcc_timer(jme);
1128}
1129
cd0ff491 1130static inline void
192570e0
GFT		 1131jme_polling_mode(struct jme_adapter *jme)
1132{
1133 jme_set_rx_pcc(jme, PCC_OFF);
1134}
1135
cd0ff491 1136static inline void
192570e0
GFT		 1137jme_interrupt_mode(struct jme_adapter *jme)
1138{
1139 jme_set_rx_pcc(jme, PCC_P1);
1140}
1141
cd0ff491
GFT		 1142static inline int
1143jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1144{
1145 u32 apmc;
1146 apmc = jread32(jme, JME_APMC);
1147 return apmc & JME_APMC_PSEUDO_HP_EN;
1148}
1149
1150static void
1151jme_start_shutdown_timer(struct jme_adapter *jme)
1152{
1153 u32 apmc;
1154
1155 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1156 apmc &= ~JME_APMC_EPIEN_CTRL;
1157 if (!no_extplug) {
1158 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1159 wmb();
1160 }
1161 jwrite32f(jme, JME_APMC, apmc);
1162
1163 jwrite32f(jme, JME_TIMER2, 0);
1164 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1165 jwrite32(jme, JME_TMCSR,
1166 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1167}
1168
1169static void
1170jme_stop_shutdown_timer(struct jme_adapter *jme)
1171{
1172 u32 apmc;
1173
1174 jwrite32f(jme, JME_TMCSR, 0);
1175 jwrite32f(jme, JME_TIMER2, 0);
1176 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1177
1178 apmc = jread32(jme, JME_APMC);
1179 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1180 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1181 wmb();
1182 jwrite32f(jme, JME_APMC, apmc);
1183}
1184
3bf61c55
GFT		 1185static void
1186jme_link_change_tasklet(unsigned long arg)
1187{
cd0ff491 1188 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1189 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1190 int rc;
1191
cd0ff491
GFT		 1192 while (!atomic_dec_and_test(&jme->link_changing)) {
1193 atomic_inc(&jme->link_changing);
c97b5740 1194 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
e882564f 1195 while (atomic_read(&jme->link_changing) != 1)
c97b5740 1196 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
cd0ff491 1197 }
fcf45b4c 1198
cd0ff491 1199 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1200 goto out;
1201
29bdd921 1202 jme->old_mtu = netdev->mtu;
fcf45b4c 1203 netif_stop_queue(netdev);
cd0ff491
GFT		 1204 if (jme_pseudo_hotplug_enabled(jme))
1205 jme_stop_shutdown_timer(jme);
1206
1207 jme_stop_pcc_timer(jme);
1208 tasklet_disable(&jme->txclean_task);
1209 tasklet_disable(&jme->rxclean_task);
1210 tasklet_disable(&jme->rxempty_task);
1211
1212 if (netif_carrier_ok(netdev)) {
1213 jme_reset_ghc_speed(jme);
1214 jme_disable_rx_engine(jme);
1215 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1216 jme_reset_mac_processor(jme);
1217 jme_free_rx_resources(jme);
1218 jme_free_tx_resources(jme);
192570e0 1219
cd0ff491 1220 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1221 jme_polling_mode(jme);
cd0ff491
GFT		 1222
1223 netif_carrier_off(netdev);
fcf45b4c
GFT		 1224 }
1225
1226 jme_check_link(netdev, 0);
cd0ff491 1227 if (netif_carrier_ok(netdev)) {
fcf45b4c 1228 rc = jme_setup_rx_resources(jme);
cd0ff491
GFT		 1229 if (rc) {
1230 jeprintk(jme->pdev, "Allocating resources for RX error"
fcf45b4c 1231 ", Device STOPPED!\n");
cd0ff491 1232 goto out_enable_tasklet;
fcf45b4c
GFT		 1233 }
1234
fcf45b4c 1235 rc = jme_setup_tx_resources(jme);
cd0ff491
GFT		 1236 if (rc) {
1237 jeprintk(jme->pdev, "Allocating resources for TX error"
fcf45b4c
GFT		 1238 ", Device STOPPED!\n");
1239 goto err_out_free_rx_resources;
1240 }
1241
1242 jme_enable_rx_engine(jme);
1243 jme_enable_tx_engine(jme);
1244
1245 netif_start_queue(netdev);
192570e0 1246
cd0ff491 1247 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1248 jme_interrupt_mode(jme);
192570e0 1249
79ce639c 1250 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1251 } else if (jme_pseudo_hotplug_enabled(jme)) {
1252 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1253 }
1254
cd0ff491 1255 goto out_enable_tasklet;
fcf45b4c
GFT		 1256
1257err_out_free_rx_resources:
1258 jme_free_rx_resources(jme);
cd0ff491
GFT		 1259out_enable_tasklet:
1260 tasklet_enable(&jme->txclean_task);
1261 tasklet_hi_enable(&jme->rxclean_task);
1262 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1263out:
1264 atomic_inc(&jme->link_changing);
3bf61c55 1265}
d7699f87 1266
3bf61c55
GFT		 1267static void
1268jme_rx_clean_tasklet(unsigned long arg)
1269{
cd0ff491 1270 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1271 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1272
192570e0
GFT		 1273 jme_process_receive(jme, jme->rx_ring_size);
1274 ++(dpi->intr_cnt);
42b1055e 1275
192570e0 1276}
fcf45b4c 1277
192570e0 1278static int
cdcdc9eb 1279jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1280{
cdcdc9eb 1281 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1282 int rest;
fcf45b4c 1283
cdcdc9eb 1284 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1285
cd0ff491 1286 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1287 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1288 ++(NET_STAT(jme).rx_dropped);
1289 jme_restart_rx_engine(jme);
1290 }
1291 atomic_inc(&jme->rx_empty);
1292
cd0ff491 1293 if (rest) {
cdcdc9eb 1294 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1295 jme_interrupt_mode(jme);
1296 }
1297
cdcdc9eb
GFT		 1298 JME_NAPI_WEIGHT_SET(budget, rest);
1299 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1300}
1301
1302static void
1303jme_rx_empty_tasklet(unsigned long arg)
1304{
cd0ff491 1305 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1306
cd0ff491 1307 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1308 return;
1309
cd0ff491 1310 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1311 return;
1312
c97b5740 1313 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1314
fcf45b4c 1315 jme_rx_clean_tasklet(arg);
cdcdc9eb 1316
cd0ff491 1317 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1318 atomic_dec(&jme->rx_empty);
1319 ++(NET_STAT(jme).rx_dropped);
1320 jme_restart_rx_engine(jme);
1321 }
1322 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1323}
1324
b3821cc5
GFT		 1325static void
1326jme_wake_queue_if_stopped(struct jme_adapter *jme)
1327{
fa97b924 1328 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1329
1330 smp_wmb();
cd0ff491 1331 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1332 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
c97b5740 1333 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
b3821cc5 1334 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1335 }
1336
1337}
1338
3bf61c55
GFT		 1339static void
1340jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1341{
cd0ff491 1342 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1343 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1344 struct txdesc *txdesc = txring->desc;
3bf61c55 1345 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1346 int i, j, cnt = 0, max, err, mask;
3bf61c55 1347
cd0ff491
GFT		 1348 tx_dbg(jme, "Into txclean.\n");
1349
1350 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1351 goto out;
1352
cd0ff491 1353 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1354 goto out;
1355
cd0ff491 1356 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1357 goto out;
1358
b3821cc5
GFT		 1359 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1360 mask = jme->tx_ring_mask;
3bf61c55 1361
cd0ff491 1362 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1363
1364 ctxbi = txbi + i;
1365
cd0ff491 1366 if (likely(ctxbi->skb &&
b3821cc5 1367 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1368
cd0ff491
GFT		 1369 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1370 i, ctxbi->nr_desc, jiffies);
3bf61c55 1371
cd0ff491 1372 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1373
cd0ff491 1374 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1375 ttxbi = txbi + ((i + j) & (mask));
1376 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1377
b3821cc5 1378 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1379 ttxbi->mapping,
1380 ttxbi->len,
1381 PCI_DMA_TODEVICE);
1382
3bf61c55
GFT		 1383 ttxbi->mapping = 0;
1384 ttxbi->len = 0;
1385 }
1386
1387 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1388
1389 cnt += ctxbi->nr_desc;
1390
cd0ff491 1391 if (unlikely(err)) {
8c198884 1392 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1393 } else {
8c198884 1394 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1395 NET_STAT(jme).tx_bytes += ctxbi->len;
1396 }
1397
1398 ctxbi->skb = NULL;
1399 ctxbi->len = 0;
cdcdc9eb 1400 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1401
1402 } else {
3bf61c55
GFT		 1403 break;
1404 }
1405
b3821cc5 1406 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1407
1408 ctxbi->nr_desc = 0;
d7699f87
GFT		 1409 }
1410
cd0ff491 1411 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
cdcdc9eb 1412 atomic_set(&txring->next_to_clean, i);
79ce639c 1413 atomic_add(cnt, &txring->nr_free);
3bf61c55 1414
b3821cc5
GFT		 1415 jme_wake_queue_if_stopped(jme);
1416
fcf45b4c
GFT		 1417out:
1418 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1419}
1420
79ce639c 1421static void
cd0ff491 1422jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1423{
3bf61c55
GFT		 1424 /*
1425 * Disable interrupt
1426 */
1427 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1428
cd0ff491 1429 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1430 /*
1431 * Link change event is critical
1432 * all other events are ignored
1433 */
1434 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1435 tasklet_schedule(&jme->linkch_task);
29bdd921 1436 goto out_reenable;
fcf45b4c 1437 }
d7699f87 1438
cd0ff491 1439 if (intrstat & INTR_TMINTR) {
47220951 1440 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1441 tasklet_schedule(&jme->pcc_task);
47220951 1442 }
79ce639c 1443
cd0ff491 1444 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1445 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1446 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1447 }
1448
cd0ff491 1449 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1450 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1451 INTR_PCCRX0 |
1452 INTR_RX0EMP)) |
1453 INTR_RX0);
1454 }
d7699f87 1455
cd0ff491
GFT		 1456 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1457 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1458 atomic_inc(&jme->rx_empty);
1459
cd0ff491
GFT		 1460 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1461 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1462 jme_polling_mode(jme);
cdcdc9eb 1463 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1464 }
1465 }
cd0ff491
GFT		 1466 } else {
1467 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1468 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1469 tasklet_hi_schedule(&jme->rxempty_task);
1470 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1471 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1472 }
4330c2f2 1473 }
d7699f87 1474
29bdd921 1475out_reenable:
3bf61c55 1476 /*
fcf45b4c 1477 * Re-enable interrupt
3bf61c55 1478 */
fcf45b4c 1479 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1480}
1481
1482static irqreturn_t
1483jme_intr(int irq, void *dev_id)
1484{
cd0ff491
GFT		 1485 struct net_device *netdev = dev_id;
1486 struct jme_adapter *jme = netdev_priv(netdev);
1487 u32 intrstat;
79ce639c
GFT		 1488
1489 intrstat = jread32(jme, JME_IEVE);
1490
1491 /*
1492 * Check if it's really an interrupt for us
1493 */
9b9d55de 1494 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1495 return IRQ_NONE;
79ce639c
GFT		 1496
1497 /*
1498 * Check if the device still exist
1499 */
cd0ff491
GFT		 1500 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1501 return IRQ_NONE;
79ce639c
GFT		 1502
1503 jme_intr_msi(jme, intrstat);
1504
cd0ff491 1505 return IRQ_HANDLED;
d7699f87
GFT		 1506}
1507
79ce639c
GFT		 1508static irqreturn_t
1509jme_msi(int irq, void *dev_id)
1510{
cd0ff491
GFT		 1511 struct net_device *netdev = dev_id;
1512 struct jme_adapter *jme = netdev_priv(netdev);
1513 u32 intrstat;
79ce639c 1514
fa97b924 1515 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1516
1517 jme_intr_msi(jme, intrstat);
1518
cd0ff491 1519 return IRQ_HANDLED;
79ce639c
GFT		 1520}
1521
79ce639c
GFT		 1522static void
1523jme_reset_link(struct jme_adapter *jme)
1524{
1525 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1526}
1527
fcf45b4c
GFT		 1528static void
1529jme_restart_an(struct jme_adapter *jme)
1530{
cd0ff491 1531 u32 bmcr;
fcf45b4c 1532
cd0ff491 1533 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1534 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1535 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1536 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1537 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1538}
1539
1540static int
1541jme_request_irq(struct jme_adapter *jme)
1542{
1543 int rc;
cd0ff491
GFT		 1544 struct net_device *netdev = jme->dev;
1545 irq_handler_t handler = jme_intr;
1546 int irq_flags = IRQF_SHARED;
1547
1548 if (!pci_enable_msi(jme->pdev)) {
1549 set_bit(JME_FLAG_MSI, &jme->flags);
1550 handler = jme_msi;
1551 irq_flags = 0;
1552 }
1553
1554 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1555 netdev);
1556 if (rc) {
1557 jeprintk(jme->pdev,
b3821cc5 1558 "Unable to request %s interrupt (return: %d)\n",
cd0ff491
GFT		 1559 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1560 rc);
79ce639c 1561
cd0ff491
GFT		 1562 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1563 pci_disable_msi(jme->pdev);
1564 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1565 }
cd0ff491 1566 } else {
79ce639c
GFT		 1567 netdev->irq = jme->pdev->irq;
1568 }
1569
cd0ff491 1570 return rc;
79ce639c
GFT		 1571}
1572
1573static void
1574jme_free_irq(struct jme_adapter *jme)
1575{
cd0ff491
GFT		 1576 free_irq(jme->pdev->irq, jme->dev);
1577 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1578 pci_disable_msi(jme->pdev);
1579 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1580 jme->dev->irq = jme->pdev->irq;
cd0ff491 1581 }
fcf45b4c
GFT		 1582}
1583
3bf61c55
GFT		 1584static int
1585jme_open(struct net_device *netdev)
d7699f87
GFT		 1586{
1587 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1588 int rc;
79ce639c 1589
42b1055e 1590 jme_clear_pm(jme);
cdcdc9eb 1591 JME_NAPI_ENABLE(jme);
d7699f87 1592
fa97b924 1593 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1594 tasklet_enable(&jme->txclean_task);
1595 tasklet_hi_enable(&jme->rxclean_task);
1596 tasklet_hi_enable(&jme->rxempty_task);
1597
79ce639c 1598 rc = jme_request_irq(jme);
cd0ff491 1599 if (rc)
4330c2f2 1600 goto err_out;
79ce639c 1601
d7699f87 1602 jme_start_irq(jme);
42b1055e 1603
cd0ff491 1604 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e
GFT		 1605 jme_set_settings(netdev, &jme->old_ecmd);
1606 else
1607 jme_reset_phy_processor(jme);
1608
29bdd921 1609 jme_reset_link(jme);
d7699f87
GFT		 1610
1611 return 0;
1612
d7699f87
GFT		 1613err_out:
1614 netif_stop_queue(netdev);
1615 netif_carrier_off(netdev);
4330c2f2 1616 return rc;
d7699f87
GFT		 1617}
1618
9b9d55de 1619#ifdef CONFIG_PM
42b1055e
GFT		 1620static void
1621jme_set_100m_half(struct jme_adapter *jme)
1622{
cd0ff491 1623 u32 bmcr, tmp;
42b1055e
GFT		 1624
1625 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1626 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1627 BMCR_SPEED1000 | BMCR_FULLDPLX);
1628 tmp |= BMCR_SPEED100;
1629
1630 if (bmcr != tmp)
1631 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1632
cd0ff491 1633 if (jme->fpgaver)
cdcdc9eb
GFT		 1634 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1635 else
1636 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1637}
1638
47220951
GFT		 1639#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1640static void
1641jme_wait_link(struct jme_adapter *jme)
1642{
cd0ff491 1643 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1644
1645 mdelay(1000);
1646 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1647 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1648 mdelay(10);
1649 phylink = jme_linkstat_from_phy(jme);
1650 }
1651}
9b9d55de 1652#endif
47220951 1653
cd0ff491 1654static inline void
42b1055e
GFT		 1655jme_phy_off(struct jme_adapter *jme)
1656{
1657 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1658}
1659
3bf61c55
GFT		 1660static int
1661jme_close(struct net_device *netdev)
d7699f87
GFT		 1662{
1663 struct jme_adapter *jme = netdev_priv(netdev);
1664
1665 netif_stop_queue(netdev);
1666 netif_carrier_off(netdev);
1667
1668 jme_stop_irq(jme);
79ce639c 1669 jme_free_irq(jme);
d7699f87 1670
cdcdc9eb 1671 JME_NAPI_DISABLE(jme);
192570e0 1672
fa97b924
GFT		 1673 tasklet_disable(&jme->linkch_task);
1674 tasklet_disable(&jme->txclean_task);
1675 tasklet_disable(&jme->rxclean_task);
1676 tasklet_disable(&jme->rxempty_task);
8c198884 1677
cd0ff491
GFT		 1678 jme_reset_ghc_speed(jme);
1679 jme_disable_rx_engine(jme);
1680 jme_disable_tx_engine(jme);
8c198884 1681 jme_reset_mac_processor(jme);
d7699f87
GFT		 1682 jme_free_rx_resources(jme);
1683 jme_free_tx_resources(jme);
42b1055e 1684 jme->phylink = 0;
b3821cc5
GFT		 1685 jme_phy_off(jme);
1686
1687 return 0;
1688}
1689
1690static int
1691jme_alloc_txdesc(struct jme_adapter *jme,
1692 struct sk_buff *skb)
1693{
fa97b924 1694 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1695 int idx, nr_alloc, mask = jme->tx_ring_mask;
1696
1697 idx = txring->next_to_use;
1698 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1699
cd0ff491 1700 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1701 return -1;
1702
1703 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1704
b3821cc5
GFT		 1705 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1706
1707 return idx;
1708}
1709
1710static void
1711jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1712 struct txdesc *txdesc,
b3821cc5
GFT		 1713 struct jme_buffer_info *txbi,
1714 struct page *page,
cd0ff491
GFT		 1715 u32 page_offset,
1716 u32 len,
1717 u8 hidma)
b3821cc5
GFT		 1718{
1719 dma_addr_t dmaaddr;
1720
1721 dmaaddr = pci_map_page(pdev,
1722 page,
1723 page_offset,
1724 len,
1725 PCI_DMA_TODEVICE);
1726
1727 pci_dma_sync_single_for_device(pdev,
1728 dmaaddr,
1729 len,
1730 PCI_DMA_TODEVICE);
1731
1732 txdesc->dw[0] = 0;
1733 txdesc->dw[1] = 0;
1734 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1735 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1736 txdesc->desc2.datalen = cpu_to_le16(len);
1737 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1738 txdesc->desc2.bufaddrl = cpu_to_le32(
1739 (__u64)dmaaddr & 0xFFFFFFFFUL);
1740
1741 txbi->mapping = dmaaddr;
1742 txbi->len = len;
1743}
1744
1745static void
1746jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1747{
fa97b924 1748 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1749 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1750 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1751 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1752 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1753 int mask = jme->tx_ring_mask;
1754 struct skb_frag_struct *frag;
cd0ff491 1755 u32 len;
b3821cc5 1756
cd0ff491
GFT		 1757 for (i = 0 ; i < nr_frags ; ++i) {
1758 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1759 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1760 ctxbi = txbi + ((idx + i + 2) & (mask));
1761
1762 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1763 frag->page_offset, frag->size, hidma);
42b1055e 1764 }
b3821cc5 1765
cd0ff491 1766 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1767 ctxdesc = txdesc + ((idx + 1) & (mask));
1768 ctxbi = txbi + ((idx + 1) & (mask));
1769 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1770 offset_in_page(skb->data), len, hidma);
1771
1772}
1773
1774static int
1775jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1776{
cd0ff491 1777 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT		 1778 skb_header_cloned(skb) &&
1779 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1780 dev_kfree_skb(skb);
1781 return -1;
1782 }
1783
1784 return 0;
1785}
1786
1787static int
94c5ea02 1788jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1789{
94c5ea02 1790 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1791 if (*mss) {
b3821cc5
GFT		 1792 *flags |= TXFLAG_LSEN;
1793
cd0ff491 1794 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 1795 struct iphdr *iph = ip_hdr(skb);
1796
1797 iph->check = 0;
cd0ff491 1798 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 1799 iph->daddr, 0,
1800 IPPROTO_TCP,
1801 0);
cd0ff491 1802 } else {
b3821cc5
GFT		 1803 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1804
cd0ff491 1805 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 1806 &ip6h->daddr, 0,
1807 IPPROTO_TCP,
1808 0);
1809 }
1810
1811 return 0;
1812 }
1813
1814 return 1;
1815}
1816
1817static void
cd0ff491 1818jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1819{
cd0ff491
GFT		 1820 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1821 u8 ip_proto;
b3821cc5
GFT		 1822
1823 switch (skb->protocol) {
cd0ff491 1824 case htons(ETH_P_IP):
b3821cc5
GFT		 1825 ip_proto = ip_hdr(skb)->protocol;
1826 break;
cd0ff491 1827 case htons(ETH_P_IPV6):
b3821cc5
GFT		 1828 ip_proto = ipv6_hdr(skb)->nexthdr;
1829 break;
1830 default:
1831 ip_proto = 0;
1832 break;
1833 }
1834
cd0ff491 1835 switch (ip_proto) {
b3821cc5
GFT		 1836 case IPPROTO_TCP:
1837 *flags |= TXFLAG_TCPCS;
1838 break;
1839 case IPPROTO_UDP:
1840 *flags |= TXFLAG_UDPCS;
1841 break;
1842 default:
c97b5740 1843 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
b3821cc5
GFT		 1844 break;
1845 }
1846 }
1847}
1848
cd0ff491 1849static inline void
94c5ea02 1850jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1851{
cd0ff491 1852 if (vlan_tx_tag_present(skb)) {
b3821cc5 1853 *flags |= TXFLAG_TAGON;
94c5ea02 1854 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1855 }
b3821cc5
GFT		 1856}
1857
1858static int
94c5ea02 1859jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1860{
fa97b924 1861 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1862 struct txdesc *txdesc;
b3821cc5 1863 struct jme_buffer_info *txbi;
cd0ff491 1864 u8 flags;
b3821cc5 1865
cd0ff491 1866 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 1867 txbi = txring->bufinf + idx;
1868
1869 txdesc->dw[0] = 0;
1870 txdesc->dw[1] = 0;
1871 txdesc->dw[2] = 0;
1872 txdesc->dw[3] = 0;
1873 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1874 /*
1875 * Set OWN bit at final.
1876 * When kernel transmit faster than NIC.
1877 * And NIC trying to send this descriptor before we tell
1878 * it to start sending this TX queue.
1879 * Other fields are already filled correctly.
1880 */
1881 wmb();
1882 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 1883 /*
1884 * Set checksum flags while not tso
1885 */
1886 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1887 jme_tx_csum(jme, skb, &flags);
b3821cc5 1888 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 1889 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 1890 txdesc->desc1.flags = flags;
1891 /*
1892 * Set tx buffer info after telling NIC to send
1893 * For better tx_clean timing
1894 */
1895 wmb();
1896 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1897 txbi->skb = skb;
1898 txbi->len = skb->len;
cd0ff491
GFT		 1899 txbi->start_xmit = jiffies;
1900 if (!txbi->start_xmit)
8d27293f 1901 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 1902
1903 return 0;
1904}
1905
b3821cc5
GFT		 1906static void
1907jme_stop_queue_if_full(struct jme_adapter *jme)
1908{
fa97b924 1909 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 1910 struct jme_buffer_info *txbi = txring->bufinf;
1911 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1912
cd0ff491 1913 txbi += idx;
b3821cc5
GFT		 1914
1915 smp_wmb();
cd0ff491 1916 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1917 netif_stop_queue(jme->dev);
c97b5740 1918 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
b3821cc5 1919 smp_wmb();
cd0ff491
GFT		 1920 if (atomic_read(&txring->nr_free)
1921 >= (jme->tx_wake_threshold)) {
b3821cc5 1922 netif_wake_queue(jme->dev);
c97b5740 1923 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
b3821cc5
GFT		 1924 }
1925 }
1926
cd0ff491 1927 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 1928 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1929 txbi->skb)) {
1930 netif_stop_queue(jme->dev);
c97b5740 1931 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
cdcdc9eb 1932 }
b3821cc5
GFT		 1933}
1934
3bf61c55
GFT		 1935/*
1936 * This function is already protected by netif_tx_lock()
1937 */
cd0ff491 1938
c97b5740 1939static netdev_tx_t
3bf61c55 1940jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 1941{
cd0ff491 1942 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1943 int idx;
d7699f87 1944
cd0ff491 1945 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 1946 ++(NET_STAT(jme).tx_dropped);
1947 return NETDEV_TX_OK;
1948 }
1949
1950 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1951
cd0ff491 1952 if (unlikely(idx < 0)) {
b3821cc5 1953 netif_stop_queue(netdev);
c97b5740 1954 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
d7699f87 1955
cd0ff491 1956 return NETDEV_TX_BUSY;
b3821cc5
GFT		 1957 }
1958
94c5ea02 1959 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 1960
4330c2f2
GFT		 1961 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1962 TXCS_SELECT_QUEUE0 |
1963 TXCS_QUEUE0S |
1964 TXCS_ENABLE);
d7699f87 1965
cd0ff491
GFT		 1966 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1967 skb_shinfo(skb)->nr_frags + 2,
1968 jiffies);
b3821cc5
GFT		 1969 jme_stop_queue_if_full(jme);
1970
cd0ff491 1971 return NETDEV_TX_OK;
d7699f87
GFT		 1972}
1973
3bf61c55
GFT		 1974static int
1975jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 1976{
cd0ff491 1977 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1978 struct sockaddr *addr = p;
cd0ff491 1979 u32 val;
d7699f87 1980
cd0ff491 1981 if (netif_running(netdev))
d7699f87
GFT		 1982 return -EBUSY;
1983
cd0ff491 1984 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT		 1985 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1986
186fc259
GFT		 1987 val = (addr->sa_data[3] & 0xff) << 24 |
1988 (addr->sa_data[2] & 0xff) << 16 |
1989 (addr->sa_data[1] & 0xff) << 8 |
1990 (addr->sa_data[0] & 0xff);
4330c2f2 1991 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT		 1992 val = (addr->sa_data[5] & 0xff) << 8 |
1993 (addr->sa_data[4] & 0xff);
4330c2f2 1994 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 1995 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 1996
1997 return 0;
1998}
1999
3bf61c55
GFT		 2000static void
2001jme_set_multi(struct net_device *netdev)
d7699f87 2002{
3bf61c55 2003 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2004 u32 mc_hash[2] = {};
d7699f87 2005
cd0ff491 2006 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2007
2008 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2009
cd0ff491 2010 if (netdev->flags & IFF_PROMISC) {
8c198884 2011 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2012 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2013 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2014 } else if (netdev->flags & IFF_MULTICAST) {
3bf61c55
GFT		 2015 struct dev_mc_list *mclist;
2016 int bit_nr;
d7699f87 2017
8c198884 2018 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
c97b5740 2019 netdev_for_each_mc_addr(mclist, netdev) {
cd0ff491
GFT		 2020 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2021 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2022 }
d7699f87 2023
4330c2f2
GFT		 2024 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2025 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2026 }
2027
d7699f87 2028 wmb();
8c198884
GFT		 2029 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2030
cd0ff491 2031 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2032}
2033
3bf61c55 2034static int
8c198884 2035jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2036{
cd0ff491 2037 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2038
cd0ff491 2039 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2040 return 0;
2041
cd0ff491
GFT		 2042 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2043 ((new_mtu) < IPV6_MIN_MTU))
2044 return -EINVAL;
79ce639c 2045
cd0ff491 2046 if (new_mtu > 4000) {
79ce639c
GFT		 2047 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2048 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2049 jme_restart_rx_engine(jme);
cd0ff491 2050 } else {
79ce639c
GFT		 2051 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2052 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2053 jme_restart_rx_engine(jme);
2054 }
2055
cd0ff491 2056 if (new_mtu > 1900) {
b3821cc5
GFT		 2057 netdev->features &= ~(NETIF_F_HW_CSUM |
2058 NETIF_F_TSO |
2059 NETIF_F_TSO6);
cd0ff491
GFT		 2060 } else {
2061 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2062 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2063 if (test_bit(JME_FLAG_TSO, &jme->flags))
b3821cc5 2064 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 2065 }
2066
cd0ff491
GFT		 2067 netdev->mtu = new_mtu;
2068 jme_reset_link(jme);
79ce639c
GFT		 2069
2070 return 0;
d7699f87
GFT		 2071}
2072
8c198884
GFT		 2073static void
2074jme_tx_timeout(struct net_device *netdev)
2075{
cd0ff491 2076 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2077
cdcdc9eb
GFT		 2078 jme->phylink = 0;
2079 jme_reset_phy_processor(jme);
cd0ff491 2080 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2081 jme_set_settings(netdev, &jme->old_ecmd);
2082
8c198884 2083 /*
cdcdc9eb 2084 * Force to Reset the link again
8c198884 2085 */
29bdd921 2086 jme_reset_link(jme);
8c198884
GFT		 2087}
2088
42b1055e
GFT		 2089static void
2090jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2091{
2092 struct jme_adapter *jme = netdev_priv(netdev);
2093
c97b5740 2094 spin_lock_bh(&jme->vlgrp_lock);
42b1055e 2095 jme->vlgrp = grp;
c97b5740 2096 spin_unlock_bh(&jme->vlgrp_lock);
42b1055e
GFT		 2097}
2098
3bf61c55
GFT		 2099static void
2100jme_get_drvinfo(struct net_device *netdev,
2101 struct ethtool_drvinfo *info)
d7699f87 2102{
cd0ff491 2103 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2104
cd0ff491
GFT		 2105 strcpy(info->driver, DRV_NAME);
2106 strcpy(info->version, DRV_VERSION);
2107 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2108}
2109
8c198884
GFT		 2110static int
2111jme_get_regs_len(struct net_device *netdev)
2112{
cd0ff491 2113 return JME_REG_LEN;
8c198884
GFT		 2114}
2115
2116static void
cd0ff491 2117mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2118{
2119 int i;
2120
cd0ff491 2121 for (i = 0 ; i < len ; i += 4)
79ce639c 2122 p[i >> 2] = jread32(jme, reg + i);
186fc259 2123}
8c198884 2124
186fc259 2125static void
cd0ff491 2126mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2127{
2128 int i;
cd0ff491 2129 u16 *p16 = (u16 *)p;
186fc259 2130
cd0ff491 2131 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2132 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2133}
2134
2135static void
2136jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2137{
cd0ff491
GFT		 2138 struct jme_adapter *jme = netdev_priv(netdev);
2139 u32 *p32 = (u32 *)p;
8c198884 2140
186fc259 2141 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2142
2143 regs->version = 1;
2144 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2145
2146 p32 += 0x100 >> 2;
2147 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2148
2149 p32 += 0x100 >> 2;
2150 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2151
2152 p32 += 0x100 >> 2;
2153 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2154
186fc259
GFT		 2155 p32 += 0x100 >> 2;
2156 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2157}
2158
2159static int
2160jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2161{
2162 struct jme_adapter *jme = netdev_priv(netdev);
2163
8c198884
GFT		 2164 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2165 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2166
cd0ff491 2167 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2168 ecmd->use_adaptive_rx_coalesce = false;
2169 ecmd->rx_coalesce_usecs = 0;
2170 ecmd->rx_max_coalesced_frames = 0;
2171 return 0;
2172 }
2173
2174 ecmd->use_adaptive_rx_coalesce = true;
2175
cd0ff491 2176 switch (jme->dpi.cur) {
8c198884
GFT		 2177 case PCC_P1:
2178 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2179 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2180 break;
2181 case PCC_P2:
2182 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2183 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2184 break;
2185 case PCC_P3:
2186 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2187 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2188 break;
2189 default:
2190 break;
2191 }
2192
2193 return 0;
2194}
2195
192570e0
GFT		 2196static int
2197jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2198{
2199 struct jme_adapter *jme = netdev_priv(netdev);
2200 struct dynpcc_info *dpi = &(jme->dpi);
2201
cd0ff491 2202 if (netif_running(netdev))
cdcdc9eb
GFT		 2203 return -EBUSY;
2204
c97b5740
GFT		 2205 if (ecmd->use_adaptive_rx_coalesce &&
2206 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2207 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2208 jme->jme_rx = netif_rx;
2209 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2210 dpi->cur = PCC_P1;
2211 dpi->attempt = PCC_P1;
2212 dpi->cnt = 0;
2213 jme_set_rx_pcc(jme, PCC_P1);
2214 jme_interrupt_mode(jme);
c97b5740
GFT		 2215 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2216 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2217 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2218 jme->jme_rx = netif_receive_skb;
2219 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2220 jme_interrupt_mode(jme);
2221 }
2222
2223 return 0;
2224}
2225
8c198884
GFT		 2226static void
2227jme_get_pauseparam(struct net_device *netdev,
2228 struct ethtool_pauseparam *ecmd)
2229{
2230 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2231 u32 val;
8c198884
GFT		 2232
2233 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2234 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2235
cd0ff491
GFT		 2236 spin_lock_bh(&jme->phy_lock);
2237 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2238 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2239
2240 ecmd->autoneg =
2241 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2242}
2243
2244static int
2245jme_set_pauseparam(struct net_device *netdev,
2246 struct ethtool_pauseparam *ecmd)
2247{
2248 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2249 u32 val;
8c198884 2250
cd0ff491 2251 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2252 (ecmd->tx_pause != 0)) {
2253
cd0ff491 2254 if (ecmd->tx_pause)
8c198884
GFT		 2255 jme->reg_txpfc |= TXPFC_PF_EN;
2256 else
2257 jme->reg_txpfc &= ~TXPFC_PF_EN;
2258
2259 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2260 }
2261
cd0ff491
GFT		 2262 spin_lock_bh(&jme->rxmcs_lock);
2263 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2264 (ecmd->rx_pause != 0)) {
2265
cd0ff491 2266 if (ecmd->rx_pause)
8c198884
GFT		 2267 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2268 else
2269 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2270
2271 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2272 }
cd0ff491 2273 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2274
cd0ff491
GFT		 2275 spin_lock_bh(&jme->phy_lock);
2276 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2277 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2278 (ecmd->autoneg != 0)) {
2279
cd0ff491 2280 if (ecmd->autoneg)
8c198884
GFT		 2281 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2282 else
2283 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2284
b3821cc5
GFT		 2285 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2286 MII_ADVERTISE, val);
8c198884 2287 }
cd0ff491 2288 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2289
2290 return 0;
2291}
2292
29bdd921
GFT		 2293static void
2294jme_get_wol(struct net_device *netdev,
2295 struct ethtool_wolinfo *wol)
2296{
2297 struct jme_adapter *jme = netdev_priv(netdev);
2298
2299 wol->supported = WAKE_MAGIC | WAKE_PHY;
2300
2301 wol->wolopts = 0;
2302
cd0ff491 2303 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2304 wol->wolopts |= WAKE_PHY;
2305
cd0ff491 2306 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2307 wol->wolopts |= WAKE_MAGIC;
2308
2309}
2310
2311static int
2312jme_set_wol(struct net_device *netdev,
2313 struct ethtool_wolinfo *wol)
2314{
2315 struct jme_adapter *jme = netdev_priv(netdev);
2316
cd0ff491 2317 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2318 WAKE_UCAST |
2319 WAKE_MCAST |
2320 WAKE_BCAST |
2321 WAKE_ARP))
2322 return -EOPNOTSUPP;
2323
2324 jme->reg_pmcs = 0;
2325
cd0ff491 2326 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2327 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2328
cd0ff491 2329 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2330 jme->reg_pmcs |= PMCS_MFEN;
2331
cd0ff491 2332 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2333
29bdd921
GFT		 2334 return 0;
2335}
b3821cc5 2336
3bf61c55
GFT		 2337static int
2338jme_get_settings(struct net_device *netdev,
2339 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2340{
2341 struct jme_adapter *jme = netdev_priv(netdev);
2342 int rc;
8c198884 2343
cd0ff491 2344 spin_lock_bh(&jme->phy_lock);
d7699f87 2345 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2346 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2347 return rc;
2348}
2349
3bf61c55
GFT		 2350static int
2351jme_set_settings(struct net_device *netdev,
2352 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2353{
2354 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2355 int rc, fdc = 0;
fcf45b4c 2356
cd0ff491 2357 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2358 return -EINVAL;
2359
cd0ff491 2360 if (jme->mii_if.force_media &&
79ce639c
GFT		 2361 ecmd->autoneg != AUTONEG_ENABLE &&
2362 (jme->mii_if.full_duplex != ecmd->duplex))
2363 fdc = 1;
2364
cd0ff491 2365 spin_lock_bh(&jme->phy_lock);
d7699f87 2366 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2367 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2368
cd0ff491 2369 if (!rc && fdc)
79ce639c
GFT		 2370 jme_reset_link(jme);
2371
cd0ff491
GFT		 2372 if (!rc) {
2373 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2374 jme->old_ecmd = *ecmd;
2375 }
2376
d7699f87
GFT		 2377 return rc;
2378}
2379
cd0ff491 2380static u32
3bf61c55
GFT		 2381jme_get_link(struct net_device *netdev)
2382{
d7699f87
GFT		 2383 struct jme_adapter *jme = netdev_priv(netdev);
2384 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2385}
2386
8c198884 2387static u32
cd0ff491
GFT		 2388jme_get_msglevel(struct net_device *netdev)
2389{
2390 struct jme_adapter *jme = netdev_priv(netdev);
2391 return jme->msg_enable;
2392}
2393
2394static void
2395jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2396{
cd0ff491
GFT		 2397 struct jme_adapter *jme = netdev_priv(netdev);
2398 jme->msg_enable = value;
2399}
8c198884 2400
cd0ff491
GFT		 2401static u32
2402jme_get_rx_csum(struct net_device *netdev)
2403{
2404 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2405 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2406}
2407
2408static int
2409jme_set_rx_csum(struct net_device *netdev, u32 on)
2410{
cd0ff491 2411 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2412
cd0ff491
GFT		 2413 spin_lock_bh(&jme->rxmcs_lock);
2414 if (on)
8c198884
GFT		 2415 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2416 else
2417 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2418 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2419 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2420
2421 return 0;
2422}
2423
2424static int
2425jme_set_tx_csum(struct net_device *netdev, u32 on)
2426{
cd0ff491 2427 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2428
cd0ff491
GFT		 2429 if (on) {
2430 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2431 if (netdev->mtu <= 1900)
b3821cc5 2432 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT		 2433 } else {
2434 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2435 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2436 }
8c198884
GFT		 2437
2438 return 0;
2439}
2440
b3821cc5
GFT		 2441static int
2442jme_set_tso(struct net_device *netdev, u32 on)
2443{
cd0ff491 2444 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2445
cd0ff491
GFT		 2446 if (on) {
2447 set_bit(JME_FLAG_TSO, &jme->flags);
2448 if (netdev->mtu <= 1900)
b3821cc5 2449 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2450 } else {
2451 clear_bit(JME_FLAG_TSO, &jme->flags);
2452 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2453 }
2454
cd0ff491 2455 return 0;
b3821cc5
GFT		 2456}
2457
8c198884
GFT		 2458static int
2459jme_nway_reset(struct net_device *netdev)
2460{
cd0ff491 2461 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2462 jme_restart_an(jme);
2463 return 0;
2464}
2465
cd0ff491 2466static u8
186fc259
GFT		 2467jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2468{
cd0ff491 2469 u32 val;
186fc259
GFT		 2470 int to;
2471
2472 val = jread32(jme, JME_SMBCSR);
2473 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2474 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2475 msleep(1);
2476 val = jread32(jme, JME_SMBCSR);
2477 }
cd0ff491 2478 if (!to) {
c97b5740 2479 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT		 2480 return 0xFF;
2481 }
2482
2483 jwrite32(jme, JME_SMBINTF,
2484 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2485 SMBINTF_HWRWN_READ |
2486 SMBINTF_HWCMD);
2487
2488 val = jread32(jme, JME_SMBINTF);
2489 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2490 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2491 msleep(1);
2492 val = jread32(jme, JME_SMBINTF);
2493 }
cd0ff491 2494 if (!to) {
c97b5740 2495 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT		 2496 return 0xFF;
2497 }
2498
2499 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2500}
2501
2502static void
cd0ff491 2503jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2504{
cd0ff491 2505 u32 val;
186fc259
GFT		 2506 int to;
2507
2508 val = jread32(jme, JME_SMBCSR);
2509 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2510 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2511 msleep(1);
2512 val = jread32(jme, JME_SMBCSR);
2513 }
cd0ff491 2514 if (!to) {
c97b5740 2515 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT		 2516 return;
2517 }
2518
2519 jwrite32(jme, JME_SMBINTF,
2520 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2521 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2522 SMBINTF_HWRWN_WRITE |
2523 SMBINTF_HWCMD);
2524
2525 val = jread32(jme, JME_SMBINTF);
2526 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2527 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2528 msleep(1);
2529 val = jread32(jme, JME_SMBINTF);
2530 }
cd0ff491 2531 if (!to) {
c97b5740 2532 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT		 2533 return;
2534 }
2535
2536 mdelay(2);
2537}
2538
2539static int
2540jme_get_eeprom_len(struct net_device *netdev)
2541{
cd0ff491
GFT		 2542 struct jme_adapter *jme = netdev_priv(netdev);
2543 u32 val;
186fc259 2544 val = jread32(jme, JME_SMBCSR);
cd0ff491 2545 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2546}
2547
2548static int
2549jme_get_eeprom(struct net_device *netdev,
2550 struct ethtool_eeprom *eeprom, u8 *data)
2551{
cd0ff491 2552 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2553 int i, offset = eeprom->offset, len = eeprom->len;
2554
2555 /*
8d27293f 2556 * ethtool will check the boundary for us
186fc259
GFT		 2557 */
2558 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2559 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2560 data[i] = jme_smb_read(jme, i + offset);
2561
2562 return 0;
2563}
2564
2565static int
2566jme_set_eeprom(struct net_device *netdev,
2567 struct ethtool_eeprom *eeprom, u8 *data)
2568{
cd0ff491 2569 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2570 int i, offset = eeprom->offset, len = eeprom->len;
2571
2572 if (eeprom->magic != JME_EEPROM_MAGIC)
2573 return -EINVAL;
2574
2575 /*
8d27293f 2576 * ethtool will check the boundary for us
186fc259 2577 */
cd0ff491 2578 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2579 jme_smb_write(jme, i + offset, data[i]);
2580
2581 return 0;
2582}
2583
d7699f87 2584static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2585 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2586 .get_regs_len = jme_get_regs_len,
2587 .get_regs = jme_get_regs,
2588 .get_coalesce = jme_get_coalesce,
192570e0 2589 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2590 .get_pauseparam = jme_get_pauseparam,
2591 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2592 .get_wol = jme_get_wol,
2593 .set_wol = jme_set_wol,
d7699f87
GFT		 2594 .get_settings = jme_get_settings,
2595 .set_settings = jme_set_settings,
2596 .get_link = jme_get_link,
cd0ff491
GFT		 2597 .get_msglevel = jme_get_msglevel,
2598 .set_msglevel = jme_set_msglevel,
8c198884
GFT		 2599 .get_rx_csum = jme_get_rx_csum,
2600 .set_rx_csum = jme_set_rx_csum,
2601 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2602 .set_tso = jme_set_tso,
2603 .set_sg = ethtool_op_set_sg,
8c198884 2604 .nway_reset = jme_nway_reset,
186fc259
GFT		 2605 .get_eeprom_len = jme_get_eeprom_len,
2606 .get_eeprom = jme_get_eeprom,
2607 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2608};
2609
3bf61c55
GFT		 2610static int
2611jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2612{
94c5ea02 2613 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2614 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2615 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT		 2616 return 1;
2617
94c5ea02 2618 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2619 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2620 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT		 2621 return 1;
2622
fa97b924
GFT		 2623 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2624 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT		 2625 return 0;
2626
2627 return -1;
2628}
2629
cd0ff491 2630static inline void
cdcdc9eb
GFT		 2631jme_phy_init(struct jme_adapter *jme)
2632{
cd0ff491 2633 u16 reg26;
cdcdc9eb
GFT		 2634
2635 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2636 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2637}
2638
cd0ff491 2639static inline void
cdcdc9eb 2640jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2641{
cd0ff491 2642 u32 chipmode;
cdcdc9eb
GFT		 2643
2644 chipmode = jread32(jme, JME_CHIPMODE);
2645
2646 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2647 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT		 2648}
2649
94c5ea02
GFT		 2650static const struct net_device_ops jme_netdev_ops = {
2651 .ndo_open = jme_open,
2652 .ndo_stop = jme_close,
2653 .ndo_validate_addr = eth_validate_addr,
2654 .ndo_start_xmit = jme_start_xmit,
2655 .ndo_set_mac_address = jme_set_macaddr,
2656 .ndo_set_multicast_list = jme_set_multi,
2657 .ndo_change_mtu = jme_change_mtu,
2658 .ndo_tx_timeout = jme_tx_timeout,
2659 .ndo_vlan_rx_register = jme_vlan_rx_register,
2660};
2661
3bf61c55
GFT		 2662static int __devinit
2663jme_init_one(struct pci_dev *pdev,
2664 const struct pci_device_id *ent)
2665{
cdcdc9eb 2666 int rc = 0, using_dac, i;
d7699f87
GFT		 2667 struct net_device *netdev;
2668 struct jme_adapter *jme;
cd0ff491
GFT		 2669 u16 bmcr, bmsr;
2670 u32 apmc;
d7699f87
GFT		 2671
2672 /*
2673 * set up PCI device basics
2674 */
4330c2f2 2675 rc = pci_enable_device(pdev);
cd0ff491
GFT		 2676 if (rc) {
2677 jeprintk(pdev, "Cannot enable PCI device.\n");
4330c2f2
GFT		 2678 goto err_out;
2679 }
d7699f87 2680
3bf61c55 2681 using_dac = jme_pci_dma64(pdev);
cd0ff491
GFT		 2682 if (using_dac < 0) {
2683 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
3bf61c55
GFT		 2684 rc = -EIO;
2685 goto err_out_disable_pdev;
2686 }
2687
cd0ff491
GFT		 2688 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2689 jeprintk(pdev, "No PCI resource region found.\n");
4330c2f2
GFT		 2690 rc = -ENOMEM;
2691 goto err_out_disable_pdev;
2692 }
d7699f87 2693
4330c2f2 2694 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491
GFT		 2695 if (rc) {
2696 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
4330c2f2
GFT		 2697 goto err_out_disable_pdev;
2698 }
d7699f87
GFT		 2699
2700 pci_set_master(pdev);
2701
2702 /*
2703 * alloc and init net device
2704 */
3bf61c55 2705 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491
GFT		 2706 if (!netdev) {
2707 jeprintk(pdev, "Cannot allocate netdev structure.\n");
4330c2f2
GFT		 2708 rc = -ENOMEM;
2709 goto err_out_release_regions;
d7699f87 2710 }
94c5ea02 2711 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2712 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2713 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2714 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT		 2715 NETIF_F_SG |
2716 NETIF_F_TSO |
2717 NETIF_F_TSO6 |
42b1055e
GFT		 2718 NETIF_F_HW_VLAN_TX |
2719 NETIF_F_HW_VLAN_RX;
cd0ff491 2720 if (using_dac)
8c198884 2721 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 2722
2723 SET_NETDEV_DEV(netdev, &pdev->dev);
2724 pci_set_drvdata(pdev, netdev);
2725
2726 /*
2727 * init adapter info
2728 */
2729 jme = netdev_priv(netdev);
2730 jme->pdev = pdev;
2731 jme->dev = netdev;
cdcdc9eb
GFT		 2732 jme->jme_rx = netif_rx;
2733 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2734 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2735 jme->phylink = 0;
b3821cc5
GFT		 2736 jme->tx_ring_size = 1 << 10;
2737 jme->tx_ring_mask = jme->tx_ring_size - 1;
2738 jme->tx_wake_threshold = 1 << 9;
2739 jme->rx_ring_size = 1 << 9;
2740 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2741 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 2742 jme->regs = ioremap(pci_resource_start(pdev, 0),
2743 pci_resource_len(pdev, 0));
4330c2f2 2744 if (!(jme->regs)) {
cd0ff491 2745 jeprintk(pdev, "Mapping PCI resource region error.\n");
d7699f87
GFT		 2746 rc = -ENOMEM;
2747 goto err_out_free_netdev;
2748 }
4330c2f2 2749
cd0ff491
GFT		 2750 if (no_pseudohp) {
2751 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2752 jwrite32(jme, JME_APMC, apmc);
2753 } else if (force_pseudohp) {
2754 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2755 jwrite32(jme, JME_APMC, apmc);
2756 }
2757
cdcdc9eb 2758 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2759
d7699f87 2760 spin_lock_init(&jme->phy_lock);
fcf45b4c 2761 spin_lock_init(&jme->macaddr_lock);
8c198884 2762 spin_lock_init(&jme->rxmcs_lock);
c97b5740 2763 spin_lock_init(&jme->vlgrp_lock);
fcf45b4c 2764
fcf45b4c
GFT		 2765 atomic_set(&jme->link_changing, 1);
2766 atomic_set(&jme->rx_cleaning, 1);
2767 atomic_set(&jme->tx_cleaning, 1);
192570e0 2768 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2769
79ce639c 2770 tasklet_init(&jme->pcc_task,
c97b5740 2771 jme_pcc_tasklet,
79ce639c 2772 (unsigned long) jme);
4330c2f2 2773 tasklet_init(&jme->linkch_task,
c97b5740 2774 jme_link_change_tasklet,
4330c2f2
GFT		 2775 (unsigned long) jme);
2776 tasklet_init(&jme->txclean_task,
c97b5740 2777 jme_tx_clean_tasklet,
4330c2f2
GFT		 2778 (unsigned long) jme);
2779 tasklet_init(&jme->rxclean_task,
c97b5740 2780 jme_rx_clean_tasklet,
4330c2f2 2781 (unsigned long) jme);
fcf45b4c 2782 tasklet_init(&jme->rxempty_task,
c97b5740 2783 jme_rx_empty_tasklet,
fcf45b4c 2784 (unsigned long) jme);
fa97b924 2785 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 2786 tasklet_disable_nosync(&jme->txclean_task);
2787 tasklet_disable_nosync(&jme->rxclean_task);
2788 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 2789 jme->dpi.cur = PCC_P1;
2790
cd0ff491 2791 jme->reg_ghc = 0;
79ce639c 2792 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 2793 jme->reg_rxmcs = RXMCS_DEFAULT;
2794 jme->reg_txpfc = 0;
47220951 2795 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT		 2796 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2797 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2798
fcf45b4c
GFT		 2799 /*
2800 * Get Max Read Req Size from PCI Config Space
2801 */
cd0ff491
GFT		 2802 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2803 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2804 switch (jme->mrrs) {
2805 case MRRS_128B:
2806 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2807 break;
2808 case MRRS_256B:
2809 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2810 break;
2811 default:
2812 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2813 break;
fcf45b4c
GFT		 2814 };
2815
d7699f87 2816 /*
cdcdc9eb 2817 * Must check before reset_mac_processor
d7699f87 2818 */
cdcdc9eb
GFT		 2819 jme_check_hw_ver(jme);
2820 jme->mii_if.dev = netdev;
cd0ff491 2821 if (jme->fpgaver) {
cdcdc9eb 2822 jme->mii_if.phy_id = 0;
cd0ff491 2823 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 2824 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2825 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 2826 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 2827 jme->mii_if.phy_id = i;
2828 break;
2829 }
2830 }
2831
cd0ff491 2832 if (!jme->mii_if.phy_id) {
cdcdc9eb 2833 rc = -EIO;
cd0ff491 2834 jeprintk(pdev, "Can not find phy_id.\n");
fa97b924 2835 goto err_out_unmap;
cdcdc9eb
GFT		 2836 }
2837
2838 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 2839 } else {
cdcdc9eb
GFT		 2840 jme->mii_if.phy_id = 1;
2841 }
cd0ff491 2842 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 2843 jme->mii_if.supports_gmii = true;
2844 else
2845 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT		 2846 jme->mii_if.mdio_read = jme_mdio_read;
2847 jme->mii_if.mdio_write = jme_mdio_write;
2848
d7699f87 2849 jme_clear_pm(jme);
e882564f 2850 jme_set_phyfifoa(jme);
cd0ff491
GFT		 2851 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2852 if (!jme->fpgaver)
cdcdc9eb 2853 jme_phy_init(jme);
42b1055e 2854 jme_phy_off(jme);
cdcdc9eb
GFT		 2855
2856 /*
2857 * Reset MAC processor and reload EEPROM for MAC Address
2858 */
d7699f87 2859 jme_reset_mac_processor(jme);
4330c2f2 2860 rc = jme_reload_eeprom(jme);
cd0ff491
GFT		 2861 if (rc) {
2862 jeprintk(pdev,
b3821cc5 2863 "Reload eeprom for reading MAC Address error.\n");
fa97b924 2864 goto err_out_unmap;
4330c2f2 2865 }
d7699f87
GFT		 2866 jme_load_macaddr(netdev);
2867
d7699f87
GFT		 2868 /*
2869 * Tell stack that we are not ready to work until open()
2870 */
2871 netif_carrier_off(netdev);
2872 netif_stop_queue(netdev);
2873
2874 /*
2875 * Register netdev
2876 */
4330c2f2 2877 rc = register_netdev(netdev);
cd0ff491
GFT		 2878 if (rc) {
2879 jeprintk(pdev, "Cannot register net device.\n");
fa97b924 2880 goto err_out_unmap;
4330c2f2 2881 }
d7699f87 2882
c97b5740
GFT		 2883 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2884 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2885 "JMC250 Gigabit Ethernet" :
2886 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2887 "JMC260 Fast Ethernet" : "Unknown",
2888 (jme->fpgaver != 0) ? " (FPGA)" : "",
2889 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2890 jme->rev, netdev->dev_addr);
d7699f87
GFT		 2891
2892 return 0;
2893
2894err_out_unmap:
2895 iounmap(jme->regs);
2896err_out_free_netdev:
2897 pci_set_drvdata(pdev, NULL);
2898 free_netdev(netdev);
4330c2f2
GFT		 2899err_out_release_regions:
2900 pci_release_regions(pdev);
d7699f87 2901err_out_disable_pdev:
cd0ff491 2902 pci_disable_device(pdev);
d7699f87 2903err_out:
4330c2f2 2904 return rc;
d7699f87
GFT		 2905}
2906
3bf61c55
GFT		 2907static void __devexit
2908jme_remove_one(struct pci_dev *pdev)
2909{
d7699f87
GFT		 2910 struct net_device *netdev = pci_get_drvdata(pdev);
2911 struct jme_adapter *jme = netdev_priv(netdev);
2912
2913 unregister_netdev(netdev);
2914 iounmap(jme->regs);
2915 pci_set_drvdata(pdev, NULL);
2916 free_netdev(netdev);
2917 pci_release_regions(pdev);
2918 pci_disable_device(pdev);
2919
2920}
2921
9b9d55de 2922#ifdef CONFIG_PM
29bdd921
GFT		 2923static int
2924jme_suspend(struct pci_dev *pdev, pm_message_t state)
2925{
2926 struct net_device *netdev = pci_get_drvdata(pdev);
2927 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 2928
2929 atomic_dec(&jme->link_changing);
2930
2931 netif_device_detach(netdev);
2932 netif_stop_queue(netdev);
2933 jme_stop_irq(jme);
29bdd921 2934
cd0ff491
GFT		 2935 tasklet_disable(&jme->txclean_task);
2936 tasklet_disable(&jme->rxclean_task);
2937 tasklet_disable(&jme->rxempty_task);
2938
cd0ff491
GFT		 2939 if (netif_carrier_ok(netdev)) {
2940 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 2941 jme_polling_mode(jme);
2942
29bdd921 2943 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 2944 jme_reset_ghc_speed(jme);
2945 jme_disable_rx_engine(jme);
2946 jme_disable_tx_engine(jme);
29bdd921
GFT		 2947 jme_reset_mac_processor(jme);
2948 jme_free_rx_resources(jme);
2949 jme_free_tx_resources(jme);
2950 netif_carrier_off(netdev);
2951 jme->phylink = 0;
2952 }
2953
cd0ff491
GFT		 2954 tasklet_enable(&jme->txclean_task);
2955 tasklet_hi_enable(&jme->rxclean_task);
2956 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT		 2957
2958 pci_save_state(pdev);
cd0ff491 2959 if (jme->reg_pmcs) {
42b1055e 2960 jme_set_100m_half(jme);
47220951 2961
cd0ff491 2962 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT		 2963 jme_wait_link(jme);
2964
29bdd921 2965 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 2966
42b1055e 2967 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 2968 } else {
42b1055e 2969 jme_phy_off(jme);
29bdd921 2970 }
cd0ff491 2971 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT		 2972
2973 return 0;
2974}
2975
2976static int
2977jme_resume(struct pci_dev *pdev)
2978{
2979 struct net_device *netdev = pci_get_drvdata(pdev);
2980 struct jme_adapter *jme = netdev_priv(netdev);
2981
2982 jme_clear_pm(jme);
2983 pci_restore_state(pdev);
2984
cd0ff491 2985 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921
GFT		 2986 jme_set_settings(netdev, &jme->old_ecmd);
2987 else
2988 jme_reset_phy_processor(jme);
2989
29bdd921
GFT		 2990 jme_start_irq(jme);
2991 netif_device_attach(netdev);
2992
2993 atomic_inc(&jme->link_changing);
2994
2995 jme_reset_link(jme);
2996
2997 return 0;
2998}
9b9d55de 2999#endif
29bdd921 3000
c97b5740 3001static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT		 3002 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3003 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3004 { }
3005};
3006
3007static struct pci_driver jme_driver = {
cd0ff491
GFT		 3008 .name = DRV_NAME,
3009 .id_table = jme_pci_tbl,
3010 .probe = jme_init_one,
3011 .remove = __devexit_p(jme_remove_one),
d7699f87 3012#ifdef CONFIG_PM
cd0ff491
GFT		 3013 .suspend = jme_suspend,
3014 .resume = jme_resume,
d7699f87 3015#endif /* CONFIG_PM */
d7699f87
GFT		 3016};
3017
3bf61c55
GFT		 3018static int __init
3019jme_init_module(void)
d7699f87 3020{
94c5ea02 3021 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
4330c2f2 3022 "driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3023 return pci_register_driver(&jme_driver);
3024}
3025
3bf61c55
GFT		 3026static void __exit
3027jme_cleanup_module(void)
d7699f87
GFT		 3028{
3029 pci_unregister_driver(&jme_driver);
3030}
3031
3032module_init(jme_init_module);
3033module_exit(jme_cleanup_module);
3034
3bf61c55 3035MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3036MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3037MODULE_LICENSE("GPL");
3038MODULE_VERSION(DRV_VERSION);
3039MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3040
JMicron Ethernet Linux driver