jme: convert to SKB paged frag API.
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
52a46ba8
JP
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
d7699f87
GFT
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
4330c2f2 35#include <linux/delay.h>
29bdd921 36#include <linux/spinlock.h>
8c198884
GFT
37#include <linux/in.h>
38#include <linux/ip.h>
79ce639c
GFT
39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42b1055e 42#include <linux/if_vlan.h>
6d641c63 43#include <linux/slab.h>
94c5ea02 44#include <net/ip6_checksum.h>
d7699f87
GFT
45#include "jme.h"
46
cd0ff491
GFT
47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 58
3bf61c55
GFT
59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
61{
62 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 64
186fc259 65read_again:
cd0ff491 66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
d7699f87
GFT
69
70 wmb();
cd0ff491 71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 72 udelay(20);
b3821cc5
GFT
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
3bf61c55 75 break;
cd0ff491 76 }
d7699f87 77
cd0ff491 78 if (i == 0) {
52a46ba8 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 80 return 0;
cd0ff491 81 }
d7699f87 82
cd0ff491 83 if (again--)
186fc259
GFT
84 goto read_again;
85
cd0ff491 86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
87}
88
3bf61c55
GFT
89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
d7699f87
GFT
92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
3bf61c55
GFT
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
99
100 wmb();
cdcdc9eb
GFT
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
8d27293f 103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
104 break;
105 }
d7699f87 106
3bf61c55 107 if (i == 0)
52a46ba8 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
109}
110
cd0ff491 111static inline void
3bf61c55 112jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 113{
cd0ff491 114 u32 val;
3bf61c55
GFT
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
8c198884
GFT
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 120
cd0ff491 121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 126
fcf45b4c
GFT
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
134}
135
b3821cc5
GFT
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
0d8a2973 138 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
ed830419
GFT
163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
cd0ff491 224static inline void
3bf61c55
GFT
225jme_reset_mac_processor(struct jme_adapter *jme)
226{
0d8a2973 227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT
228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
b3821cc5
GFT
230 int i;
231
ed830419
GFT
232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
cd0ff491
GFT
250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
4330c2f2
GFT
260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 263 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 264 if (jme->fpgaver)
cdcdc9eb
GFT
265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT
269}
270
271static inline void
3bf61c55 272jme_clear_pm(struct jme_adapter *jme)
d7699f87 273{
18783c49 274 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT
275}
276
3bf61c55
GFT
277static int
278jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 279{
cd0ff491 280 u32 val;
d7699f87
GFT
281 int i;
282
283 val = jread32(jme, JME_SMBCSR);
284
cd0ff491 285 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
286 val |= SMBCSR_CNACK;
287 jwrite32(jme, JME_SMBCSR, val);
288 val |= SMBCSR_RELOAD;
289 jwrite32(jme, JME_SMBCSR, val);
290 mdelay(12);
291
cd0ff491 292 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
293 mdelay(1);
294 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
295 break;
296 }
297
cd0ff491 298 if (i == 0) {
52a46ba8 299 pr_err("eeprom reload timeout\n");
d7699f87
GFT
300 return -EIO;
301 }
302 }
3bf61c55 303
d7699f87
GFT
304 return 0;
305}
306
3bf61c55
GFT
307static void
308jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
309{
310 struct jme_adapter *jme = netdev_priv(netdev);
311 unsigned char macaddr[6];
cd0ff491 312 u32 val;
d7699f87 313
cd0ff491 314 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 315 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
316 macaddr[0] = (val >> 0) & 0xFF;
317 macaddr[1] = (val >> 8) & 0xFF;
318 macaddr[2] = (val >> 16) & 0xFF;
319 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 320 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
321 macaddr[4] = (val >> 0) & 0xFF;
322 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
323 memcpy(netdev->dev_addr, macaddr, 6);
324 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
325}
326
cd0ff491 327static inline void
3bf61c55
GFT
328jme_set_rx_pcc(struct jme_adapter *jme, int p)
329{
cd0ff491 330 switch (p) {
192570e0
GFT
331 case PCC_OFF:
332 jwrite32(jme, JME_PCCRX0,
333 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
334 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
335 break;
3bf61c55
GFT
336 case PCC_P1:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
341 case PCC_P2:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P3:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 default:
352 break;
353 }
192570e0 354 wmb();
3bf61c55 355
cd0ff491 356 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 357 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
358}
359
fcf45b4c 360static void
3bf61c55 361jme_start_irq(struct jme_adapter *jme)
d7699f87 362{
3bf61c55
GFT
363 register struct dynpcc_info *dpi = &(jme->dpi);
364
365 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
366 dpi->cur = PCC_P1;
367 dpi->attempt = PCC_P1;
368 dpi->cnt = 0;
369
370 jwrite32(jme, JME_PCCTX,
8c198884
GFT
371 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
372 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
373 PCCTXQ0_EN
374 );
375
d7699f87
GFT
376 /*
377 * Enable Interrupts
378 */
379 jwrite32(jme, JME_IENS, INTR_ENABLE);
380}
381
cd0ff491 382static inline void
3bf61c55 383jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
384{
385 /*
386 * Disable Interrupts
387 */
cd0ff491 388 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
389}
390
cd0ff491 391static u32
cdcdc9eb
GFT
392jme_linkstat_from_phy(struct jme_adapter *jme)
393{
cd0ff491 394 u32 phylink, bmsr;
cdcdc9eb
GFT
395
396 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
397 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 398 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
399 phylink |= PHY_LINK_AUTONEG_COMPLETE;
400
401 return phylink;
402}
403
cd0ff491 404static inline void
06168a20 405jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT
406{
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
408}
409
410static inline void
06168a20 411jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT
412{
413 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
414}
415
fcf45b4c
GFT
416static int
417jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
418{
419 struct jme_adapter *jme = netdev_priv(netdev);
ed830419 420 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 421 char linkmsg[64];
fcf45b4c 422 int rc = 0;
d7699f87 423
b3821cc5 424 linkmsg[0] = '\0';
cdcdc9eb 425
cd0ff491 426 if (jme->fpgaver)
cdcdc9eb
GFT
427 phylink = jme_linkstat_from_phy(jme);
428 else
429 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 430
cd0ff491
GFT
431 if (phylink & PHY_LINK_UP) {
432 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
433 /*
434 * If we did not enable AN
435 * Speed/Duplex Info should be obtained from SMI
436 */
437 phylink = PHY_LINK_UP;
438
439 bmcr = jme_mdio_read(jme->dev,
440 jme->mii_if.phy_id,
441 MII_BMCR);
442
443 phylink |= ((bmcr & BMCR_SPEED1000) &&
444 (bmcr & BMCR_SPEED100) == 0) ?
445 PHY_LINK_SPEED_1000M :
446 (bmcr & BMCR_SPEED100) ?
447 PHY_LINK_SPEED_100M :
448 PHY_LINK_SPEED_10M;
449
450 phylink |= (bmcr & BMCR_FULLDPLX) ?
451 PHY_LINK_DUPLEX : 0;
79ce639c 452
b3821cc5 453 strcat(linkmsg, "Forced: ");
cd0ff491 454 } else {
8c198884
GFT
455 /*
456 * Keep polling for speed/duplex resolve complete
457 */
cd0ff491 458 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
459 --cnt) {
460
461 udelay(1);
8c198884 462
cd0ff491 463 if (jme->fpgaver)
cdcdc9eb
GFT
464 phylink = jme_linkstat_from_phy(jme);
465 else
466 phylink = jread32(jme, JME_PHY_LINK);
8c198884 467 }
cd0ff491 468 if (!cnt)
52a46ba8 469 pr_err("Waiting speed resolve timeout\n");
79ce639c 470
b3821cc5 471 strcat(linkmsg, "ANed: ");
d7699f87
GFT
472 }
473
cd0ff491 474 if (jme->phylink == phylink) {
fcf45b4c
GFT
475 rc = 1;
476 goto out;
477 }
cd0ff491 478 if (testonly)
fcf45b4c
GFT
479 goto out;
480
481 jme->phylink = phylink;
482
ed830419
GFT
483 /*
484 * The speed/duplex setting of jme->reg_ghc already cleared
485 * by jme_reset_mac_processor()
486 */
cd0ff491
GFT
487 switch (phylink & PHY_LINK_SPEED_MASK) {
488 case PHY_LINK_SPEED_10M:
ed830419 489 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 490 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
491 break;
492 case PHY_LINK_SPEED_100M:
ed830419 493 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 494 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
495 break;
496 case PHY_LINK_SPEED_1000M:
ed830419 497 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 498 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
499 break;
500 default:
501 break;
d7699f87 502 }
d7699f87 503
cd0ff491 504 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 505 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
19bbc546 506 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
ed830419 507 jme->reg_ghc |= GHC_DPX;
cd0ff491 508 } else {
d7699f87 509 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
510 TXMCS_BACKOFF |
511 TXMCS_CARRIERSENSE |
512 TXMCS_COLLISION);
19bbc546 513 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 514 }
9b9d55de 515
ed830419
GFT
516 jwrite32(jme, JME_GHC, jme->reg_ghc);
517
9b9d55de 518 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
ed830419
GFT
519 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
520 GPREG1_RSSPATCH);
9b9d55de 521 if (!(phylink & PHY_LINK_DUPLEX))
ed830419 522 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
9b9d55de
GFT
523 switch (phylink & PHY_LINK_SPEED_MASK) {
524 case PHY_LINK_SPEED_10M:
06168a20 525 jme_set_phyfifo_8level(jme);
ed830419 526 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT
527 break;
528 case PHY_LINK_SPEED_100M:
06168a20 529 jme_set_phyfifo_5level(jme);
ed830419 530 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT
531 break;
532 case PHY_LINK_SPEED_1000M:
06168a20 533 jme_set_phyfifo_8level(jme);
9b9d55de
GFT
534 break;
535 default:
536 break;
537 }
538 }
ed830419 539 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 540
94c5ea02
GFT
541 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
542 "Full-Duplex, " :
543 "Half-Duplex, ");
544 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
545 "MDI-X" :
546 "MDI");
52a46ba8 547 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
548 netif_carrier_on(netdev);
549 } else {
550 if (testonly)
fcf45b4c
GFT
551 goto out;
552
52a46ba8 553 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 554 jme->phylink = 0;
cd0ff491 555 netif_carrier_off(netdev);
d7699f87 556 }
fcf45b4c
GFT
557
558out:
559 return rc;
d7699f87
GFT
560}
561
3bf61c55
GFT
562static int
563jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 564{
d7699f87
GFT
565 struct jme_ring *txring = &(jme->txring[0]);
566
567 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
568 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
569 &(txring->dmaalloc),
570 GFP_ATOMIC);
fcf45b4c 571
fa97b924
GFT
572 if (!txring->alloc)
573 goto err_set_null;
d7699f87
GFT
574
575 /*
576 * 16 Bytes align
577 */
cd0ff491 578 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 579 RING_DESC_ALIGN);
4330c2f2 580 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 581 txring->next_to_use = 0;
cdcdc9eb 582 atomic_set(&txring->next_to_clean, 0);
b3821cc5 583 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 584
fa97b924
GFT
585 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
586 jme->tx_ring_size, GFP_ATOMIC);
587 if (unlikely(!(txring->bufinf)))
588 goto err_free_txring;
589
d7699f87 590 /*
b3821cc5 591 * Initialize Transmit Descriptors
d7699f87 592 */
b3821cc5 593 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 594 memset(txring->bufinf, 0,
b3821cc5 595 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
596
597 return 0;
fa97b924
GFT
598
599err_free_txring:
600 dma_free_coherent(&(jme->pdev->dev),
601 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602 txring->alloc,
603 txring->dmaalloc);
604
605err_set_null:
606 txring->desc = NULL;
607 txring->dmaalloc = 0;
608 txring->dma = 0;
609 txring->bufinf = NULL;
610
611 return -ENOMEM;
d7699f87
GFT
612}
613
3bf61c55
GFT
614static void
615jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
616{
617 int i;
618 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 619 struct jme_buffer_info *txbi;
d7699f87 620
cd0ff491 621 if (txring->alloc) {
fa97b924
GFT
622 if (txring->bufinf) {
623 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624 txbi = txring->bufinf + i;
625 if (txbi->skb) {
626 dev_kfree_skb(txbi->skb);
627 txbi->skb = NULL;
628 }
629 txbi->mapping = 0;
630 txbi->len = 0;
631 txbi->nr_desc = 0;
632 txbi->start_xmit = 0;
d7699f87 633 }
fa97b924 634 kfree(txring->bufinf);
d7699f87
GFT
635 }
636
637 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 638 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
639 txring->alloc,
640 txring->dmaalloc);
3bf61c55
GFT
641
642 txring->alloc = NULL;
643 txring->desc = NULL;
644 txring->dmaalloc = 0;
645 txring->dma = 0;
fa97b924 646 txring->bufinf = NULL;
d7699f87 647 }
3bf61c55 648 txring->next_to_use = 0;
cdcdc9eb 649 atomic_set(&txring->next_to_clean, 0);
79ce639c 650 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
651}
652
cd0ff491 653static inline void
3bf61c55 654jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
655{
656 /*
657 * Select Queue 0
658 */
659 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 660 wmb();
d7699f87
GFT
661
662 /*
663 * Setup TX Queue 0 DMA Bass Address
664 */
fcf45b4c 665 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 666 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 667 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
668
669 /*
670 * Setup TX Descptor Count
671 */
b3821cc5 672 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
673
674 /*
675 * Enable TX Engine
676 */
677 wmb();
ed830419 678 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT
679 TXCS_SELECT_QUEUE0 |
680 TXCS_ENABLE);
d7699f87 681
ed830419
GFT
682 /*
683 * Start clock for TX MAC Processor
684 */
685 jme_mac_txclk_on(jme);
d7699f87
GFT
686}
687
cd0ff491 688static inline void
29bdd921
GFT
689jme_restart_tx_engine(struct jme_adapter *jme)
690{
691 /*
692 * Restart TX Engine
693 */
694 jwrite32(jme, JME_TXCS, jme->reg_txcs |
695 TXCS_SELECT_QUEUE0 |
696 TXCS_ENABLE);
697}
698
cd0ff491 699static inline void
3bf61c55 700jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
701{
702 int i;
cd0ff491 703 u32 val;
d7699f87
GFT
704
705 /*
706 * Disable TX Engine
707 */
fcf45b4c 708 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 709 wmb();
d7699f87
GFT
710
711 val = jread32(jme, JME_TXCS);
cd0ff491 712 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 713 mdelay(1);
d7699f87 714 val = jread32(jme, JME_TXCS);
cd0ff491 715 rmb();
d7699f87
GFT
716 }
717
cd0ff491 718 if (!i)
52a46ba8 719 pr_err("Disable TX engine timeout\n");
ed830419
GFT
720
721 /*
722 * Stop clock for TX MAC Processor
723 */
724 jme_mac_txclk_off(jme);
d7699f87
GFT
725}
726
3bf61c55
GFT
727static void
728jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 729{
fa97b924 730 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 731 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
732 struct jme_buffer_info *rxbi = rxring->bufinf;
733 rxdesc += i;
734 rxbi += i;
735
736 rxdesc->dw[0] = 0;
737 rxdesc->dw[1] = 0;
3bf61c55 738 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
739 rxdesc->desc1.bufaddrl = cpu_to_le32(
740 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 741 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 742 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 743 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 744 wmb();
3bf61c55 745 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
746}
747
3bf61c55
GFT
748static int
749jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
750{
751 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 752 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 753 struct sk_buff *skb;
52edb99a 754 dma_addr_t mapping;
4330c2f2 755
79ce639c
GFT
756 skb = netdev_alloc_skb(jme->dev,
757 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 758 if (unlikely(!skb))
4330c2f2 759 return -ENOMEM;
3bf61c55 760
52edb99a
GFT
761 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
762 offset_in_page(skb->data), skb_tailroom(skb),
763 PCI_DMA_FROMDEVICE);
764 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
765 dev_kfree_skb(skb);
766 return -ENOMEM;
767 }
768
769 if (likely(rxbi->mapping))
770 pci_unmap_page(jme->pdev, rxbi->mapping,
771 rxbi->len, PCI_DMA_FROMDEVICE);
772
4330c2f2 773 rxbi->skb = skb;
3bf61c55 774 rxbi->len = skb_tailroom(skb);
52edb99a 775 rxbi->mapping = mapping;
4330c2f2
GFT
776 return 0;
777}
778
3bf61c55
GFT
779static void
780jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
781{
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
784 rxbi += i;
785
cd0ff491 786 if (rxbi->skb) {
b3821cc5 787 pci_unmap_page(jme->pdev,
4330c2f2 788 rxbi->mapping,
3bf61c55 789 rxbi->len,
4330c2f2
GFT
790 PCI_DMA_FROMDEVICE);
791 dev_kfree_skb(rxbi->skb);
792 rxbi->skb = NULL;
793 rxbi->mapping = 0;
3bf61c55 794 rxbi->len = 0;
4330c2f2
GFT
795 }
796}
797
3bf61c55
GFT
798static void
799jme_free_rx_resources(struct jme_adapter *jme)
800{
801 int i;
802 struct jme_ring *rxring = &(jme->rxring[0]);
803
cd0ff491 804 if (rxring->alloc) {
fa97b924
GFT
805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
809 }
3bf61c55
GFT
810
811 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
813 rxring->alloc,
814 rxring->dmaalloc);
815 rxring->alloc = NULL;
816 rxring->desc = NULL;
817 rxring->dmaalloc = 0;
818 rxring->dma = 0;
fa97b924 819 rxring->bufinf = NULL;
3bf61c55
GFT
820 }
821 rxring->next_to_use = 0;
cdcdc9eb 822 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
823}
824
825static int
826jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
827{
828 int i;
829 struct jme_ring *rxring = &(jme->rxring[0]);
830
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
833 &(rxring->dmaalloc),
834 GFP_ATOMIC);
fa97b924
GFT
835 if (!rxring->alloc)
836 goto err_set_null;
d7699f87
GFT
837
838 /*
839 * 16 Bytes align
840 */
cd0ff491 841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 842 RING_DESC_ALIGN);
4330c2f2 843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 844 rxring->next_to_use = 0;
cdcdc9eb 845 atomic_set(&rxring->next_to_clean, 0);
d7699f87 846
fa97b924
GFT
847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
851
d7699f87
GFT
852 /*
853 * Initiallize Receive Descriptors
854 */
fa97b924
GFT
855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
859 jme_free_rx_resources(jme);
860 return -ENOMEM;
861 }
d7699f87
GFT
862
863 jme_set_clean_rxdesc(jme, i);
864 }
865
d7699f87 866 return 0;
fa97b924
GFT
867
868err_free_rxring:
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871 rxring->alloc,
872 rxring->dmaalloc);
873err_set_null:
874 rxring->desc = NULL;
875 rxring->dmaalloc = 0;
876 rxring->dma = 0;
877 rxring->bufinf = NULL;
878
879 return -ENOMEM;
d7699f87
GFT
880}
881
cd0ff491 882static inline void
3bf61c55 883jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 884{
cd0ff491
GFT
885 /*
886 * Select Queue 0
887 */
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889 RXCS_QUEUESEL_Q0);
890 wmb();
891
d7699f87
GFT
892 /*
893 * Setup RX DMA Bass Address
894 */
fa97b924 895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
898
899 /*
b3821cc5 900 * Setup RX Descriptor Count
d7699f87 901 */
b3821cc5 902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 903
3bf61c55 904 /*
d7699f87
GFT
905 * Setup Unicast Filter
906 */
bb4c5c8c 907 jme_set_unicastaddr(jme->dev);
d7699f87
GFT
908 jme_set_multi(jme->dev);
909
910 /*
911 * Enable RX Engine
912 */
913 wmb();
ed830419 914 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
915 RXCS_QUEUESEL_Q0 |
916 RXCS_ENABLE |
917 RXCS_QST);
ed830419
GFT
918
919 /*
920 * Start clock for RX MAC Processor
921 */
922 jme_mac_rxclk_on(jme);
d7699f87
GFT
923}
924
cd0ff491 925static inline void
3bf61c55 926jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
927{
928 /*
3bf61c55 929 * Start RX Engine
4330c2f2 930 */
79ce639c 931 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
932 RXCS_QUEUESEL_Q0 |
933 RXCS_ENABLE |
934 RXCS_QST);
935}
936
cd0ff491 937static inline void
3bf61c55 938jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
939{
940 int i;
cd0ff491 941 u32 val;
d7699f87
GFT
942
943 /*
944 * Disable RX Engine
945 */
29bdd921 946 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 947 wmb();
d7699f87
GFT
948
949 val = jread32(jme, JME_RXCS);
cd0ff491 950 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 951 mdelay(1);
d7699f87 952 val = jread32(jme, JME_RXCS);
cd0ff491 953 rmb();
d7699f87
GFT
954 }
955
cd0ff491 956 if (!i)
52a46ba8 957 pr_err("Disable RX engine timeout\n");
d7699f87 958
ed830419
GFT
959 /*
960 * Stop clock for RX MAC Processor
961 */
962 jme_mac_rxclk_off(jme);
d7699f87
GFT
963}
964
a452eef1
GFT
965static u16
966jme_udpsum(struct sk_buff *skb)
967{
968 u16 csum = 0xFFFFu;
969
970 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
971 return csum;
972 if (skb->protocol != htons(ETH_P_IP))
973 return csum;
974 skb_set_network_header(skb, ETH_HLEN);
975 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
976 (skb->len < (ETH_HLEN +
977 (ip_hdr(skb)->ihl << 2) +
978 sizeof(struct udphdr)))) {
979 skb_reset_network_header(skb);
980 return csum;
981 }
982 skb_set_transport_header(skb,
983 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
984 csum = udp_hdr(skb)->check;
985 skb_reset_transport_header(skb);
986 skb_reset_network_header(skb);
987
988 return csum;
989}
990
192570e0 991static int
a452eef1 992jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 993{
cd0ff491 994 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
995 return false;
996
fa97b924
GFT
997 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
998 == RXWBFLAG_TCPON)) {
999 if (flags & RXWBFLAG_IPV4)
c97b5740 1000 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 1001 return false;
192570e0
GFT
1002 }
1003
fa97b924 1004 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
a452eef1 1005 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
fa97b924 1006 if (flags & RXWBFLAG_IPV4)
52a46ba8 1007 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
fa97b924 1008 return false;
192570e0
GFT
1009 }
1010
fa97b924
GFT
1011 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1012 == RXWBFLAG_IPV4)) {
52a46ba8 1013 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
fa97b924 1014 return false;
192570e0
GFT
1015 }
1016
1017 return true;
1018}
1019
3bf61c55 1020static void
42b1055e 1021jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1022{
d7699f87 1023 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1024 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1025 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1026 struct sk_buff *skb;
3bf61c55 1027 int framesize;
d7699f87 1028
3bf61c55
GFT
1029 rxdesc += idx;
1030 rxbi += idx;
d7699f87 1031
3bf61c55
GFT
1032 skb = rxbi->skb;
1033 pci_dma_sync_single_for_cpu(jme->pdev,
1034 rxbi->mapping,
1035 rxbi->len,
1036 PCI_DMA_FROMDEVICE);
1037
cd0ff491 1038 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
1039 pci_dma_sync_single_for_device(jme->pdev,
1040 rxbi->mapping,
1041 rxbi->len,
1042 PCI_DMA_FROMDEVICE);
1043
1044 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1045 } else {
3bf61c55
GFT
1046 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1047 - RX_PREPAD_SIZE;
1048
1049 skb_reserve(skb, RX_PREPAD_SIZE);
1050 skb_put(skb, framesize);
1051 skb->protocol = eth_type_trans(skb, jme->dev);
1052
a452eef1 1053 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1054 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1055 else
97984ab7 1056 skb_checksum_none_assert(skb);
8c198884 1057
94c5ea02 1058 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
202bd32d
JP
1059 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1060
1061 __vlan_hwaccel_put_tag(skb, vid);
1062 NET_STAT(jme).rx_bytes += 4;
b3821cc5 1063 }
202bd32d 1064 jme->jme_rx(skb);
3bf61c55 1065
94c5ea02
GFT
1066 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1067 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
1068 ++(NET_STAT(jme).multicast);
1069
3bf61c55
GFT
1070 NET_STAT(jme).rx_bytes += framesize;
1071 ++(NET_STAT(jme).rx_packets);
1072 }
1073
1074 jme_set_clean_rxdesc(jme, idx);
1075
1076}
1077
1078static int
1079jme_process_receive(struct jme_adapter *jme, int limit)
1080{
1081 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1082 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1083 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1084
cd0ff491 1085 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
1086 goto out_inc;
1087
cd0ff491 1088 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
1089 goto out_inc;
1090
cd0ff491 1091 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
1092 goto out_inc;
1093
cdcdc9eb 1094 i = atomic_read(&rxring->next_to_clean);
fa97b924 1095 while (limit > 0) {
3bf61c55
GFT
1096 rxdesc = rxring->desc;
1097 rxdesc += i;
1098
94c5ea02 1099 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
1100 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1101 goto out;
fa97b924 1102 --limit;
d7699f87 1103
1a7a122d 1104 rmb();
4330c2f2
GFT
1105 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1106
cd0ff491 1107 if (unlikely(desccnt > 1 ||
192570e0 1108 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1109
cd0ff491 1110 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1111 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1112 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1113 ++(NET_STAT(jme).rx_fifo_errors);
1114 else
1115 ++(NET_STAT(jme).rx_errors);
4330c2f2 1116
cd0ff491 1117 if (desccnt > 1)
3bf61c55 1118 limit -= desccnt - 1;
4330c2f2 1119
cd0ff491 1120 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1121 jme_set_clean_rxdesc(jme, j);
b3821cc5 1122 j = (j + 1) & (mask);
4330c2f2 1123 }
3bf61c55 1124
cd0ff491 1125 } else {
42b1055e 1126 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1127 }
4330c2f2 1128
b3821cc5 1129 i = (i + desccnt) & (mask);
3bf61c55 1130 }
4330c2f2 1131
3bf61c55 1132out:
cdcdc9eb 1133 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1134
192570e0
GFT
1135out_inc:
1136 atomic_inc(&jme->rx_cleaning);
1137
3bf61c55 1138 return limit > 0 ? limit : 0;
4330c2f2 1139
3bf61c55 1140}
d7699f87 1141
79ce639c
GFT
1142static void
1143jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1144{
cd0ff491 1145 if (likely(atmp == dpi->cur)) {
192570e0 1146 dpi->cnt = 0;
79ce639c 1147 return;
192570e0 1148 }
79ce639c 1149
cd0ff491 1150 if (dpi->attempt == atmp) {
79ce639c 1151 ++(dpi->cnt);
cd0ff491 1152 } else {
79ce639c
GFT
1153 dpi->attempt = atmp;
1154 dpi->cnt = 0;
1155 }
1156
1157}
1158
1159static void
1160jme_dynamic_pcc(struct jme_adapter *jme)
1161{
1162 register struct dynpcc_info *dpi = &(jme->dpi);
1163
cd0ff491 1164 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1165 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT
1166 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1167 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1168 jme_attempt_pcc(dpi, PCC_P2);
1169 else
1170 jme_attempt_pcc(dpi, PCC_P1);
1171
cd0ff491
GFT
1172 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1173 if (dpi->attempt < dpi->cur)
1174 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1175 jme_set_rx_pcc(jme, dpi->attempt);
1176 dpi->cur = dpi->attempt;
1177 dpi->cnt = 0;
1178 }
1179}
1180
1181static void
1182jme_start_pcc_timer(struct jme_adapter *jme)
1183{
1184 struct dynpcc_info *dpi = &(jme->dpi);
1185 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1186 dpi->last_pkts = NET_STAT(jme).rx_packets;
1187 dpi->intr_cnt = 0;
1188 jwrite32(jme, JME_TMCSR,
1189 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1190}
1191
cd0ff491 1192static inline void
29bdd921
GFT
1193jme_stop_pcc_timer(struct jme_adapter *jme)
1194{
1195 jwrite32(jme, JME_TMCSR, 0);
1196}
1197
cd0ff491
GFT
1198static void
1199jme_shutdown_nic(struct jme_adapter *jme)
1200{
1201 u32 phylink;
1202
1203 phylink = jme_linkstat_from_phy(jme);
1204
1205 if (!(phylink & PHY_LINK_UP)) {
1206 /*
1207 * Disable all interrupt before issue timer
1208 */
1209 jme_stop_irq(jme);
1210 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1211 }
1212}
1213
79ce639c
GFT
1214static void
1215jme_pcc_tasklet(unsigned long arg)
1216{
cd0ff491 1217 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1218 struct net_device *netdev = jme->dev;
1219
cd0ff491
GFT
1220 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1221 jme_shutdown_nic(jme);
1222 return;
1223 }
29bdd921 1224
cd0ff491 1225 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1226 (atomic_read(&jme->link_changing) != 1)
1227 )) {
1228 jme_stop_pcc_timer(jme);
79ce639c
GFT
1229 return;
1230 }
29bdd921 1231
cd0ff491 1232 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1233 jme_dynamic_pcc(jme);
1234
79ce639c
GFT
1235 jme_start_pcc_timer(jme);
1236}
1237
cd0ff491 1238static inline void
192570e0
GFT
1239jme_polling_mode(struct jme_adapter *jme)
1240{
1241 jme_set_rx_pcc(jme, PCC_OFF);
1242}
1243
cd0ff491 1244static inline void
192570e0
GFT
1245jme_interrupt_mode(struct jme_adapter *jme)
1246{
1247 jme_set_rx_pcc(jme, PCC_P1);
1248}
1249
cd0ff491
GFT
1250static inline int
1251jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1252{
1253 u32 apmc;
1254 apmc = jread32(jme, JME_APMC);
1255 return apmc & JME_APMC_PSEUDO_HP_EN;
1256}
1257
1258static void
1259jme_start_shutdown_timer(struct jme_adapter *jme)
1260{
1261 u32 apmc;
1262
1263 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1264 apmc &= ~JME_APMC_EPIEN_CTRL;
1265 if (!no_extplug) {
1266 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1267 wmb();
1268 }
1269 jwrite32f(jme, JME_APMC, apmc);
1270
1271 jwrite32f(jme, JME_TIMER2, 0);
1272 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1273 jwrite32(jme, JME_TMCSR,
1274 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1275}
1276
1277static void
1278jme_stop_shutdown_timer(struct jme_adapter *jme)
1279{
1280 u32 apmc;
1281
1282 jwrite32f(jme, JME_TMCSR, 0);
1283 jwrite32f(jme, JME_TIMER2, 0);
1284 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1285
1286 apmc = jread32(jme, JME_APMC);
1287 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1288 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1289 wmb();
1290 jwrite32f(jme, JME_APMC, apmc);
1291}
1292
3bf61c55
GFT
1293static void
1294jme_link_change_tasklet(unsigned long arg)
1295{
cd0ff491 1296 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1297 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1298 int rc;
1299
cd0ff491
GFT
1300 while (!atomic_dec_and_test(&jme->link_changing)) {
1301 atomic_inc(&jme->link_changing);
52a46ba8 1302 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
e882564f 1303 while (atomic_read(&jme->link_changing) != 1)
52a46ba8 1304 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1305 }
fcf45b4c 1306
cd0ff491 1307 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1308 goto out;
1309
29bdd921 1310 jme->old_mtu = netdev->mtu;
fcf45b4c 1311 netif_stop_queue(netdev);
cd0ff491
GFT
1312 if (jme_pseudo_hotplug_enabled(jme))
1313 jme_stop_shutdown_timer(jme);
1314
1315 jme_stop_pcc_timer(jme);
1316 tasklet_disable(&jme->txclean_task);
1317 tasklet_disable(&jme->rxclean_task);
1318 tasklet_disable(&jme->rxempty_task);
1319
1320 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT
1321 jme_disable_rx_engine(jme);
1322 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1323 jme_reset_mac_processor(jme);
1324 jme_free_rx_resources(jme);
1325 jme_free_tx_resources(jme);
192570e0 1326
cd0ff491 1327 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1328 jme_polling_mode(jme);
cd0ff491
GFT
1329
1330 netif_carrier_off(netdev);
fcf45b4c
GFT
1331 }
1332
1333 jme_check_link(netdev, 0);
cd0ff491 1334 if (netif_carrier_ok(netdev)) {
fcf45b4c 1335 rc = jme_setup_rx_resources(jme);
cd0ff491 1336 if (rc) {
52a46ba8 1337 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1338 goto out_enable_tasklet;
fcf45b4c
GFT
1339 }
1340
fcf45b4c 1341 rc = jme_setup_tx_resources(jme);
cd0ff491 1342 if (rc) {
52a46ba8 1343 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1344 goto err_out_free_rx_resources;
1345 }
1346
1347 jme_enable_rx_engine(jme);
1348 jme_enable_tx_engine(jme);
1349
1350 netif_start_queue(netdev);
192570e0 1351
cd0ff491 1352 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1353 jme_interrupt_mode(jme);
192570e0 1354
79ce639c 1355 jme_start_pcc_timer(jme);
cd0ff491
GFT
1356 } else if (jme_pseudo_hotplug_enabled(jme)) {
1357 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1358 }
1359
cd0ff491 1360 goto out_enable_tasklet;
fcf45b4c
GFT
1361
1362err_out_free_rx_resources:
1363 jme_free_rx_resources(jme);
cd0ff491
GFT
1364out_enable_tasklet:
1365 tasklet_enable(&jme->txclean_task);
1366 tasklet_hi_enable(&jme->rxclean_task);
1367 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1368out:
1369 atomic_inc(&jme->link_changing);
3bf61c55 1370}
d7699f87 1371
3bf61c55
GFT
1372static void
1373jme_rx_clean_tasklet(unsigned long arg)
1374{
cd0ff491 1375 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1376 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1377
192570e0
GFT
1378 jme_process_receive(jme, jme->rx_ring_size);
1379 ++(dpi->intr_cnt);
42b1055e 1380
192570e0 1381}
fcf45b4c 1382
192570e0 1383static int
cdcdc9eb 1384jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1385{
cdcdc9eb 1386 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1387 int rest;
fcf45b4c 1388
cdcdc9eb 1389 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1390
cd0ff491 1391 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1392 atomic_dec(&jme->rx_empty);
192570e0
GFT
1393 ++(NET_STAT(jme).rx_dropped);
1394 jme_restart_rx_engine(jme);
1395 }
1396 atomic_inc(&jme->rx_empty);
1397
cd0ff491 1398 if (rest) {
cdcdc9eb 1399 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1400 jme_interrupt_mode(jme);
1401 }
1402
cdcdc9eb
GFT
1403 JME_NAPI_WEIGHT_SET(budget, rest);
1404 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1405}
1406
1407static void
1408jme_rx_empty_tasklet(unsigned long arg)
1409{
cd0ff491 1410 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1411
cd0ff491 1412 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1413 return;
1414
cd0ff491 1415 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1416 return;
1417
c97b5740 1418 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1419
fcf45b4c 1420 jme_rx_clean_tasklet(arg);
cdcdc9eb 1421
cd0ff491 1422 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1423 atomic_dec(&jme->rx_empty);
1424 ++(NET_STAT(jme).rx_dropped);
1425 jme_restart_rx_engine(jme);
1426 }
1427 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1428}
1429
b3821cc5
GFT
1430static void
1431jme_wake_queue_if_stopped(struct jme_adapter *jme)
1432{
fa97b924 1433 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1434
1435 smp_wmb();
cd0ff491 1436 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1437 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
52a46ba8 1438 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1439 netif_wake_queue(jme->dev);
b3821cc5
GFT
1440 }
1441
1442}
1443
3bf61c55
GFT
1444static void
1445jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1446{
cd0ff491 1447 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1448 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1449 struct txdesc *txdesc = txring->desc;
3bf61c55 1450 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1451 int i, j, cnt = 0, max, err, mask;
3bf61c55 1452
52a46ba8 1453 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1454
1455 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1456 goto out;
1457
cd0ff491 1458 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1459 goto out;
1460
cd0ff491 1461 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1462 goto out;
1463
b3821cc5
GFT
1464 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1465 mask = jme->tx_ring_mask;
3bf61c55 1466
cd0ff491 1467 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1468
1469 ctxbi = txbi + i;
1470
cd0ff491 1471 if (likely(ctxbi->skb &&
b3821cc5 1472 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1473
cd0ff491 1474 tx_dbg(jme, "txclean: %d+%d@%lu\n",
52a46ba8 1475 i, ctxbi->nr_desc, jiffies);
3bf61c55 1476
cd0ff491 1477 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1478
cd0ff491 1479 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1480 ttxbi = txbi + ((i + j) & (mask));
1481 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1482
b3821cc5 1483 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1484 ttxbi->mapping,
1485 ttxbi->len,
1486 PCI_DMA_TODEVICE);
1487
3bf61c55
GFT
1488 ttxbi->mapping = 0;
1489 ttxbi->len = 0;
1490 }
1491
1492 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1493
1494 cnt += ctxbi->nr_desc;
1495
cd0ff491 1496 if (unlikely(err)) {
8c198884 1497 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1498 } else {
8c198884 1499 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1500 NET_STAT(jme).tx_bytes += ctxbi->len;
1501 }
1502
1503 ctxbi->skb = NULL;
1504 ctxbi->len = 0;
cdcdc9eb 1505 ctxbi->start_xmit = 0;
cd0ff491
GFT
1506
1507 } else {
3bf61c55
GFT
1508 break;
1509 }
1510
b3821cc5 1511 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1512
1513 ctxbi->nr_desc = 0;
d7699f87
GFT
1514 }
1515
52a46ba8 1516 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1517 atomic_set(&txring->next_to_clean, i);
79ce639c 1518 atomic_add(cnt, &txring->nr_free);
3bf61c55 1519
b3821cc5
GFT
1520 jme_wake_queue_if_stopped(jme);
1521
fcf45b4c
GFT
1522out:
1523 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1524}
1525
79ce639c 1526static void
cd0ff491 1527jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1528{
3bf61c55
GFT
1529 /*
1530 * Disable interrupt
1531 */
1532 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1533
cd0ff491 1534 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1535 /*
1536 * Link change event is critical
1537 * all other events are ignored
1538 */
1539 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1540 tasklet_schedule(&jme->linkch_task);
29bdd921 1541 goto out_reenable;
fcf45b4c 1542 }
d7699f87 1543
cd0ff491 1544 if (intrstat & INTR_TMINTR) {
47220951 1545 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1546 tasklet_schedule(&jme->pcc_task);
47220951 1547 }
79ce639c 1548
cd0ff491 1549 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1550 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1551 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1552 }
1553
cd0ff491 1554 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1555 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1556 INTR_PCCRX0 |
1557 INTR_RX0EMP)) |
1558 INTR_RX0);
1559 }
d7699f87 1560
cd0ff491
GFT
1561 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1562 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1563 atomic_inc(&jme->rx_empty);
1564
cd0ff491
GFT
1565 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1566 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1567 jme_polling_mode(jme);
cdcdc9eb 1568 JME_RX_SCHEDULE(jme);
192570e0
GFT
1569 }
1570 }
cd0ff491
GFT
1571 } else {
1572 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1573 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1574 tasklet_hi_schedule(&jme->rxempty_task);
1575 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1576 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1577 }
4330c2f2 1578 }
d7699f87 1579
29bdd921 1580out_reenable:
3bf61c55 1581 /*
fcf45b4c 1582 * Re-enable interrupt
3bf61c55 1583 */
fcf45b4c 1584 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1585}
1586
1587static irqreturn_t
1588jme_intr(int irq, void *dev_id)
1589{
cd0ff491
GFT
1590 struct net_device *netdev = dev_id;
1591 struct jme_adapter *jme = netdev_priv(netdev);
1592 u32 intrstat;
79ce639c
GFT
1593
1594 intrstat = jread32(jme, JME_IEVE);
1595
1596 /*
1597 * Check if it's really an interrupt for us
1598 */
9b9d55de 1599 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1600 return IRQ_NONE;
79ce639c
GFT
1601
1602 /*
1603 * Check if the device still exist
1604 */
cd0ff491
GFT
1605 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1606 return IRQ_NONE;
79ce639c
GFT
1607
1608 jme_intr_msi(jme, intrstat);
1609
cd0ff491 1610 return IRQ_HANDLED;
d7699f87
GFT
1611}
1612
79ce639c
GFT
1613static irqreturn_t
1614jme_msi(int irq, void *dev_id)
1615{
cd0ff491
GFT
1616 struct net_device *netdev = dev_id;
1617 struct jme_adapter *jme = netdev_priv(netdev);
1618 u32 intrstat;
79ce639c 1619
fa97b924 1620 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1621
1622 jme_intr_msi(jme, intrstat);
1623
cd0ff491 1624 return IRQ_HANDLED;
79ce639c
GFT
1625}
1626
79ce639c
GFT
1627static void
1628jme_reset_link(struct jme_adapter *jme)
1629{
1630 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1631}
1632
fcf45b4c
GFT
1633static void
1634jme_restart_an(struct jme_adapter *jme)
1635{
cd0ff491 1636 u32 bmcr;
fcf45b4c 1637
cd0ff491 1638 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1639 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1640 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1641 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1642 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1643}
1644
1645static int
1646jme_request_irq(struct jme_adapter *jme)
1647{
1648 int rc;
cd0ff491
GFT
1649 struct net_device *netdev = jme->dev;
1650 irq_handler_t handler = jme_intr;
1651 int irq_flags = IRQF_SHARED;
1652
1653 if (!pci_enable_msi(jme->pdev)) {
1654 set_bit(JME_FLAG_MSI, &jme->flags);
1655 handler = jme_msi;
1656 irq_flags = 0;
1657 }
1658
1659 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1660 netdev);
1661 if (rc) {
52a46ba8
JP
1662 netdev_err(netdev,
1663 "Unable to request %s interrupt (return: %d)\n",
1664 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1665 rc);
79ce639c 1666
cd0ff491
GFT
1667 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1668 pci_disable_msi(jme->pdev);
1669 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1670 }
cd0ff491 1671 } else {
79ce639c
GFT
1672 netdev->irq = jme->pdev->irq;
1673 }
1674
cd0ff491 1675 return rc;
79ce639c
GFT
1676}
1677
1678static void
1679jme_free_irq(struct jme_adapter *jme)
1680{
cd0ff491
GFT
1681 free_irq(jme->pdev->irq, jme->dev);
1682 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1683 pci_disable_msi(jme->pdev);
1684 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1685 jme->dev->irq = jme->pdev->irq;
cd0ff491 1686 }
fcf45b4c
GFT
1687}
1688
e4610a83
GFT
1689static inline void
1690jme_new_phy_on(struct jme_adapter *jme)
1691{
1692 u32 reg;
1693
1694 reg = jread32(jme, JME_PHY_PWR);
1695 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1696 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1697 jwrite32(jme, JME_PHY_PWR, reg);
1698
1699 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1700 reg &= ~PE1_GPREG0_PBG;
1701 reg |= PE1_GPREG0_ENBG;
1702 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1703}
1704
1705static inline void
1706jme_new_phy_off(struct jme_adapter *jme)
1707{
1708 u32 reg;
1709
1710 reg = jread32(jme, JME_PHY_PWR);
1711 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1712 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1713 jwrite32(jme, JME_PHY_PWR, reg);
1714
1715 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1716 reg &= ~PE1_GPREG0_PBG;
1717 reg |= PE1_GPREG0_PDD3COLD;
1718 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1719}
1720
48db98f7
GFT
1721static inline void
1722jme_phy_on(struct jme_adapter *jme)
1723{
1724 u32 bmcr;
1725
1726 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1727 bmcr &= ~BMCR_PDOWN;
1728 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
e4610a83
GFT
1729
1730 if (new_phy_power_ctrl(jme->chip_main_rev))
1731 jme_new_phy_on(jme);
1732}
1733
1734static inline void
1735jme_phy_off(struct jme_adapter *jme)
1736{
1737 u32 bmcr;
1738
1739 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1740 bmcr |= BMCR_PDOWN;
1741 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1742
1743 if (new_phy_power_ctrl(jme->chip_main_rev))
1744 jme_new_phy_off(jme);
48db98f7
GFT
1745}
1746
3bf61c55
GFT
1747static int
1748jme_open(struct net_device *netdev)
d7699f87
GFT
1749{
1750 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1751 int rc;
79ce639c 1752
42b1055e 1753 jme_clear_pm(jme);
cdcdc9eb 1754 JME_NAPI_ENABLE(jme);
d7699f87 1755
fa97b924 1756 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1757 tasklet_enable(&jme->txclean_task);
1758 tasklet_hi_enable(&jme->rxclean_task);
1759 tasklet_hi_enable(&jme->rxempty_task);
1760
79ce639c 1761 rc = jme_request_irq(jme);
cd0ff491 1762 if (rc)
4330c2f2 1763 goto err_out;
79ce639c 1764
d7699f87 1765 jme_start_irq(jme);
42b1055e 1766
e4610a83
GFT
1767 jme_phy_on(jme);
1768 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1769 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 1770 else
42b1055e
GFT
1771 jme_reset_phy_processor(jme);
1772
29bdd921 1773 jme_reset_link(jme);
d7699f87
GFT
1774
1775 return 0;
1776
d7699f87
GFT
1777err_out:
1778 netif_stop_queue(netdev);
1779 netif_carrier_off(netdev);
4330c2f2 1780 return rc;
d7699f87
GFT
1781}
1782
42b1055e
GFT
1783static void
1784jme_set_100m_half(struct jme_adapter *jme)
1785{
cd0ff491 1786 u32 bmcr, tmp;
42b1055e 1787
fba4bc0c 1788 jme_phy_on(jme);
42b1055e
GFT
1789 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1790 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1791 BMCR_SPEED1000 | BMCR_FULLDPLX);
1792 tmp |= BMCR_SPEED100;
1793
1794 if (bmcr != tmp)
1795 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1796
cd0ff491 1797 if (jme->fpgaver)
cdcdc9eb
GFT
1798 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1799 else
1800 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1801}
1802
47220951
GFT
1803#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1804static void
1805jme_wait_link(struct jme_adapter *jme)
1806{
cd0ff491 1807 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1808
1809 mdelay(1000);
1810 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1811 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1812 mdelay(10);
1813 phylink = jme_linkstat_from_phy(jme);
1814 }
1815}
1816
fba4bc0c
GFT
1817static void
1818jme_powersave_phy(struct jme_adapter *jme)
1819{
1820 if (jme->reg_pmcs) {
1821 jme_set_100m_half(jme);
fba4bc0c
GFT
1822 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1823 jme_wait_link(jme);
18783c49 1824 jme_clear_pm(jme);
fba4bc0c
GFT
1825 } else {
1826 jme_phy_off(jme);
1827 }
1828}
1829
3bf61c55
GFT
1830static int
1831jme_close(struct net_device *netdev)
d7699f87
GFT
1832{
1833 struct jme_adapter *jme = netdev_priv(netdev);
1834
1835 netif_stop_queue(netdev);
1836 netif_carrier_off(netdev);
1837
1838 jme_stop_irq(jme);
79ce639c 1839 jme_free_irq(jme);
d7699f87 1840
cdcdc9eb 1841 JME_NAPI_DISABLE(jme);
192570e0 1842
fa97b924
GFT
1843 tasklet_disable(&jme->linkch_task);
1844 tasklet_disable(&jme->txclean_task);
1845 tasklet_disable(&jme->rxclean_task);
1846 tasklet_disable(&jme->rxempty_task);
8c198884 1847
cd0ff491
GFT
1848 jme_disable_rx_engine(jme);
1849 jme_disable_tx_engine(jme);
8c198884 1850 jme_reset_mac_processor(jme);
d7699f87
GFT
1851 jme_free_rx_resources(jme);
1852 jme_free_tx_resources(jme);
42b1055e 1853 jme->phylink = 0;
b3821cc5
GFT
1854 jme_phy_off(jme);
1855
1856 return 0;
1857}
1858
1859static int
1860jme_alloc_txdesc(struct jme_adapter *jme,
1861 struct sk_buff *skb)
1862{
fa97b924 1863 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1864 int idx, nr_alloc, mask = jme->tx_ring_mask;
1865
1866 idx = txring->next_to_use;
1867 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1868
cd0ff491 1869 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1870 return -1;
1871
1872 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1873
b3821cc5
GFT
1874 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1875
1876 return idx;
1877}
1878
1879static void
1880jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1881 struct txdesc *txdesc,
b3821cc5
GFT
1882 struct jme_buffer_info *txbi,
1883 struct page *page,
cd0ff491
GFT
1884 u32 page_offset,
1885 u32 len,
1886 u8 hidma)
b3821cc5
GFT
1887{
1888 dma_addr_t dmaaddr;
1889
1890 dmaaddr = pci_map_page(pdev,
1891 page,
1892 page_offset,
1893 len,
1894 PCI_DMA_TODEVICE);
1895
1896 pci_dma_sync_single_for_device(pdev,
1897 dmaaddr,
1898 len,
1899 PCI_DMA_TODEVICE);
1900
1901 txdesc->dw[0] = 0;
1902 txdesc->dw[1] = 0;
1903 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1904 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1905 txdesc->desc2.datalen = cpu_to_le16(len);
1906 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1907 txdesc->desc2.bufaddrl = cpu_to_le32(
1908 (__u64)dmaaddr & 0xFFFFFFFFUL);
1909
1910 txbi->mapping = dmaaddr;
1911 txbi->len = len;
1912}
1913
1914static void
1915jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1916{
fa97b924 1917 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1918 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1919 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1920 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1921 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1922 int mask = jme->tx_ring_mask;
1923 struct skb_frag_struct *frag;
cd0ff491 1924 u32 len;
b3821cc5 1925
cd0ff491
GFT
1926 for (i = 0 ; i < nr_frags ; ++i) {
1927 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1928 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1929 ctxbi = txbi + ((idx + i + 2) & (mask));
1930
608a9fae
IC
1931 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
1932 skb_frag_page(frag),
1933 frag->page_offset, frag->size, hidma);
42b1055e 1934 }
b3821cc5 1935
cd0ff491 1936 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1937 ctxdesc = txdesc + ((idx + 1) & (mask));
1938 ctxbi = txbi + ((idx + 1) & (mask));
1939 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1940 offset_in_page(skb->data), len, hidma);
1941
1942}
1943
1944static int
1945jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1946{
cd0ff491 1947 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT
1948 skb_header_cloned(skb) &&
1949 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1950 dev_kfree_skb(skb);
1951 return -1;
1952 }
1953
1954 return 0;
1955}
1956
1957static int
94c5ea02 1958jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1959{
94c5ea02 1960 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1961 if (*mss) {
b3821cc5
GFT
1962 *flags |= TXFLAG_LSEN;
1963
cd0ff491 1964 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1965 struct iphdr *iph = ip_hdr(skb);
1966
1967 iph->check = 0;
cd0ff491 1968 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1969 iph->daddr, 0,
1970 IPPROTO_TCP,
1971 0);
cd0ff491 1972 } else {
b3821cc5
GFT
1973 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1974
cd0ff491 1975 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1976 &ip6h->daddr, 0,
1977 IPPROTO_TCP,
1978 0);
1979 }
1980
1981 return 0;
1982 }
1983
1984 return 1;
1985}
1986
1987static void
cd0ff491 1988jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1989{
cd0ff491
GFT
1990 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1991 u8 ip_proto;
b3821cc5
GFT
1992
1993 switch (skb->protocol) {
cd0ff491 1994 case htons(ETH_P_IP):
b3821cc5
GFT
1995 ip_proto = ip_hdr(skb)->protocol;
1996 break;
cd0ff491 1997 case htons(ETH_P_IPV6):
b3821cc5
GFT
1998 ip_proto = ipv6_hdr(skb)->nexthdr;
1999 break;
2000 default:
2001 ip_proto = 0;
2002 break;
2003 }
2004
cd0ff491 2005 switch (ip_proto) {
b3821cc5
GFT
2006 case IPPROTO_TCP:
2007 *flags |= TXFLAG_TCPCS;
2008 break;
2009 case IPPROTO_UDP:
2010 *flags |= TXFLAG_UDPCS;
2011 break;
2012 default:
52a46ba8 2013 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
2014 break;
2015 }
2016 }
2017}
2018
cd0ff491 2019static inline void
94c5ea02 2020jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2021{
cd0ff491 2022 if (vlan_tx_tag_present(skb)) {
b3821cc5 2023 *flags |= TXFLAG_TAGON;
94c5ea02 2024 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2025 }
b3821cc5
GFT
2026}
2027
2028static int
94c5ea02 2029jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2030{
fa97b924 2031 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2032 struct txdesc *txdesc;
b3821cc5 2033 struct jme_buffer_info *txbi;
cd0ff491 2034 u8 flags;
b3821cc5 2035
cd0ff491 2036 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
2037 txbi = txring->bufinf + idx;
2038
2039 txdesc->dw[0] = 0;
2040 txdesc->dw[1] = 0;
2041 txdesc->dw[2] = 0;
2042 txdesc->dw[3] = 0;
2043 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2044 /*
2045 * Set OWN bit at final.
2046 * When kernel transmit faster than NIC.
2047 * And NIC trying to send this descriptor before we tell
2048 * it to start sending this TX queue.
2049 * Other fields are already filled correctly.
2050 */
2051 wmb();
2052 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
2053 /*
2054 * Set checksum flags while not tso
2055 */
2056 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2057 jme_tx_csum(jme, skb, &flags);
b3821cc5 2058 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 2059 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
2060 txdesc->desc1.flags = flags;
2061 /*
2062 * Set tx buffer info after telling NIC to send
2063 * For better tx_clean timing
2064 */
2065 wmb();
2066 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2067 txbi->skb = skb;
2068 txbi->len = skb->len;
cd0ff491
GFT
2069 txbi->start_xmit = jiffies;
2070 if (!txbi->start_xmit)
8d27293f 2071 txbi->start_xmit = (0UL-1);
d7699f87
GFT
2072
2073 return 0;
2074}
2075
b3821cc5
GFT
2076static void
2077jme_stop_queue_if_full(struct jme_adapter *jme)
2078{
fa97b924 2079 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
2080 struct jme_buffer_info *txbi = txring->bufinf;
2081 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2082
cd0ff491 2083 txbi += idx;
b3821cc5
GFT
2084
2085 smp_wmb();
cd0ff491 2086 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2087 netif_stop_queue(jme->dev);
52a46ba8 2088 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2089 smp_wmb();
cd0ff491
GFT
2090 if (atomic_read(&txring->nr_free)
2091 >= (jme->tx_wake_threshold)) {
b3821cc5 2092 netif_wake_queue(jme->dev);
52a46ba8 2093 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
2094 }
2095 }
2096
cd0ff491 2097 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
2098 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2099 txbi->skb)) {
2100 netif_stop_queue(jme->dev);
52a46ba8
JP
2101 netif_info(jme, tx_queued, jme->dev,
2102 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2103 }
b3821cc5
GFT
2104}
2105
3bf61c55
GFT
2106/*
2107 * This function is already protected by netif_tx_lock()
2108 */
cd0ff491 2109
c97b5740 2110static netdev_tx_t
3bf61c55 2111jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2112{
cd0ff491 2113 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2114 int idx;
d7699f87 2115
cd0ff491 2116 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
2117 ++(NET_STAT(jme).tx_dropped);
2118 return NETDEV_TX_OK;
2119 }
2120
2121 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2122
cd0ff491 2123 if (unlikely(idx < 0)) {
b3821cc5 2124 netif_stop_queue(netdev);
52a46ba8
JP
2125 netif_err(jme, tx_err, jme->dev,
2126 "BUG! Tx ring full when queue awake!\n");
d7699f87 2127
cd0ff491 2128 return NETDEV_TX_BUSY;
b3821cc5
GFT
2129 }
2130
94c5ea02 2131 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2132
4330c2f2
GFT
2133 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2134 TXCS_SELECT_QUEUE0 |
2135 TXCS_QUEUE0S |
2136 TXCS_ENABLE);
d7699f87 2137
52a46ba8
JP
2138 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2139 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
2140 jme_stop_queue_if_full(jme);
2141
cd0ff491 2142 return NETDEV_TX_OK;
d7699f87
GFT
2143}
2144
bb4c5c8c
GFT
2145static void
2146jme_set_unicastaddr(struct net_device *netdev)
2147{
2148 struct jme_adapter *jme = netdev_priv(netdev);
2149 u32 val;
2150
2151 val = (netdev->dev_addr[3] & 0xff) << 24 |
2152 (netdev->dev_addr[2] & 0xff) << 16 |
2153 (netdev->dev_addr[1] & 0xff) << 8 |
2154 (netdev->dev_addr[0] & 0xff);
2155 jwrite32(jme, JME_RXUMA_LO, val);
2156 val = (netdev->dev_addr[5] & 0xff) << 8 |
2157 (netdev->dev_addr[4] & 0xff);
2158 jwrite32(jme, JME_RXUMA_HI, val);
2159}
2160
3bf61c55
GFT
2161static int
2162jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2163{
cd0ff491 2164 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2165 struct sockaddr *addr = p;
d7699f87 2166
cd0ff491 2167 if (netif_running(netdev))
d7699f87
GFT
2168 return -EBUSY;
2169
cd0ff491 2170 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2171 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
bb4c5c8c 2172 jme_set_unicastaddr(netdev);
cd0ff491 2173 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2174
2175 return 0;
2176}
2177
3bf61c55
GFT
2178static void
2179jme_set_multi(struct net_device *netdev)
d7699f87 2180{
3bf61c55 2181 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2182 u32 mc_hash[2] = {};
d7699f87 2183
cd0ff491 2184 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2185
2186 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2187
cd0ff491 2188 if (netdev->flags & IFF_PROMISC) {
8c198884 2189 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2190 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2191 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2192 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2193 struct netdev_hw_addr *ha;
3bf61c55 2194 int bit_nr;
d7699f87 2195
8c198884 2196 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP
2197 netdev_for_each_mc_addr(ha, netdev) {
2198 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT
2199 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2200 }
d7699f87 2201
4330c2f2
GFT
2202 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2203 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2204 }
2205
d7699f87 2206 wmb();
8c198884
GFT
2207 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2208
cd0ff491 2209 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2210}
2211
3bf61c55 2212static int
8c198884 2213jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2214{
cd0ff491 2215 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2216
cd0ff491 2217 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2218 return 0;
2219
cd0ff491
GFT
2220 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2221 ((new_mtu) < IPV6_MIN_MTU))
2222 return -EINVAL;
79ce639c 2223
cd0ff491 2224 if (new_mtu > 4000) {
79ce639c
GFT
2225 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2226 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2227 jme_restart_rx_engine(jme);
cd0ff491 2228 } else {
79ce639c
GFT
2229 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2230 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2231 jme_restart_rx_engine(jme);
2232 }
2233
cd0ff491 2234 netdev->mtu = new_mtu;
aa4d6a67
MM
2235 netdev_update_features(netdev);
2236
cd0ff491 2237 jme_reset_link(jme);
79ce639c
GFT
2238
2239 return 0;
d7699f87
GFT
2240}
2241
8c198884
GFT
2242static void
2243jme_tx_timeout(struct net_device *netdev)
2244{
cd0ff491 2245 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2246
cdcdc9eb
GFT
2247 jme->phylink = 0;
2248 jme_reset_phy_processor(jme);
cd0ff491 2249 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2250 jme_set_settings(netdev, &jme->old_ecmd);
2251
8c198884 2252 /*
cdcdc9eb 2253 * Force to Reset the link again
8c198884 2254 */
29bdd921 2255 jme_reset_link(jme);
8c198884
GFT
2256}
2257
f7f428e4
GFT
2258static inline void jme_pause_rx(struct jme_adapter *jme)
2259{
2260 atomic_dec(&jme->link_changing);
2261
2262 jme_set_rx_pcc(jme, PCC_OFF);
2263 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2264 JME_NAPI_DISABLE(jme);
2265 } else {
2266 tasklet_disable(&jme->rxclean_task);
2267 tasklet_disable(&jme->rxempty_task);
2268 }
2269}
2270
2271static inline void jme_resume_rx(struct jme_adapter *jme)
2272{
2273 struct dynpcc_info *dpi = &(jme->dpi);
2274
2275 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2276 JME_NAPI_ENABLE(jme);
2277 } else {
2278 tasklet_hi_enable(&jme->rxclean_task);
2279 tasklet_hi_enable(&jme->rxempty_task);
2280 }
2281 dpi->cur = PCC_P1;
2282 dpi->attempt = PCC_P1;
2283 dpi->cnt = 0;
2284 jme_set_rx_pcc(jme, PCC_P1);
2285
2286 atomic_inc(&jme->link_changing);
2287}
2288
3bf61c55
GFT
2289static void
2290jme_get_drvinfo(struct net_device *netdev,
2291 struct ethtool_drvinfo *info)
d7699f87 2292{
cd0ff491 2293 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2294
cd0ff491
GFT
2295 strcpy(info->driver, DRV_NAME);
2296 strcpy(info->version, DRV_VERSION);
2297 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2298}
2299
8c198884
GFT
2300static int
2301jme_get_regs_len(struct net_device *netdev)
2302{
cd0ff491 2303 return JME_REG_LEN;
8c198884
GFT
2304}
2305
2306static void
cd0ff491 2307mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2308{
2309 int i;
2310
cd0ff491 2311 for (i = 0 ; i < len ; i += 4)
79ce639c 2312 p[i >> 2] = jread32(jme, reg + i);
186fc259 2313}
8c198884 2314
186fc259 2315static void
cd0ff491 2316mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2317{
2318 int i;
cd0ff491 2319 u16 *p16 = (u16 *)p;
186fc259 2320
cd0ff491 2321 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2322 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2323}
2324
2325static void
2326jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2327{
cd0ff491
GFT
2328 struct jme_adapter *jme = netdev_priv(netdev);
2329 u32 *p32 = (u32 *)p;
8c198884 2330
186fc259 2331 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2332
2333 regs->version = 1;
2334 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2335
2336 p32 += 0x100 >> 2;
2337 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2338
2339 p32 += 0x100 >> 2;
2340 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2341
2342 p32 += 0x100 >> 2;
2343 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2344
186fc259
GFT
2345 p32 += 0x100 >> 2;
2346 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2347}
2348
2349static int
2350jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2351{
2352 struct jme_adapter *jme = netdev_priv(netdev);
2353
8c198884
GFT
2354 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2355 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2356
cd0ff491 2357 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2358 ecmd->use_adaptive_rx_coalesce = false;
2359 ecmd->rx_coalesce_usecs = 0;
2360 ecmd->rx_max_coalesced_frames = 0;
2361 return 0;
2362 }
2363
2364 ecmd->use_adaptive_rx_coalesce = true;
2365
cd0ff491 2366 switch (jme->dpi.cur) {
8c198884
GFT
2367 case PCC_P1:
2368 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2369 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2370 break;
2371 case PCC_P2:
2372 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2373 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2374 break;
2375 case PCC_P3:
2376 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2377 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2378 break;
2379 default:
2380 break;
2381 }
2382
2383 return 0;
2384}
2385
192570e0
GFT
2386static int
2387jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2388{
2389 struct jme_adapter *jme = netdev_priv(netdev);
2390 struct dynpcc_info *dpi = &(jme->dpi);
2391
cd0ff491 2392 if (netif_running(netdev))
cdcdc9eb
GFT
2393 return -EBUSY;
2394
c97b5740
GFT
2395 if (ecmd->use_adaptive_rx_coalesce &&
2396 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2397 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb 2398 jme->jme_rx = netif_rx;
192570e0
GFT
2399 dpi->cur = PCC_P1;
2400 dpi->attempt = PCC_P1;
2401 dpi->cnt = 0;
2402 jme_set_rx_pcc(jme, PCC_P1);
2403 jme_interrupt_mode(jme);
c97b5740
GFT
2404 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2405 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2406 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb 2407 jme->jme_rx = netif_receive_skb;
192570e0
GFT
2408 jme_interrupt_mode(jme);
2409 }
2410
2411 return 0;
2412}
2413
8c198884
GFT
2414static void
2415jme_get_pauseparam(struct net_device *netdev,
2416 struct ethtool_pauseparam *ecmd)
2417{
2418 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2419 u32 val;
8c198884
GFT
2420
2421 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2422 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2423
cd0ff491
GFT
2424 spin_lock_bh(&jme->phy_lock);
2425 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2426 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2427
2428 ecmd->autoneg =
2429 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2430}
2431
2432static int
2433jme_set_pauseparam(struct net_device *netdev,
2434 struct ethtool_pauseparam *ecmd)
2435{
2436 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2437 u32 val;
8c198884 2438
cd0ff491 2439 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2440 (ecmd->tx_pause != 0)) {
2441
cd0ff491 2442 if (ecmd->tx_pause)
8c198884
GFT
2443 jme->reg_txpfc |= TXPFC_PF_EN;
2444 else
2445 jme->reg_txpfc &= ~TXPFC_PF_EN;
2446
2447 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2448 }
2449
cd0ff491
GFT
2450 spin_lock_bh(&jme->rxmcs_lock);
2451 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2452 (ecmd->rx_pause != 0)) {
2453
cd0ff491 2454 if (ecmd->rx_pause)
8c198884
GFT
2455 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2456 else
2457 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2458
2459 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2460 }
cd0ff491 2461 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2462
cd0ff491
GFT
2463 spin_lock_bh(&jme->phy_lock);
2464 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2465 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2466 (ecmd->autoneg != 0)) {
2467
cd0ff491 2468 if (ecmd->autoneg)
8c198884
GFT
2469 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2470 else
2471 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2472
b3821cc5
GFT
2473 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2474 MII_ADVERTISE, val);
8c198884 2475 }
cd0ff491 2476 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2477
2478 return 0;
2479}
2480
29bdd921
GFT
2481static void
2482jme_get_wol(struct net_device *netdev,
2483 struct ethtool_wolinfo *wol)
2484{
2485 struct jme_adapter *jme = netdev_priv(netdev);
2486
2487 wol->supported = WAKE_MAGIC | WAKE_PHY;
2488
2489 wol->wolopts = 0;
2490
cd0ff491 2491 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2492 wol->wolopts |= WAKE_PHY;
2493
cd0ff491 2494 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2495 wol->wolopts |= WAKE_MAGIC;
2496
2497}
2498
2499static int
2500jme_set_wol(struct net_device *netdev,
2501 struct ethtool_wolinfo *wol)
2502{
2503 struct jme_adapter *jme = netdev_priv(netdev);
2504
cd0ff491 2505 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2506 WAKE_UCAST |
2507 WAKE_MCAST |
2508 WAKE_BCAST |
2509 WAKE_ARP))
2510 return -EOPNOTSUPP;
2511
2512 jme->reg_pmcs = 0;
2513
cd0ff491 2514 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2515 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2516
cd0ff491 2517 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2518 jme->reg_pmcs |= PMCS_MFEN;
2519
cd0ff491 2520 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
18783c49 2521 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
8ad2ddac 2522
29bdd921
GFT
2523 return 0;
2524}
b3821cc5 2525
3bf61c55
GFT
2526static int
2527jme_get_settings(struct net_device *netdev,
2528 struct ethtool_cmd *ecmd)
d7699f87
GFT
2529{
2530 struct jme_adapter *jme = netdev_priv(netdev);
2531 int rc;
8c198884 2532
cd0ff491 2533 spin_lock_bh(&jme->phy_lock);
d7699f87 2534 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2535 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2536 return rc;
2537}
2538
3bf61c55
GFT
2539static int
2540jme_set_settings(struct net_device *netdev,
2541 struct ethtool_cmd *ecmd)
d7699f87
GFT
2542{
2543 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2544 int rc, fdc = 0;
fcf45b4c 2545
035550c9
DD
2546 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2547 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2548 return -EINVAL;
2549
f79361a6
GFT
2550 /*
2551 * Check If user changed duplex only while force_media.
2552 * Hardware would not generate link change interrupt.
2553 */
cd0ff491 2554 if (jme->mii_if.force_media &&
79ce639c
GFT
2555 ecmd->autoneg != AUTONEG_ENABLE &&
2556 (jme->mii_if.full_duplex != ecmd->duplex))
2557 fdc = 1;
2558
cd0ff491 2559 spin_lock_bh(&jme->phy_lock);
d7699f87 2560 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2561 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2562
cd0ff491 2563 if (!rc) {
f79361a6
GFT
2564 if (fdc)
2565 jme_reset_link(jme);
29bdd921 2566 jme->old_ecmd = *ecmd;
43e4651b
GFT
2567 set_bit(JME_FLAG_SSET, &jme->flags);
2568 }
2569
2570 return rc;
2571}
2572
2573static int
2574jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2575{
2576 int rc;
2577 struct jme_adapter *jme = netdev_priv(netdev);
2578 struct mii_ioctl_data *mii_data = if_mii(rq);
2579 unsigned int duplex_chg;
2580
2581 if (cmd == SIOCSMIIREG) {
2582 u16 val = mii_data->val_in;
2583 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2584 (val & BMCR_SPEED1000))
2585 return -EINVAL;
2586 }
2587
2588 spin_lock_bh(&jme->phy_lock);
2589 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2590 spin_unlock_bh(&jme->phy_lock);
2591
2592 if (!rc && (cmd == SIOCSMIIREG)) {
2593 if (duplex_chg)
2594 jme_reset_link(jme);
2595 jme_get_settings(netdev, &jme->old_ecmd);
2596 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2597 }
2598
d7699f87
GFT
2599 return rc;
2600}
2601
cd0ff491 2602static u32
3bf61c55
GFT
2603jme_get_link(struct net_device *netdev)
2604{
d7699f87
GFT
2605 struct jme_adapter *jme = netdev_priv(netdev);
2606 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2607}
2608
8c198884 2609static u32
cd0ff491
GFT
2610jme_get_msglevel(struct net_device *netdev)
2611{
2612 struct jme_adapter *jme = netdev_priv(netdev);
2613 return jme->msg_enable;
2614}
2615
2616static void
2617jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2618{
cd0ff491
GFT
2619 struct jme_adapter *jme = netdev_priv(netdev);
2620 jme->msg_enable = value;
2621}
8c198884 2622
cd0ff491 2623static u32
aa4d6a67 2624jme_fix_features(struct net_device *netdev, u32 features)
cd0ff491 2625{
aa4d6a67
MM
2626 if (netdev->mtu > 1900)
2627 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2628 return features;
8c198884
GFT
2629}
2630
2631static int
aa4d6a67 2632jme_set_features(struct net_device *netdev, u32 features)
8c198884 2633{
cd0ff491 2634 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2635
cd0ff491 2636 spin_lock_bh(&jme->rxmcs_lock);
aa4d6a67 2637 if (features & NETIF_F_RXCSUM)
8c198884
GFT
2638 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2639 else
2640 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2641 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2642 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2643
2644 return 0;
2645}
2646
8c198884
GFT
2647static int
2648jme_nway_reset(struct net_device *netdev)
2649{
cd0ff491 2650 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2651 jme_restart_an(jme);
2652 return 0;
2653}
2654
cd0ff491 2655static u8
186fc259
GFT
2656jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2657{
cd0ff491 2658 u32 val;
186fc259
GFT
2659 int to;
2660
2661 val = jread32(jme, JME_SMBCSR);
2662 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2663 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2664 msleep(1);
2665 val = jread32(jme, JME_SMBCSR);
2666 }
cd0ff491 2667 if (!to) {
52a46ba8 2668 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2669 return 0xFF;
2670 }
2671
2672 jwrite32(jme, JME_SMBINTF,
2673 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2674 SMBINTF_HWRWN_READ |
2675 SMBINTF_HWCMD);
2676
2677 val = jread32(jme, JME_SMBINTF);
2678 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2679 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2680 msleep(1);
2681 val = jread32(jme, JME_SMBINTF);
2682 }
cd0ff491 2683 if (!to) {
52a46ba8 2684 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2685 return 0xFF;
2686 }
2687
2688 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2689}
2690
2691static void
cd0ff491 2692jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2693{
cd0ff491 2694 u32 val;
186fc259
GFT
2695 int to;
2696
2697 val = jread32(jme, JME_SMBCSR);
2698 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2699 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2700 msleep(1);
2701 val = jread32(jme, JME_SMBCSR);
2702 }
cd0ff491 2703 if (!to) {
52a46ba8 2704 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2705 return;
2706 }
2707
2708 jwrite32(jme, JME_SMBINTF,
2709 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2710 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2711 SMBINTF_HWRWN_WRITE |
2712 SMBINTF_HWCMD);
2713
2714 val = jread32(jme, JME_SMBINTF);
2715 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2716 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2717 msleep(1);
2718 val = jread32(jme, JME_SMBINTF);
2719 }
cd0ff491 2720 if (!to) {
52a46ba8 2721 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2722 return;
2723 }
2724
2725 mdelay(2);
2726}
2727
2728static int
2729jme_get_eeprom_len(struct net_device *netdev)
2730{
cd0ff491
GFT
2731 struct jme_adapter *jme = netdev_priv(netdev);
2732 u32 val;
186fc259 2733 val = jread32(jme, JME_SMBCSR);
cd0ff491 2734 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2735}
2736
2737static int
2738jme_get_eeprom(struct net_device *netdev,
2739 struct ethtool_eeprom *eeprom, u8 *data)
2740{
cd0ff491 2741 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2742 int i, offset = eeprom->offset, len = eeprom->len;
2743
2744 /*
8d27293f 2745 * ethtool will check the boundary for us
186fc259
GFT
2746 */
2747 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2748 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2749 data[i] = jme_smb_read(jme, i + offset);
2750
2751 return 0;
2752}
2753
2754static int
2755jme_set_eeprom(struct net_device *netdev,
2756 struct ethtool_eeprom *eeprom, u8 *data)
2757{
cd0ff491 2758 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2759 int i, offset = eeprom->offset, len = eeprom->len;
2760
2761 if (eeprom->magic != JME_EEPROM_MAGIC)
2762 return -EINVAL;
2763
2764 /*
8d27293f 2765 * ethtool will check the boundary for us
186fc259 2766 */
cd0ff491 2767 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2768 jme_smb_write(jme, i + offset, data[i]);
2769
2770 return 0;
2771}
2772
d7699f87 2773static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2774 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2775 .get_regs_len = jme_get_regs_len,
2776 .get_regs = jme_get_regs,
2777 .get_coalesce = jme_get_coalesce,
192570e0 2778 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2779 .get_pauseparam = jme_get_pauseparam,
2780 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2781 .get_wol = jme_get_wol,
2782 .set_wol = jme_set_wol,
d7699f87
GFT
2783 .get_settings = jme_get_settings,
2784 .set_settings = jme_set_settings,
2785 .get_link = jme_get_link,
cd0ff491
GFT
2786 .get_msglevel = jme_get_msglevel,
2787 .set_msglevel = jme_set_msglevel,
8c198884 2788 .nway_reset = jme_nway_reset,
186fc259
GFT
2789 .get_eeprom_len = jme_get_eeprom_len,
2790 .get_eeprom = jme_get_eeprom,
2791 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2792};
2793
3bf61c55
GFT
2794static int
2795jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2796{
94c5ea02 2797 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2798 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2799 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT
2800 return 1;
2801
94c5ea02 2802 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2803 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2804 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT
2805 return 1;
2806
fa97b924
GFT
2807 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2808 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT
2809 return 0;
2810
2811 return -1;
2812}
2813
cd0ff491 2814static inline void
cdcdc9eb
GFT
2815jme_phy_init(struct jme_adapter *jme)
2816{
cd0ff491 2817 u16 reg26;
cdcdc9eb
GFT
2818
2819 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2820 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2821}
2822
cd0ff491 2823static inline void
cdcdc9eb 2824jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2825{
cd0ff491 2826 u32 chipmode;
cdcdc9eb
GFT
2827
2828 chipmode = jread32(jme, JME_CHIPMODE);
2829
2830 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2831 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
4400ae98
GFT
2832 jme->chip_main_rev = jme->chiprev & 0xF;
2833 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT
2834}
2835
94c5ea02
GFT
2836static const struct net_device_ops jme_netdev_ops = {
2837 .ndo_open = jme_open,
2838 .ndo_stop = jme_close,
2839 .ndo_validate_addr = eth_validate_addr,
43e4651b 2840 .ndo_do_ioctl = jme_ioctl,
94c5ea02
GFT
2841 .ndo_start_xmit = jme_start_xmit,
2842 .ndo_set_mac_address = jme_set_macaddr,
43df9b78 2843 .ndo_set_rx_mode = jme_set_multi,
94c5ea02
GFT
2844 .ndo_change_mtu = jme_change_mtu,
2845 .ndo_tx_timeout = jme_tx_timeout,
aa4d6a67
MM
2846 .ndo_fix_features = jme_fix_features,
2847 .ndo_set_features = jme_set_features,
94c5ea02
GFT
2848};
2849
3bf61c55
GFT
2850static int __devinit
2851jme_init_one(struct pci_dev *pdev,
2852 const struct pci_device_id *ent)
2853{
cdcdc9eb 2854 int rc = 0, using_dac, i;
d7699f87
GFT
2855 struct net_device *netdev;
2856 struct jme_adapter *jme;
cd0ff491
GFT
2857 u16 bmcr, bmsr;
2858 u32 apmc;
d7699f87
GFT
2859
2860 /*
2861 * set up PCI device basics
2862 */
4330c2f2 2863 rc = pci_enable_device(pdev);
cd0ff491 2864 if (rc) {
52a46ba8 2865 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
2866 goto err_out;
2867 }
d7699f87 2868
3bf61c55 2869 using_dac = jme_pci_dma64(pdev);
cd0ff491 2870 if (using_dac < 0) {
52a46ba8 2871 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
2872 rc = -EIO;
2873 goto err_out_disable_pdev;
2874 }
2875
cd0ff491 2876 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
52a46ba8 2877 pr_err("No PCI resource region found\n");
4330c2f2
GFT
2878 rc = -ENOMEM;
2879 goto err_out_disable_pdev;
2880 }
d7699f87 2881
4330c2f2 2882 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2883 if (rc) {
52a46ba8 2884 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
2885 goto err_out_disable_pdev;
2886 }
d7699f87
GFT
2887
2888 pci_set_master(pdev);
2889
2890 /*
2891 * alloc and init net device
2892 */
3bf61c55 2893 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2894 if (!netdev) {
52a46ba8 2895 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
2896 rc = -ENOMEM;
2897 goto err_out_release_regions;
d7699f87 2898 }
94c5ea02 2899 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2900 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2901 netdev->watchdog_timeo = TX_TIMEOUT;
aa4d6a67
MM
2902 netdev->hw_features = NETIF_F_IP_CSUM |
2903 NETIF_F_IPV6_CSUM |
2904 NETIF_F_SG |
2905 NETIF_F_TSO |
2906 NETIF_F_TSO6 |
2907 NETIF_F_RXCSUM;
9a08cd10
MM
2908 netdev->features = NETIF_F_IP_CSUM |
2909 NETIF_F_IPV6_CSUM |
b3821cc5
GFT
2910 NETIF_F_SG |
2911 NETIF_F_TSO |
2912 NETIF_F_TSO6 |
42b1055e
GFT
2913 NETIF_F_HW_VLAN_TX |
2914 NETIF_F_HW_VLAN_RX;
cd0ff491 2915 if (using_dac)
8c198884 2916 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2917
2918 SET_NETDEV_DEV(netdev, &pdev->dev);
2919 pci_set_drvdata(pdev, netdev);
2920
2921 /*
2922 * init adapter info
2923 */
2924 jme = netdev_priv(netdev);
2925 jme->pdev = pdev;
2926 jme->dev = netdev;
cdcdc9eb 2927 jme->jme_rx = netif_rx;
29bdd921 2928 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2929 jme->phylink = 0;
b3821cc5
GFT
2930 jme->tx_ring_size = 1 << 10;
2931 jme->tx_ring_mask = jme->tx_ring_size - 1;
2932 jme->tx_wake_threshold = 1 << 9;
2933 jme->rx_ring_size = 1 << 9;
2934 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2935 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2936 jme->regs = ioremap(pci_resource_start(pdev, 0),
2937 pci_resource_len(pdev, 0));
4330c2f2 2938 if (!(jme->regs)) {
52a46ba8 2939 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
2940 rc = -ENOMEM;
2941 goto err_out_free_netdev;
2942 }
4330c2f2 2943
cd0ff491
GFT
2944 if (no_pseudohp) {
2945 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2946 jwrite32(jme, JME_APMC, apmc);
2947 } else if (force_pseudohp) {
2948 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2949 jwrite32(jme, JME_APMC, apmc);
2950 }
2951
cdcdc9eb 2952 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2953
d7699f87 2954 spin_lock_init(&jme->phy_lock);
fcf45b4c 2955 spin_lock_init(&jme->macaddr_lock);
8c198884 2956 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2957
fcf45b4c
GFT
2958 atomic_set(&jme->link_changing, 1);
2959 atomic_set(&jme->rx_cleaning, 1);
2960 atomic_set(&jme->tx_cleaning, 1);
192570e0 2961 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2962
79ce639c 2963 tasklet_init(&jme->pcc_task,
c97b5740 2964 jme_pcc_tasklet,
79ce639c 2965 (unsigned long) jme);
4330c2f2 2966 tasklet_init(&jme->linkch_task,
c97b5740 2967 jme_link_change_tasklet,
4330c2f2
GFT
2968 (unsigned long) jme);
2969 tasklet_init(&jme->txclean_task,
c97b5740 2970 jme_tx_clean_tasklet,
4330c2f2
GFT
2971 (unsigned long) jme);
2972 tasklet_init(&jme->rxclean_task,
c97b5740 2973 jme_rx_clean_tasklet,
4330c2f2 2974 (unsigned long) jme);
fcf45b4c 2975 tasklet_init(&jme->rxempty_task,
c97b5740 2976 jme_rx_empty_tasklet,
fcf45b4c 2977 (unsigned long) jme);
fa97b924 2978 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
2979 tasklet_disable_nosync(&jme->txclean_task);
2980 tasklet_disable_nosync(&jme->rxclean_task);
2981 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
2982 jme->dpi.cur = PCC_P1;
2983
cd0ff491 2984 jme->reg_ghc = 0;
79ce639c 2985 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2986 jme->reg_rxmcs = RXMCS_DEFAULT;
2987 jme->reg_txpfc = 0;
47220951 2988 jme->reg_pmcs = PMCS_MFEN;
ed830419 2989 jme->reg_gpreg1 = GPREG1_DEFAULT;
aa4d6a67
MM
2990
2991 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
2992 netdev->features |= NETIF_F_RXCSUM;
192570e0 2993
fcf45b4c
GFT
2994 /*
2995 * Get Max Read Req Size from PCI Config Space
2996 */
cd0ff491
GFT
2997 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2998 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2999 switch (jme->mrrs) {
3000 case MRRS_128B:
3001 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3002 break;
3003 case MRRS_256B:
3004 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3005 break;
3006 default:
3007 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3008 break;
06527f9b 3009 }
fcf45b4c 3010
d7699f87 3011 /*
cdcdc9eb 3012 * Must check before reset_mac_processor
d7699f87 3013 */
cdcdc9eb
GFT
3014 jme_check_hw_ver(jme);
3015 jme->mii_if.dev = netdev;
cd0ff491 3016 if (jme->fpgaver) {
cdcdc9eb 3017 jme->mii_if.phy_id = 0;
cd0ff491 3018 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
3019 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3020 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3021 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
3022 jme->mii_if.phy_id = i;
3023 break;
3024 }
3025 }
3026
cd0ff491 3027 if (!jme->mii_if.phy_id) {
cdcdc9eb 3028 rc = -EIO;
52a46ba8
JP
3029 pr_err("Can not find phy_id\n");
3030 goto err_out_unmap;
cdcdc9eb
GFT
3031 }
3032
3033 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3034 } else {
cdcdc9eb
GFT
3035 jme->mii_if.phy_id = 1;
3036 }
cd0ff491 3037 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
3038 jme->mii_if.supports_gmii = true;
3039 else
3040 jme->mii_if.supports_gmii = false;
43e4651b
GFT
3041 jme->mii_if.phy_id_mask = 0x1F;
3042 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT
3043 jme->mii_if.mdio_read = jme_mdio_read;
3044 jme->mii_if.mdio_write = jme_mdio_write;
3045
d7699f87 3046 jme_clear_pm(jme);
18783c49
GFT
3047 pci_set_power_state(jme->pdev, PCI_D0);
3048 device_set_wakeup_enable(&pdev->dev, true);
3049
06168a20 3050 jme_set_phyfifo_5level(jme);
6db67aa5 3051 jme->pcirev = pdev->revision;
cd0ff491 3052 if (!jme->fpgaver)
cdcdc9eb 3053 jme_phy_init(jme);
42b1055e 3054 jme_phy_off(jme);
cdcdc9eb
GFT
3055
3056 /*
3057 * Reset MAC processor and reload EEPROM for MAC Address
3058 */
d7699f87 3059 jme_reset_mac_processor(jme);
4330c2f2 3060 rc = jme_reload_eeprom(jme);
cd0ff491 3061 if (rc) {
52a46ba8 3062 pr_err("Reload eeprom for reading MAC Address error\n");
fa97b924 3063 goto err_out_unmap;
4330c2f2 3064 }
d7699f87
GFT
3065 jme_load_macaddr(netdev);
3066
d7699f87
GFT
3067 /*
3068 * Tell stack that we are not ready to work until open()
3069 */
3070 netif_carrier_off(netdev);
d7699f87 3071
4330c2f2 3072 rc = register_netdev(netdev);
cd0ff491 3073 if (rc) {
52a46ba8 3074 pr_err("Cannot register net device\n");
fa97b924 3075 goto err_out_unmap;
4330c2f2 3076 }
d7699f87 3077
4400ae98 3078 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
c97b5740
GFT
3079 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3080 "JMC250 Gigabit Ethernet" :
3081 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3082 "JMC260 Fast Ethernet" : "Unknown",
3083 (jme->fpgaver != 0) ? " (FPGA)" : "",
3084 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
4400ae98 3085 jme->pcirev, netdev->dev_addr);
d7699f87
GFT
3086
3087 return 0;
3088
3089err_out_unmap:
3090 iounmap(jme->regs);
3091err_out_free_netdev:
3092 pci_set_drvdata(pdev, NULL);
3093 free_netdev(netdev);
4330c2f2
GFT
3094err_out_release_regions:
3095 pci_release_regions(pdev);
d7699f87 3096err_out_disable_pdev:
cd0ff491 3097 pci_disable_device(pdev);
d7699f87 3098err_out:
4330c2f2 3099 return rc;
d7699f87
GFT
3100}
3101
3bf61c55
GFT
3102static void __devexit
3103jme_remove_one(struct pci_dev *pdev)
3104{
d7699f87
GFT
3105 struct net_device *netdev = pci_get_drvdata(pdev);
3106 struct jme_adapter *jme = netdev_priv(netdev);
3107
3108 unregister_netdev(netdev);
3109 iounmap(jme->regs);
3110 pci_set_drvdata(pdev, NULL);
3111 free_netdev(netdev);
3112 pci_release_regions(pdev);
3113 pci_disable_device(pdev);
3114
3115}
3116
fba4bc0c
GFT
3117static void
3118jme_shutdown(struct pci_dev *pdev)
3119{
3120 struct net_device *netdev = pci_get_drvdata(pdev);
3121 struct jme_adapter *jme = netdev_priv(netdev);
3122
3123 jme_powersave_phy(jme);
3124 pci_pme_active(pdev, true);
3125}
3126
e10cd037 3127#ifdef CONFIG_PM_SLEEP
18783c49
GFT
3128static int
3129jme_suspend(struct device *dev)
29bdd921 3130{
8ad2ddac 3131 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT
3132 struct net_device *netdev = pci_get_drvdata(pdev);
3133 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
3134
3135 atomic_dec(&jme->link_changing);
3136
3137 netif_device_detach(netdev);
3138 netif_stop_queue(netdev);
3139 jme_stop_irq(jme);
29bdd921 3140
cd0ff491
GFT
3141 tasklet_disable(&jme->txclean_task);
3142 tasklet_disable(&jme->rxclean_task);
3143 tasklet_disable(&jme->rxempty_task);
3144
cd0ff491
GFT
3145 if (netif_carrier_ok(netdev)) {
3146 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
3147 jme_polling_mode(jme);
3148
29bdd921 3149 jme_stop_pcc_timer(jme);
cd0ff491
GFT
3150 jme_disable_rx_engine(jme);
3151 jme_disable_tx_engine(jme);
29bdd921
GFT
3152 jme_reset_mac_processor(jme);
3153 jme_free_rx_resources(jme);
3154 jme_free_tx_resources(jme);
3155 netif_carrier_off(netdev);
3156 jme->phylink = 0;
3157 }
3158
cd0ff491
GFT
3159 tasklet_enable(&jme->txclean_task);
3160 tasklet_hi_enable(&jme->rxclean_task);
3161 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3162
fba4bc0c 3163 jme_powersave_phy(jme);
29bdd921
GFT
3164
3165 return 0;
3166}
3167
18783c49
GFT
3168static int
3169jme_resume(struct device *dev)
29bdd921 3170{
8ad2ddac 3171 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT
3172 struct net_device *netdev = pci_get_drvdata(pdev);
3173 struct jme_adapter *jme = netdev_priv(netdev);
3174
18783c49 3175 jme_clear_pm(jme);
e4610a83
GFT
3176 jme_phy_on(jme);
3177 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3178 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 3179 else
29bdd921
GFT
3180 jme_reset_phy_processor(jme);
3181
29bdd921
GFT
3182 jme_start_irq(jme);
3183 netif_device_attach(netdev);
3184
3185 atomic_inc(&jme->link_changing);
3186
3187 jme_reset_link(jme);
3188
3189 return 0;
3190}
8ad2ddac
RW
3191
3192static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3193#define JME_PM_OPS (&jme_pm_ops)
3194
3195#else
3196
3197#define JME_PM_OPS NULL
9b9d55de 3198#endif
29bdd921 3199
c97b5740 3200static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT
3201 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3202 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3203 { }
3204};
3205
3206static struct pci_driver jme_driver = {
cd0ff491
GFT
3207 .name = DRV_NAME,
3208 .id_table = jme_pci_tbl,
3209 .probe = jme_init_one,
3210 .remove = __devexit_p(jme_remove_one),
fba4bc0c 3211 .shutdown = jme_shutdown,
8ad2ddac 3212 .driver.pm = JME_PM_OPS,
d7699f87
GFT
3213};
3214
3bf61c55
GFT
3215static int __init
3216jme_init_module(void)
d7699f87 3217{
52a46ba8 3218 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3219 return pci_register_driver(&jme_driver);
3220}
3221
3bf61c55
GFT
3222static void __exit
3223jme_cleanup_module(void)
d7699f87
GFT
3224{
3225 pci_unregister_driver(&jme_driver);
3226}
3227
3228module_init(jme_init_module);
3229module_exit(jme_cleanup_module);
3230
3bf61c55 3231MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3232MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3233MODULE_LICENSE("GPL");
3234MODULE_VERSION(DRV_VERSION);
3235MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3236