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[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
52a46ba8
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
d7699f87
GFT		 27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
4330c2f2 35#include <linux/delay.h>
29bdd921 36#include <linux/spinlock.h>
8c198884
GFT		 37#include <linux/in.h>
38#include <linux/ip.h>
79ce639c
GFT		 39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42b1055e 42#include <linux/if_vlan.h>
6d641c63 43#include <linux/slab.h>
94c5ea02 44#include <net/ip6_checksum.h>
d7699f87
GFT		 45#include "jme.h"
46
cd0ff491
GFT		 47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 58
3bf61c55
GFT		 59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 61{
62 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 64
186fc259 65read_again:
cd0ff491 66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
d7699f87
GFT		 69
70 wmb();
cd0ff491 71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 72 udelay(20);
b3821cc5
GFT		 73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
3bf61c55 75 break;
cd0ff491 76 }
d7699f87 77
cd0ff491 78 if (i == 0) {
52a46ba8 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 80 return 0;
cd0ff491 81 }
d7699f87 82
cd0ff491 83 if (again--)
186fc259
GFT		 84 goto read_again;
85
cd0ff491 86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 87}
88
3bf61c55
GFT		 89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
d7699f87
GFT		 92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
3bf61c55
GFT		 96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 99
100 wmb();
cdcdc9eb
GFT		 101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
8d27293f 103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 104 break;
105 }
d7699f87 106
3bf61c55 107 if (i == 0)
52a46ba8 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 109}
110
cd0ff491 111static inline void
3bf61c55 112jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 113{
cd0ff491 114 u32 val;
3bf61c55
GFT		 115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
8c198884
GFT		 118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 120
cd0ff491 121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 126
fcf45b4c
GFT		 127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 134}
135
b3821cc5
GFT		 136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
0d8a2973 138 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
ed830419
GFT		 163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
cd0ff491 224static inline void
3bf61c55
GFT		 225jme_reset_mac_processor(struct jme_adapter *jme)
226{
0d8a2973 227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
b3821cc5
GFT		 230 int i;
231
ed830419
GFT		 232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
cd0ff491
GFT		 250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
4330c2f2
GFT		 260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 263 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 264 if (jme->fpgaver)
cdcdc9eb
GFT		 265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 269}
270
271static inline void
3bf61c55 272jme_clear_pm(struct jme_adapter *jme)
d7699f87 273{
29bdd921 274 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 275 pci_set_power_state(jme->pdev, PCI_D0);
8ad2ddac 276 device_set_wakeup_enable(&jme->pdev->dev, false);
d7699f87
GFT		 277}
278
3bf61c55
GFT		 279static int
280jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 281{
cd0ff491 282 u32 val;
d7699f87
GFT		 283 int i;
284
285 val = jread32(jme, JME_SMBCSR);
286
cd0ff491 287 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 288 val |= SMBCSR_CNACK;
289 jwrite32(jme, JME_SMBCSR, val);
290 val |= SMBCSR_RELOAD;
291 jwrite32(jme, JME_SMBCSR, val);
292 mdelay(12);
293
cd0ff491 294 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 295 mdelay(1);
296 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
297 break;
298 }
299
cd0ff491 300 if (i == 0) {
52a46ba8 301 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 302 return -EIO;
303 }
304 }
3bf61c55 305
d7699f87
GFT		 306 return 0;
307}
308
3bf61c55
GFT		 309static void
310jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 311{
312 struct jme_adapter *jme = netdev_priv(netdev);
313 unsigned char macaddr[6];
cd0ff491 314 u32 val;
d7699f87 315
cd0ff491 316 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 317 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 318 macaddr[0] = (val >> 0) & 0xFF;
319 macaddr[1] = (val >> 8) & 0xFF;
320 macaddr[2] = (val >> 16) & 0xFF;
321 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 322 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 323 macaddr[4] = (val >> 0) & 0xFF;
324 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 325 memcpy(netdev->dev_addr, macaddr, 6);
326 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 327}
328
cd0ff491 329static inline void
3bf61c55
GFT		 330jme_set_rx_pcc(struct jme_adapter *jme, int p)
331{
cd0ff491 332 switch (p) {
192570e0
GFT		 333 case PCC_OFF:
334 jwrite32(jme, JME_PCCRX0,
335 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
336 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
337 break;
3bf61c55
GFT		 338 case PCC_P1:
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 break;
343 case PCC_P2:
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 break;
348 case PCC_P3:
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 break;
353 default:
354 break;
355 }
192570e0 356 wmb();
3bf61c55 357
cd0ff491 358 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 359 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 360}
361
fcf45b4c 362static void
3bf61c55 363jme_start_irq(struct jme_adapter *jme)
d7699f87 364{
3bf61c55
GFT		 365 register struct dynpcc_info *dpi = &(jme->dpi);
366
367 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 368 dpi->cur = PCC_P1;
369 dpi->attempt = PCC_P1;
370 dpi->cnt = 0;
371
372 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 373 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
374 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 375 PCCTXQ0_EN
376 );
377
d7699f87
GFT		 378 /*
379 * Enable Interrupts
380 */
381 jwrite32(jme, JME_IENS, INTR_ENABLE);
382}
383
cd0ff491 384static inline void
3bf61c55 385jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 386{
387 /*
388 * Disable Interrupts
389 */
cd0ff491 390 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 391}
392
cd0ff491 393static u32
cdcdc9eb
GFT		 394jme_linkstat_from_phy(struct jme_adapter *jme)
395{
cd0ff491 396 u32 phylink, bmsr;
cdcdc9eb
GFT		 397
398 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
399 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 400 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 401 phylink |= PHY_LINK_AUTONEG_COMPLETE;
402
403 return phylink;
404}
405
cd0ff491 406static inline void
06168a20 407jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 408{
409 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
410}
411
412static inline void
06168a20 413jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 414{
415 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
416}
417
fcf45b4c
GFT		 418static int
419jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 420{
421 struct jme_adapter *jme = netdev_priv(netdev);
ed830419 422 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 423 char linkmsg[64];
fcf45b4c 424 int rc = 0;
d7699f87 425
b3821cc5 426 linkmsg[0] = '\0';
cdcdc9eb 427
cd0ff491 428 if (jme->fpgaver)
cdcdc9eb
GFT		 429 phylink = jme_linkstat_from_phy(jme);
430 else
431 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 432
cd0ff491
GFT		 433 if (phylink & PHY_LINK_UP) {
434 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 435 /*
436 * If we did not enable AN
437 * Speed/Duplex Info should be obtained from SMI
438 */
439 phylink = PHY_LINK_UP;
440
441 bmcr = jme_mdio_read(jme->dev,
442 jme->mii_if.phy_id,
443 MII_BMCR);
444
445 phylink |= ((bmcr & BMCR_SPEED1000) &&
446 (bmcr & BMCR_SPEED100) == 0) ?
447 PHY_LINK_SPEED_1000M :
448 (bmcr & BMCR_SPEED100) ?
449 PHY_LINK_SPEED_100M :
450 PHY_LINK_SPEED_10M;
451
452 phylink |= (bmcr & BMCR_FULLDPLX) ?
453 PHY_LINK_DUPLEX : 0;
79ce639c 454
b3821cc5 455 strcat(linkmsg, "Forced: ");
cd0ff491 456 } else {
8c198884
GFT		 457 /*
458 * Keep polling for speed/duplex resolve complete
459 */
cd0ff491 460 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 461 --cnt) {
462
463 udelay(1);
8c198884 464
cd0ff491 465 if (jme->fpgaver)
cdcdc9eb
GFT		 466 phylink = jme_linkstat_from_phy(jme);
467 else
468 phylink = jread32(jme, JME_PHY_LINK);
8c198884 469 }
cd0ff491 470 if (!cnt)
52a46ba8 471 pr_err("Waiting speed resolve timeout\n");
79ce639c 472
b3821cc5 473 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 474 }
475
cd0ff491 476 if (jme->phylink == phylink) {
fcf45b4c
GFT		 477 rc = 1;
478 goto out;
479 }
cd0ff491 480 if (testonly)
fcf45b4c
GFT		 481 goto out;
482
483 jme->phylink = phylink;
484
ed830419
GFT		 485 /*
486 * The speed/duplex setting of jme->reg_ghc already cleared
487 * by jme_reset_mac_processor()
488 */
cd0ff491
GFT		 489 switch (phylink & PHY_LINK_SPEED_MASK) {
490 case PHY_LINK_SPEED_10M:
ed830419 491 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 492 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 493 break;
494 case PHY_LINK_SPEED_100M:
ed830419 495 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 496 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 497 break;
498 case PHY_LINK_SPEED_1000M:
ed830419 499 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 500 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 501 break;
502 default:
503 break;
d7699f87 504 }
d7699f87 505
cd0ff491 506 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 507 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
19bbc546 508 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
ed830419 509 jme->reg_ghc |= GHC_DPX;
cd0ff491 510 } else {
d7699f87 511 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 512 TXMCS_BACKOFF |
513 TXMCS_CARRIERSENSE |
514 TXMCS_COLLISION);
19bbc546 515 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 516 }
9b9d55de 517
ed830419
GFT		 518 jwrite32(jme, JME_GHC, jme->reg_ghc);
519
9b9d55de 520 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
ed830419
GFT		 521 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
522 GPREG1_RSSPATCH);
9b9d55de 523 if (!(phylink & PHY_LINK_DUPLEX))
ed830419 524 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
9b9d55de
GFT		 525 switch (phylink & PHY_LINK_SPEED_MASK) {
526 case PHY_LINK_SPEED_10M:
06168a20 527 jme_set_phyfifo_8level(jme);
ed830419 528 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT		 529 break;
530 case PHY_LINK_SPEED_100M:
06168a20 531 jme_set_phyfifo_5level(jme);
ed830419 532 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT		 533 break;
534 case PHY_LINK_SPEED_1000M:
06168a20 535 jme_set_phyfifo_8level(jme);
9b9d55de
GFT		 536 break;
537 default:
538 break;
539 }
540 }
ed830419 541 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 542
94c5ea02
GFT		 543 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
544 "Full-Duplex, " :
545 "Half-Duplex, ");
546 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
547 "MDI-X" :
548 "MDI");
52a46ba8 549 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 550 netif_carrier_on(netdev);
551 } else {
552 if (testonly)
fcf45b4c
GFT		 553 goto out;
554
52a46ba8 555 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 556 jme->phylink = 0;
cd0ff491 557 netif_carrier_off(netdev);
d7699f87 558 }
fcf45b4c
GFT		 559
560out:
561 return rc;
d7699f87
GFT		 562}
563
3bf61c55
GFT		 564static int
565jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 566{
d7699f87
GFT		 567 struct jme_ring *txring = &(jme->txring[0]);
568
569 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 570 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
571 &(txring->dmaalloc),
572 GFP_ATOMIC);
fcf45b4c 573
fa97b924
GFT		 574 if (!txring->alloc)
575 goto err_set_null;
d7699f87
GFT		 576
577 /*
578 * 16 Bytes align
579 */
cd0ff491 580 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 581 RING_DESC_ALIGN);
4330c2f2 582 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 583 txring->next_to_use = 0;
cdcdc9eb 584 atomic_set(&txring->next_to_clean, 0);
b3821cc5 585 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 586
fa97b924
GFT		 587 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
588 jme->tx_ring_size, GFP_ATOMIC);
589 if (unlikely(!(txring->bufinf)))
590 goto err_free_txring;
591
d7699f87 592 /*
b3821cc5 593 * Initialize Transmit Descriptors
d7699f87 594 */
b3821cc5 595 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 596 memset(txring->bufinf, 0,
b3821cc5 597 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 598
599 return 0;
fa97b924
GFT		 600
601err_free_txring:
602 dma_free_coherent(&(jme->pdev->dev),
603 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
604 txring->alloc,
605 txring->dmaalloc);
606
607err_set_null:
608 txring->desc = NULL;
609 txring->dmaalloc = 0;
610 txring->dma = 0;
611 txring->bufinf = NULL;
612
613 return -ENOMEM;
d7699f87
GFT		 614}
615
3bf61c55
GFT		 616static void
617jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 618{
619 int i;
620 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 621 struct jme_buffer_info *txbi;
d7699f87 622
cd0ff491 623 if (txring->alloc) {
fa97b924
GFT		 624 if (txring->bufinf) {
625 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
626 txbi = txring->bufinf + i;
627 if (txbi->skb) {
628 dev_kfree_skb(txbi->skb);
629 txbi->skb = NULL;
630 }
631 txbi->mapping = 0;
632 txbi->len = 0;
633 txbi->nr_desc = 0;
634 txbi->start_xmit = 0;
d7699f87 635 }
fa97b924 636 kfree(txring->bufinf);
d7699f87
GFT		 637 }
638
639 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 640 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 641 txring->alloc,
642 txring->dmaalloc);
3bf61c55
GFT		 643
644 txring->alloc = NULL;
645 txring->desc = NULL;
646 txring->dmaalloc = 0;
647 txring->dma = 0;
fa97b924 648 txring->bufinf = NULL;
d7699f87 649 }
3bf61c55 650 txring->next_to_use = 0;
cdcdc9eb 651 atomic_set(&txring->next_to_clean, 0);
79ce639c 652 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 653}
654
cd0ff491 655static inline void
3bf61c55 656jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 657{
658 /*
659 * Select Queue 0
660 */
661 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 662 wmb();
d7699f87
GFT		 663
664 /*
665 * Setup TX Queue 0 DMA Bass Address
666 */
fcf45b4c 667 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 668 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 669 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 670
671 /*
672 * Setup TX Descptor Count
673 */
b3821cc5 674 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 675
676 /*
677 * Enable TX Engine
678 */
679 wmb();
ed830419 680 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 681 TXCS_SELECT_QUEUE0 |
682 TXCS_ENABLE);
d7699f87 683
ed830419
GFT		 684 /*
685 * Start clock for TX MAC Processor
686 */
687 jme_mac_txclk_on(jme);
d7699f87
GFT		 688}
689
cd0ff491 690static inline void
29bdd921
GFT		 691jme_restart_tx_engine(struct jme_adapter *jme)
692{
693 /*
694 * Restart TX Engine
695 */
696 jwrite32(jme, JME_TXCS, jme->reg_txcs |
697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
699}
700
cd0ff491 701static inline void
3bf61c55 702jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 703{
704 int i;
cd0ff491 705 u32 val;
d7699f87
GFT		 706
707 /*
708 * Disable TX Engine
709 */
fcf45b4c 710 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 711 wmb();
d7699f87
GFT		 712
713 val = jread32(jme, JME_TXCS);
cd0ff491 714 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 715 mdelay(1);
d7699f87 716 val = jread32(jme, JME_TXCS);
cd0ff491 717 rmb();
d7699f87
GFT		 718 }
719
cd0ff491 720 if (!i)
52a46ba8 721 pr_err("Disable TX engine timeout\n");
ed830419
GFT		 722
723 /*
724 * Stop clock for TX MAC Processor
725 */
726 jme_mac_txclk_off(jme);
d7699f87
GFT		 727}
728
3bf61c55
GFT		 729static void
730jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 731{
fa97b924 732 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 733 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 734 struct jme_buffer_info *rxbi = rxring->bufinf;
735 rxdesc += i;
736 rxbi += i;
737
738 rxdesc->dw[0] = 0;
739 rxdesc->dw[1] = 0;
3bf61c55 740 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 741 rxdesc->desc1.bufaddrl = cpu_to_le32(
742 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 743 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 744 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 745 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 746 wmb();
3bf61c55 747 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 748}
749
3bf61c55
GFT		 750static int
751jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 752{
753 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 754 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 755 struct sk_buff *skb;
4330c2f2 756
79ce639c
GFT		 757 skb = netdev_alloc_skb(jme->dev,
758 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 759 if (unlikely(!skb))
4330c2f2 760 return -ENOMEM;
3bf61c55 761
4330c2f2 762 rxbi->skb = skb;
3bf61c55 763 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 764 rxbi->mapping = pci_map_page(jme->pdev,
765 virt_to_page(skb->data),
766 offset_in_page(skb->data),
767 rxbi->len,
768 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 769
770 return 0;
771}
772
3bf61c55
GFT		 773static void
774jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 775{
776 struct jme_ring *rxring = &(jme->rxring[0]);
777 struct jme_buffer_info *rxbi = rxring->bufinf;
778 rxbi += i;
779
cd0ff491 780 if (rxbi->skb) {
b3821cc5 781 pci_unmap_page(jme->pdev,
4330c2f2 782 rxbi->mapping,
3bf61c55 783 rxbi->len,
4330c2f2
GFT		 784 PCI_DMA_FROMDEVICE);
785 dev_kfree_skb(rxbi->skb);
786 rxbi->skb = NULL;
787 rxbi->mapping = 0;
3bf61c55 788 rxbi->len = 0;
4330c2f2
GFT		 789 }
790}
791
3bf61c55
GFT		 792static void
793jme_free_rx_resources(struct jme_adapter *jme)
794{
795 int i;
796 struct jme_ring *rxring = &(jme->rxring[0]);
797
cd0ff491 798 if (rxring->alloc) {
fa97b924
GFT		 799 if (rxring->bufinf) {
800 for (i = 0 ; i < jme->rx_ring_size ; ++i)
801 jme_free_rx_buf(jme, i);
802 kfree(rxring->bufinf);
803 }
3bf61c55
GFT		 804
805 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 806 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 807 rxring->alloc,
808 rxring->dmaalloc);
809 rxring->alloc = NULL;
810 rxring->desc = NULL;
811 rxring->dmaalloc = 0;
812 rxring->dma = 0;
fa97b924 813 rxring->bufinf = NULL;
3bf61c55
GFT		 814 }
815 rxring->next_to_use = 0;
cdcdc9eb 816 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 817}
818
819static int
820jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 821{
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
824
825 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 826 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
827 &(rxring->dmaalloc),
828 GFP_ATOMIC);
fa97b924
GFT		 829 if (!rxring->alloc)
830 goto err_set_null;
d7699f87
GFT		 831
832 /*
833 * 16 Bytes align
834 */
cd0ff491 835 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 836 RING_DESC_ALIGN);
4330c2f2 837 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 838 rxring->next_to_use = 0;
cdcdc9eb 839 atomic_set(&rxring->next_to_clean, 0);
d7699f87 840
fa97b924
GFT		 841 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
842 jme->rx_ring_size, GFP_ATOMIC);
843 if (unlikely(!(rxring->bufinf)))
844 goto err_free_rxring;
845
d7699f87
GFT		 846 /*
847 * Initiallize Receive Descriptors
848 */
fa97b924
GFT		 849 memset(rxring->bufinf, 0,
850 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 851 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
852 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 853 jme_free_rx_resources(jme);
854 return -ENOMEM;
855 }
d7699f87
GFT		 856
857 jme_set_clean_rxdesc(jme, i);
858 }
859
d7699f87 860 return 0;
fa97b924
GFT		 861
862err_free_rxring:
863 dma_free_coherent(&(jme->pdev->dev),
864 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
865 rxring->alloc,
866 rxring->dmaalloc);
867err_set_null:
868 rxring->desc = NULL;
869 rxring->dmaalloc = 0;
870 rxring->dma = 0;
871 rxring->bufinf = NULL;
872
873 return -ENOMEM;
d7699f87
GFT		 874}
875
cd0ff491 876static inline void
3bf61c55 877jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 878{
cd0ff491
GFT		 879 /*
880 * Select Queue 0
881 */
882 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
883 RXCS_QUEUESEL_Q0);
884 wmb();
885
d7699f87
GFT		 886 /*
887 * Setup RX DMA Bass Address
888 */
fa97b924 889 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 890 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 891 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 892
893 /*
b3821cc5 894 * Setup RX Descriptor Count
d7699f87 895 */
b3821cc5 896 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 897
3bf61c55 898 /*
d7699f87
GFT		 899 * Setup Unicast Filter
900 */
bb4c5c8c 901 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 902 jme_set_multi(jme->dev);
903
904 /*
905 * Enable RX Engine
906 */
907 wmb();
ed830419 908 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 909 RXCS_QUEUESEL_Q0 |
910 RXCS_ENABLE |
911 RXCS_QST);
ed830419
GFT		 912
913 /*
914 * Start clock for RX MAC Processor
915 */
916 jme_mac_rxclk_on(jme);
d7699f87
GFT		 917}
918
cd0ff491 919static inline void
3bf61c55 920jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 921{
922 /*
3bf61c55 923 * Start RX Engine
4330c2f2 924 */
79ce639c 925 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 926 RXCS_QUEUESEL_Q0 |
927 RXCS_ENABLE |
928 RXCS_QST);
929}
930
cd0ff491 931static inline void
3bf61c55 932jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 933{
934 int i;
cd0ff491 935 u32 val;
d7699f87
GFT		 936
937 /*
938 * Disable RX Engine
939 */
29bdd921 940 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 941 wmb();
d7699f87
GFT		 942
943 val = jread32(jme, JME_RXCS);
cd0ff491 944 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 945 mdelay(1);
d7699f87 946 val = jread32(jme, JME_RXCS);
cd0ff491 947 rmb();
d7699f87
GFT		 948 }
949
cd0ff491 950 if (!i)
52a46ba8 951 pr_err("Disable RX engine timeout\n");
d7699f87 952
ed830419
GFT		 953 /*
954 * Stop clock for RX MAC Processor
955 */
956 jme_mac_rxclk_off(jme);
d7699f87
GFT		 957}
958
a452eef1
GFT		 959static u16
960jme_udpsum(struct sk_buff *skb)
961{
962 u16 csum = 0xFFFFu;
963
964 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
965 return csum;
966 if (skb->protocol != htons(ETH_P_IP))
967 return csum;
968 skb_set_network_header(skb, ETH_HLEN);
969 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
970 (skb->len < (ETH_HLEN +
971 (ip_hdr(skb)->ihl << 2) +
972 sizeof(struct udphdr)))) {
973 skb_reset_network_header(skb);
974 return csum;
975 }
976 skb_set_transport_header(skb,
977 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
978 csum = udp_hdr(skb)->check;
979 skb_reset_transport_header(skb);
980 skb_reset_network_header(skb);
981
982 return csum;
983}
984
192570e0 985static int
a452eef1 986jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 987{
cd0ff491 988 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 989 return false;
990
fa97b924
GFT		 991 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
992 == RXWBFLAG_TCPON)) {
993 if (flags & RXWBFLAG_IPV4)
c97b5740 994 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 995 return false;
192570e0
GFT		 996 }
997
fa97b924 998 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
a452eef1 999 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
fa97b924 1000 if (flags & RXWBFLAG_IPV4)
52a46ba8 1001 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
fa97b924 1002 return false;
192570e0
GFT		 1003 }
1004
fa97b924
GFT		 1005 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1006 == RXWBFLAG_IPV4)) {
52a46ba8 1007 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
fa97b924 1008 return false;
192570e0
GFT		 1009 }
1010
1011 return true;
1012}
1013
3bf61c55 1014static void
42b1055e 1015jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1016{
d7699f87 1017 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1018 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1019 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1020 struct sk_buff *skb;
3bf61c55 1021 int framesize;
d7699f87 1022
3bf61c55
GFT		 1023 rxdesc += idx;
1024 rxbi += idx;
d7699f87 1025
3bf61c55
GFT		 1026 skb = rxbi->skb;
1027 pci_dma_sync_single_for_cpu(jme->pdev,
1028 rxbi->mapping,
1029 rxbi->len,
1030 PCI_DMA_FROMDEVICE);
1031
cd0ff491 1032 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1033 pci_dma_sync_single_for_device(jme->pdev,
1034 rxbi->mapping,
1035 rxbi->len,
1036 PCI_DMA_FROMDEVICE);
1037
1038 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1039 } else {
3bf61c55
GFT		 1040 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1041 - RX_PREPAD_SIZE;
1042
1043 skb_reserve(skb, RX_PREPAD_SIZE);
1044 skb_put(skb, framesize);
1045 skb->protocol = eth_type_trans(skb, jme->dev);
1046
a452eef1 1047 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1048 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1049 else
97984ab7 1050 skb_checksum_none_assert(skb);
8c198884 1051
94c5ea02 1052 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1053 if (jme->vlgrp) {
cdcdc9eb 1054 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 1055 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1056 NET_STAT(jme).rx_bytes += 4;
c97b5740 1057 } else {
c97b5740 1058 dev_kfree_skb(skb);
b3821cc5 1059 }
cd0ff491 1060 } else {
cdcdc9eb 1061 jme->jme_rx(skb);
b3821cc5 1062 }
3bf61c55 1063
94c5ea02
GFT		 1064 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1065 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1066 ++(NET_STAT(jme).multicast);
1067
3bf61c55
GFT		 1068 NET_STAT(jme).rx_bytes += framesize;
1069 ++(NET_STAT(jme).rx_packets);
1070 }
1071
1072 jme_set_clean_rxdesc(jme, idx);
1073
1074}
1075
1076static int
1077jme_process_receive(struct jme_adapter *jme, int limit)
1078{
1079 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1080 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1081 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1082
cd0ff491 1083 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1084 goto out_inc;
1085
cd0ff491 1086 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1087 goto out_inc;
1088
cd0ff491 1089 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1090 goto out_inc;
1091
cdcdc9eb 1092 i = atomic_read(&rxring->next_to_clean);
fa97b924 1093 while (limit > 0) {
3bf61c55
GFT		 1094 rxdesc = rxring->desc;
1095 rxdesc += i;
1096
94c5ea02 1097 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1098 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1099 goto out;
fa97b924 1100 --limit;
d7699f87 1101
1a7a122d 1102 rmb();
4330c2f2
GFT		 1103 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1104
cd0ff491 1105 if (unlikely(desccnt > 1 ||
192570e0 1106 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1107
cd0ff491 1108 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1109 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1110 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1111 ++(NET_STAT(jme).rx_fifo_errors);
1112 else
1113 ++(NET_STAT(jme).rx_errors);
4330c2f2 1114
cd0ff491 1115 if (desccnt > 1)
3bf61c55 1116 limit -= desccnt - 1;
4330c2f2 1117
cd0ff491 1118 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1119 jme_set_clean_rxdesc(jme, j);
b3821cc5 1120 j = (j + 1) & (mask);
4330c2f2 1121 }
3bf61c55 1122
cd0ff491 1123 } else {
42b1055e 1124 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1125 }
4330c2f2 1126
b3821cc5 1127 i = (i + desccnt) & (mask);
3bf61c55 1128 }
4330c2f2 1129
3bf61c55 1130out:
cdcdc9eb 1131 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1132
192570e0
GFT		 1133out_inc:
1134 atomic_inc(&jme->rx_cleaning);
1135
3bf61c55 1136 return limit > 0 ? limit : 0;
4330c2f2 1137
3bf61c55 1138}
d7699f87 1139
79ce639c
GFT		 1140static void
1141jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1142{
cd0ff491 1143 if (likely(atmp == dpi->cur)) {
192570e0 1144 dpi->cnt = 0;
79ce639c 1145 return;
192570e0 1146 }
79ce639c 1147
cd0ff491 1148 if (dpi->attempt == atmp) {
79ce639c 1149 ++(dpi->cnt);
cd0ff491 1150 } else {
79ce639c
GFT		 1151 dpi->attempt = atmp;
1152 dpi->cnt = 0;
1153 }
1154
1155}
1156
1157static void
1158jme_dynamic_pcc(struct jme_adapter *jme)
1159{
1160 register struct dynpcc_info *dpi = &(jme->dpi);
1161
cd0ff491 1162 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1163 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT		 1164 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1165 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1166 jme_attempt_pcc(dpi, PCC_P2);
1167 else
1168 jme_attempt_pcc(dpi, PCC_P1);
1169
cd0ff491
GFT		 1170 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1171 if (dpi->attempt < dpi->cur)
1172 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1173 jme_set_rx_pcc(jme, dpi->attempt);
1174 dpi->cur = dpi->attempt;
1175 dpi->cnt = 0;
1176 }
1177}
1178
1179static void
1180jme_start_pcc_timer(struct jme_adapter *jme)
1181{
1182 struct dynpcc_info *dpi = &(jme->dpi);
1183 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1184 dpi->last_pkts = NET_STAT(jme).rx_packets;
1185 dpi->intr_cnt = 0;
1186 jwrite32(jme, JME_TMCSR,
1187 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1188}
1189
cd0ff491 1190static inline void
29bdd921
GFT		 1191jme_stop_pcc_timer(struct jme_adapter *jme)
1192{
1193 jwrite32(jme, JME_TMCSR, 0);
1194}
1195
cd0ff491
GFT		 1196static void
1197jme_shutdown_nic(struct jme_adapter *jme)
1198{
1199 u32 phylink;
1200
1201 phylink = jme_linkstat_from_phy(jme);
1202
1203 if (!(phylink & PHY_LINK_UP)) {
1204 /*
1205 * Disable all interrupt before issue timer
1206 */
1207 jme_stop_irq(jme);
1208 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1209 }
1210}
1211
79ce639c
GFT		 1212static void
1213jme_pcc_tasklet(unsigned long arg)
1214{
cd0ff491 1215 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1216 struct net_device *netdev = jme->dev;
1217
cd0ff491
GFT		 1218 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1219 jme_shutdown_nic(jme);
1220 return;
1221 }
29bdd921 1222
cd0ff491 1223 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1224 (atomic_read(&jme->link_changing) != 1)
1225 )) {
1226 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1227 return;
1228 }
29bdd921 1229
cd0ff491 1230 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1231 jme_dynamic_pcc(jme);
1232
79ce639c
GFT		 1233 jme_start_pcc_timer(jme);
1234}
1235
cd0ff491 1236static inline void
192570e0
GFT		 1237jme_polling_mode(struct jme_adapter *jme)
1238{
1239 jme_set_rx_pcc(jme, PCC_OFF);
1240}
1241
cd0ff491 1242static inline void
192570e0
GFT		 1243jme_interrupt_mode(struct jme_adapter *jme)
1244{
1245 jme_set_rx_pcc(jme, PCC_P1);
1246}
1247
cd0ff491
GFT		 1248static inline int
1249jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1250{
1251 u32 apmc;
1252 apmc = jread32(jme, JME_APMC);
1253 return apmc & JME_APMC_PSEUDO_HP_EN;
1254}
1255
1256static void
1257jme_start_shutdown_timer(struct jme_adapter *jme)
1258{
1259 u32 apmc;
1260
1261 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1262 apmc &= ~JME_APMC_EPIEN_CTRL;
1263 if (!no_extplug) {
1264 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1265 wmb();
1266 }
1267 jwrite32f(jme, JME_APMC, apmc);
1268
1269 jwrite32f(jme, JME_TIMER2, 0);
1270 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1271 jwrite32(jme, JME_TMCSR,
1272 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1273}
1274
1275static void
1276jme_stop_shutdown_timer(struct jme_adapter *jme)
1277{
1278 u32 apmc;
1279
1280 jwrite32f(jme, JME_TMCSR, 0);
1281 jwrite32f(jme, JME_TIMER2, 0);
1282 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1283
1284 apmc = jread32(jme, JME_APMC);
1285 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1286 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1287 wmb();
1288 jwrite32f(jme, JME_APMC, apmc);
1289}
1290
3bf61c55
GFT		 1291static void
1292jme_link_change_tasklet(unsigned long arg)
1293{
cd0ff491 1294 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1295 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1296 int rc;
1297
cd0ff491
GFT		 1298 while (!atomic_dec_and_test(&jme->link_changing)) {
1299 atomic_inc(&jme->link_changing);
52a46ba8 1300 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
e882564f 1301 while (atomic_read(&jme->link_changing) != 1)
52a46ba8 1302 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1303 }
fcf45b4c 1304
cd0ff491 1305 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1306 goto out;
1307
29bdd921 1308 jme->old_mtu = netdev->mtu;
fcf45b4c 1309 netif_stop_queue(netdev);
cd0ff491
GFT		 1310 if (jme_pseudo_hotplug_enabled(jme))
1311 jme_stop_shutdown_timer(jme);
1312
1313 jme_stop_pcc_timer(jme);
1314 tasklet_disable(&jme->txclean_task);
1315 tasklet_disable(&jme->rxclean_task);
1316 tasklet_disable(&jme->rxempty_task);
1317
1318 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1319 jme_disable_rx_engine(jme);
1320 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1321 jme_reset_mac_processor(jme);
1322 jme_free_rx_resources(jme);
1323 jme_free_tx_resources(jme);
192570e0 1324
cd0ff491 1325 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1326 jme_polling_mode(jme);
cd0ff491
GFT		 1327
1328 netif_carrier_off(netdev);
fcf45b4c
GFT		 1329 }
1330
1331 jme_check_link(netdev, 0);
cd0ff491 1332 if (netif_carrier_ok(netdev)) {
fcf45b4c 1333 rc = jme_setup_rx_resources(jme);
cd0ff491 1334 if (rc) {
52a46ba8 1335 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1336 goto out_enable_tasklet;
fcf45b4c
GFT		 1337 }
1338
fcf45b4c 1339 rc = jme_setup_tx_resources(jme);
cd0ff491 1340 if (rc) {
52a46ba8 1341 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1342 goto err_out_free_rx_resources;
1343 }
1344
1345 jme_enable_rx_engine(jme);
1346 jme_enable_tx_engine(jme);
1347
1348 netif_start_queue(netdev);
192570e0 1349
cd0ff491 1350 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1351 jme_interrupt_mode(jme);
192570e0 1352
79ce639c 1353 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1354 } else if (jme_pseudo_hotplug_enabled(jme)) {
1355 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1356 }
1357
cd0ff491 1358 goto out_enable_tasklet;
fcf45b4c
GFT		 1359
1360err_out_free_rx_resources:
1361 jme_free_rx_resources(jme);
cd0ff491
GFT		 1362out_enable_tasklet:
1363 tasklet_enable(&jme->txclean_task);
1364 tasklet_hi_enable(&jme->rxclean_task);
1365 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1366out:
1367 atomic_inc(&jme->link_changing);
3bf61c55 1368}
d7699f87 1369
3bf61c55
GFT		 1370static void
1371jme_rx_clean_tasklet(unsigned long arg)
1372{
cd0ff491 1373 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1374 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1375
192570e0
GFT		 1376 jme_process_receive(jme, jme->rx_ring_size);
1377 ++(dpi->intr_cnt);
42b1055e 1378
192570e0 1379}
fcf45b4c 1380
192570e0 1381static int
cdcdc9eb 1382jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1383{
cdcdc9eb 1384 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1385 int rest;
fcf45b4c 1386
cdcdc9eb 1387 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1388
cd0ff491 1389 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1390 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1391 ++(NET_STAT(jme).rx_dropped);
1392 jme_restart_rx_engine(jme);
1393 }
1394 atomic_inc(&jme->rx_empty);
1395
cd0ff491 1396 if (rest) {
cdcdc9eb 1397 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1398 jme_interrupt_mode(jme);
1399 }
1400
cdcdc9eb
GFT		 1401 JME_NAPI_WEIGHT_SET(budget, rest);
1402 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1403}
1404
1405static void
1406jme_rx_empty_tasklet(unsigned long arg)
1407{
cd0ff491 1408 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1409
cd0ff491 1410 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1411 return;
1412
cd0ff491 1413 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1414 return;
1415
c97b5740 1416 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1417
fcf45b4c 1418 jme_rx_clean_tasklet(arg);
cdcdc9eb 1419
cd0ff491 1420 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1421 atomic_dec(&jme->rx_empty);
1422 ++(NET_STAT(jme).rx_dropped);
1423 jme_restart_rx_engine(jme);
1424 }
1425 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1426}
1427
b3821cc5
GFT		 1428static void
1429jme_wake_queue_if_stopped(struct jme_adapter *jme)
1430{
fa97b924 1431 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1432
1433 smp_wmb();
cd0ff491 1434 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1435 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
52a46ba8 1436 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1437 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1438 }
1439
1440}
1441
3bf61c55
GFT		 1442static void
1443jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1444{
cd0ff491 1445 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1446 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1447 struct txdesc *txdesc = txring->desc;
3bf61c55 1448 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1449 int i, j, cnt = 0, max, err, mask;
3bf61c55 1450
52a46ba8 1451 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1452
1453 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1454 goto out;
1455
cd0ff491 1456 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1457 goto out;
1458
cd0ff491 1459 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1460 goto out;
1461
b3821cc5
GFT		 1462 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1463 mask = jme->tx_ring_mask;
3bf61c55 1464
cd0ff491 1465 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1466
1467 ctxbi = txbi + i;
1468
cd0ff491 1469 if (likely(ctxbi->skb &&
b3821cc5 1470 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1471
cd0ff491 1472 tx_dbg(jme, "txclean: %d+%d@%lu\n",
52a46ba8 1473 i, ctxbi->nr_desc, jiffies);
3bf61c55 1474
cd0ff491 1475 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1476
cd0ff491 1477 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1478 ttxbi = txbi + ((i + j) & (mask));
1479 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1480
b3821cc5 1481 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1482 ttxbi->mapping,
1483 ttxbi->len,
1484 PCI_DMA_TODEVICE);
1485
3bf61c55
GFT		 1486 ttxbi->mapping = 0;
1487 ttxbi->len = 0;
1488 }
1489
1490 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1491
1492 cnt += ctxbi->nr_desc;
1493
cd0ff491 1494 if (unlikely(err)) {
8c198884 1495 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1496 } else {
8c198884 1497 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1498 NET_STAT(jme).tx_bytes += ctxbi->len;
1499 }
1500
1501 ctxbi->skb = NULL;
1502 ctxbi->len = 0;
cdcdc9eb 1503 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1504
1505 } else {
3bf61c55
GFT		 1506 break;
1507 }
1508
b3821cc5 1509 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1510
1511 ctxbi->nr_desc = 0;
d7699f87
GFT		 1512 }
1513
52a46ba8 1514 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1515 atomic_set(&txring->next_to_clean, i);
79ce639c 1516 atomic_add(cnt, &txring->nr_free);
3bf61c55 1517
b3821cc5
GFT		 1518 jme_wake_queue_if_stopped(jme);
1519
fcf45b4c
GFT		 1520out:
1521 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1522}
1523
79ce639c 1524static void
cd0ff491 1525jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1526{
3bf61c55
GFT		 1527 /*
1528 * Disable interrupt
1529 */
1530 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1531
cd0ff491 1532 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1533 /*
1534 * Link change event is critical
1535 * all other events are ignored
1536 */
1537 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1538 tasklet_schedule(&jme->linkch_task);
29bdd921 1539 goto out_reenable;
fcf45b4c 1540 }
d7699f87 1541
cd0ff491 1542 if (intrstat & INTR_TMINTR) {
47220951 1543 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1544 tasklet_schedule(&jme->pcc_task);
47220951 1545 }
79ce639c 1546
cd0ff491 1547 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1548 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1549 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1550 }
1551
cd0ff491 1552 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1553 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1554 INTR_PCCRX0 |
1555 INTR_RX0EMP)) |
1556 INTR_RX0);
1557 }
d7699f87 1558
cd0ff491
GFT		 1559 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1560 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1561 atomic_inc(&jme->rx_empty);
1562
cd0ff491
GFT		 1563 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1564 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1565 jme_polling_mode(jme);
cdcdc9eb 1566 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1567 }
1568 }
cd0ff491
GFT		 1569 } else {
1570 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1571 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1572 tasklet_hi_schedule(&jme->rxempty_task);
1573 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1574 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1575 }
4330c2f2 1576 }
d7699f87 1577
29bdd921 1578out_reenable:
3bf61c55 1579 /*
fcf45b4c 1580 * Re-enable interrupt
3bf61c55 1581 */
fcf45b4c 1582 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1583}
1584
1585static irqreturn_t
1586jme_intr(int irq, void *dev_id)
1587{
cd0ff491
GFT		 1588 struct net_device *netdev = dev_id;
1589 struct jme_adapter *jme = netdev_priv(netdev);
1590 u32 intrstat;
79ce639c
GFT		 1591
1592 intrstat = jread32(jme, JME_IEVE);
1593
1594 /*
1595 * Check if it's really an interrupt for us
1596 */
9b9d55de 1597 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1598 return IRQ_NONE;
79ce639c
GFT		 1599
1600 /*
1601 * Check if the device still exist
1602 */
cd0ff491
GFT		 1603 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1604 return IRQ_NONE;
79ce639c
GFT		 1605
1606 jme_intr_msi(jme, intrstat);
1607
cd0ff491 1608 return IRQ_HANDLED;
d7699f87
GFT		 1609}
1610
79ce639c
GFT		 1611static irqreturn_t
1612jme_msi(int irq, void *dev_id)
1613{
cd0ff491
GFT		 1614 struct net_device *netdev = dev_id;
1615 struct jme_adapter *jme = netdev_priv(netdev);
1616 u32 intrstat;
79ce639c 1617
fa97b924 1618 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1619
1620 jme_intr_msi(jme, intrstat);
1621
cd0ff491 1622 return IRQ_HANDLED;
79ce639c
GFT		 1623}
1624
79ce639c
GFT		 1625static void
1626jme_reset_link(struct jme_adapter *jme)
1627{
1628 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1629}
1630
fcf45b4c
GFT		 1631static void
1632jme_restart_an(struct jme_adapter *jme)
1633{
cd0ff491 1634 u32 bmcr;
fcf45b4c 1635
cd0ff491 1636 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1637 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1638 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1639 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1640 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1641}
1642
1643static int
1644jme_request_irq(struct jme_adapter *jme)
1645{
1646 int rc;
cd0ff491
GFT		 1647 struct net_device *netdev = jme->dev;
1648 irq_handler_t handler = jme_intr;
1649 int irq_flags = IRQF_SHARED;
1650
1651 if (!pci_enable_msi(jme->pdev)) {
1652 set_bit(JME_FLAG_MSI, &jme->flags);
1653 handler = jme_msi;
1654 irq_flags = 0;
1655 }
1656
1657 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1658 netdev);
1659 if (rc) {
52a46ba8
JP		 1660 netdev_err(netdev,
1661 "Unable to request %s interrupt (return: %d)\n",
1662 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1663 rc);
79ce639c 1664
cd0ff491
GFT		 1665 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1666 pci_disable_msi(jme->pdev);
1667 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1668 }
cd0ff491 1669 } else {
79ce639c
GFT		 1670 netdev->irq = jme->pdev->irq;
1671 }
1672
cd0ff491 1673 return rc;
79ce639c
GFT		 1674}
1675
1676static void
1677jme_free_irq(struct jme_adapter *jme)
1678{
cd0ff491
GFT		 1679 free_irq(jme->pdev->irq, jme->dev);
1680 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1681 pci_disable_msi(jme->pdev);
1682 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1683 jme->dev->irq = jme->pdev->irq;
cd0ff491 1684 }
fcf45b4c
GFT		 1685}
1686
e4610a83
GFT		 1687static inline void
1688jme_new_phy_on(struct jme_adapter *jme)
1689{
1690 u32 reg;
1691
1692 reg = jread32(jme, JME_PHY_PWR);
1693 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1694 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1695 jwrite32(jme, JME_PHY_PWR, reg);
1696
1697 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1698 reg &= ~PE1_GPREG0_PBG;
1699 reg |= PE1_GPREG0_ENBG;
1700 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1701}
1702
1703static inline void
1704jme_new_phy_off(struct jme_adapter *jme)
1705{
1706 u32 reg;
1707
1708 reg = jread32(jme, JME_PHY_PWR);
1709 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1710 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1711 jwrite32(jme, JME_PHY_PWR, reg);
1712
1713 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1714 reg &= ~PE1_GPREG0_PBG;
1715 reg |= PE1_GPREG0_PDD3COLD;
1716 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1717}
1718
48db98f7
GFT		 1719static inline void
1720jme_phy_on(struct jme_adapter *jme)
1721{
1722 u32 bmcr;
1723
1724 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1725 bmcr &= ~BMCR_PDOWN;
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
e4610a83
GFT		 1727
1728 if (new_phy_power_ctrl(jme->chip_main_rev))
1729 jme_new_phy_on(jme);
1730}
1731
1732static inline void
1733jme_phy_off(struct jme_adapter *jme)
1734{
1735 u32 bmcr;
1736
1737 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1738 bmcr |= BMCR_PDOWN;
1739 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1740
1741 if (new_phy_power_ctrl(jme->chip_main_rev))
1742 jme_new_phy_off(jme);
48db98f7
GFT		 1743}
1744
3bf61c55
GFT		 1745static int
1746jme_open(struct net_device *netdev)
d7699f87
GFT		 1747{
1748 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1749 int rc;
79ce639c 1750
42b1055e 1751 jme_clear_pm(jme);
cdcdc9eb 1752 JME_NAPI_ENABLE(jme);
d7699f87 1753
fa97b924 1754 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1755 tasklet_enable(&jme->txclean_task);
1756 tasklet_hi_enable(&jme->rxclean_task);
1757 tasklet_hi_enable(&jme->rxempty_task);
1758
79ce639c 1759 rc = jme_request_irq(jme);
cd0ff491 1760 if (rc)
4330c2f2 1761 goto err_out;
79ce639c 1762
d7699f87 1763 jme_start_irq(jme);
42b1055e 1764
e4610a83
GFT		 1765 jme_phy_on(jme);
1766 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1767 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 1768 else
42b1055e
GFT		 1769 jme_reset_phy_processor(jme);
1770
29bdd921 1771 jme_reset_link(jme);
d7699f87
GFT		 1772
1773 return 0;
1774
d7699f87
GFT		 1775err_out:
1776 netif_stop_queue(netdev);
1777 netif_carrier_off(netdev);
4330c2f2 1778 return rc;
d7699f87
GFT		 1779}
1780
42b1055e
GFT		 1781static void
1782jme_set_100m_half(struct jme_adapter *jme)
1783{
cd0ff491 1784 u32 bmcr, tmp;
42b1055e 1785
fba4bc0c 1786 jme_phy_on(jme);
42b1055e
GFT		 1787 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1788 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1789 BMCR_SPEED1000 | BMCR_FULLDPLX);
1790 tmp |= BMCR_SPEED100;
1791
1792 if (bmcr != tmp)
1793 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1794
cd0ff491 1795 if (jme->fpgaver)
cdcdc9eb
GFT		 1796 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1797 else
1798 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1799}
1800
47220951
GFT		 1801#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1802static void
1803jme_wait_link(struct jme_adapter *jme)
1804{
cd0ff491 1805 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1806
1807 mdelay(1000);
1808 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1809 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1810 mdelay(10);
1811 phylink = jme_linkstat_from_phy(jme);
1812 }
1813}
1814
fba4bc0c
GFT		 1815static void
1816jme_powersave_phy(struct jme_adapter *jme)
1817{
1818 if (jme->reg_pmcs) {
1819 jme_set_100m_half(jme);
1820
1821 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1822 jme_wait_link(jme);
1823
1824 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1825 } else {
1826 jme_phy_off(jme);
1827 }
1828}
1829
3bf61c55
GFT		 1830static int
1831jme_close(struct net_device *netdev)
d7699f87
GFT		 1832{
1833 struct jme_adapter *jme = netdev_priv(netdev);
1834
1835 netif_stop_queue(netdev);
1836 netif_carrier_off(netdev);
1837
1838 jme_stop_irq(jme);
79ce639c 1839 jme_free_irq(jme);
d7699f87 1840
cdcdc9eb 1841 JME_NAPI_DISABLE(jme);
192570e0 1842
fa97b924
GFT		 1843 tasklet_disable(&jme->linkch_task);
1844 tasklet_disable(&jme->txclean_task);
1845 tasklet_disable(&jme->rxclean_task);
1846 tasklet_disable(&jme->rxempty_task);
8c198884 1847
cd0ff491
GFT		 1848 jme_disable_rx_engine(jme);
1849 jme_disable_tx_engine(jme);
8c198884 1850 jme_reset_mac_processor(jme);
d7699f87
GFT		 1851 jme_free_rx_resources(jme);
1852 jme_free_tx_resources(jme);
42b1055e 1853 jme->phylink = 0;
b3821cc5
GFT		 1854 jme_phy_off(jme);
1855
1856 return 0;
1857}
1858
1859static int
1860jme_alloc_txdesc(struct jme_adapter *jme,
1861 struct sk_buff *skb)
1862{
fa97b924 1863 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1864 int idx, nr_alloc, mask = jme->tx_ring_mask;
1865
1866 idx = txring->next_to_use;
1867 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1868
cd0ff491 1869 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1870 return -1;
1871
1872 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1873
b3821cc5
GFT		 1874 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1875
1876 return idx;
1877}
1878
1879static void
1880jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1881 struct txdesc *txdesc,
b3821cc5
GFT		 1882 struct jme_buffer_info *txbi,
1883 struct page *page,
cd0ff491
GFT		 1884 u32 page_offset,
1885 u32 len,
1886 u8 hidma)
b3821cc5
GFT		 1887{
1888 dma_addr_t dmaaddr;
1889
1890 dmaaddr = pci_map_page(pdev,
1891 page,
1892 page_offset,
1893 len,
1894 PCI_DMA_TODEVICE);
1895
1896 pci_dma_sync_single_for_device(pdev,
1897 dmaaddr,
1898 len,
1899 PCI_DMA_TODEVICE);
1900
1901 txdesc->dw[0] = 0;
1902 txdesc->dw[1] = 0;
1903 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1904 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1905 txdesc->desc2.datalen = cpu_to_le16(len);
1906 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1907 txdesc->desc2.bufaddrl = cpu_to_le32(
1908 (__u64)dmaaddr & 0xFFFFFFFFUL);
1909
1910 txbi->mapping = dmaaddr;
1911 txbi->len = len;
1912}
1913
1914static void
1915jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1916{
fa97b924 1917 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1918 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1919 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1920 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1921 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1922 int mask = jme->tx_ring_mask;
1923 struct skb_frag_struct *frag;
cd0ff491 1924 u32 len;
b3821cc5 1925
cd0ff491
GFT		 1926 for (i = 0 ; i < nr_frags ; ++i) {
1927 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1928 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1929 ctxbi = txbi + ((idx + i + 2) & (mask));
1930
1931 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1932 frag->page_offset, frag->size, hidma);
42b1055e 1933 }
b3821cc5 1934
cd0ff491 1935 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1936 ctxdesc = txdesc + ((idx + 1) & (mask));
1937 ctxbi = txbi + ((idx + 1) & (mask));
1938 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1939 offset_in_page(skb->data), len, hidma);
1940
1941}
1942
1943static int
1944jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1945{
cd0ff491 1946 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT		 1947 skb_header_cloned(skb) &&
1948 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1949 dev_kfree_skb(skb);
1950 return -1;
1951 }
1952
1953 return 0;
1954}
1955
1956static int
94c5ea02 1957jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1958{
94c5ea02 1959 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1960 if (*mss) {
b3821cc5
GFT		 1961 *flags |= TXFLAG_LSEN;
1962
cd0ff491 1963 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 1964 struct iphdr *iph = ip_hdr(skb);
1965
1966 iph->check = 0;
cd0ff491 1967 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 1968 iph->daddr, 0,
1969 IPPROTO_TCP,
1970 0);
cd0ff491 1971 } else {
b3821cc5
GFT		 1972 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1973
cd0ff491 1974 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 1975 &ip6h->daddr, 0,
1976 IPPROTO_TCP,
1977 0);
1978 }
1979
1980 return 0;
1981 }
1982
1983 return 1;
1984}
1985
1986static void
cd0ff491 1987jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1988{
cd0ff491
GFT		 1989 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1990 u8 ip_proto;
b3821cc5
GFT		 1991
1992 switch (skb->protocol) {
cd0ff491 1993 case htons(ETH_P_IP):
b3821cc5
GFT		 1994 ip_proto = ip_hdr(skb)->protocol;
1995 break;
cd0ff491 1996 case htons(ETH_P_IPV6):
b3821cc5
GFT		 1997 ip_proto = ipv6_hdr(skb)->nexthdr;
1998 break;
1999 default:
2000 ip_proto = 0;
2001 break;
2002 }
2003
cd0ff491 2004 switch (ip_proto) {
b3821cc5
GFT		 2005 case IPPROTO_TCP:
2006 *flags |= TXFLAG_TCPCS;
2007 break;
2008 case IPPROTO_UDP:
2009 *flags |= TXFLAG_UDPCS;
2010 break;
2011 default:
52a46ba8 2012 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2013 break;
2014 }
2015 }
2016}
2017
cd0ff491 2018static inline void
94c5ea02 2019jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2020{
cd0ff491 2021 if (vlan_tx_tag_present(skb)) {
b3821cc5 2022 *flags |= TXFLAG_TAGON;
94c5ea02 2023 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2024 }
b3821cc5
GFT		 2025}
2026
2027static int
94c5ea02 2028jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2029{
fa97b924 2030 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2031 struct txdesc *txdesc;
b3821cc5 2032 struct jme_buffer_info *txbi;
cd0ff491 2033 u8 flags;
b3821cc5 2034
cd0ff491 2035 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2036 txbi = txring->bufinf + idx;
2037
2038 txdesc->dw[0] = 0;
2039 txdesc->dw[1] = 0;
2040 txdesc->dw[2] = 0;
2041 txdesc->dw[3] = 0;
2042 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2043 /*
2044 * Set OWN bit at final.
2045 * When kernel transmit faster than NIC.
2046 * And NIC trying to send this descriptor before we tell
2047 * it to start sending this TX queue.
2048 * Other fields are already filled correctly.
2049 */
2050 wmb();
2051 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2052 /*
2053 * Set checksum flags while not tso
2054 */
2055 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2056 jme_tx_csum(jme, skb, &flags);
b3821cc5 2057 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 2058 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2059 txdesc->desc1.flags = flags;
2060 /*
2061 * Set tx buffer info after telling NIC to send
2062 * For better tx_clean timing
2063 */
2064 wmb();
2065 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2066 txbi->skb = skb;
2067 txbi->len = skb->len;
cd0ff491
GFT		 2068 txbi->start_xmit = jiffies;
2069 if (!txbi->start_xmit)
8d27293f 2070 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2071
2072 return 0;
2073}
2074
b3821cc5
GFT		 2075static void
2076jme_stop_queue_if_full(struct jme_adapter *jme)
2077{
fa97b924 2078 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2079 struct jme_buffer_info *txbi = txring->bufinf;
2080 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2081
cd0ff491 2082 txbi += idx;
b3821cc5
GFT		 2083
2084 smp_wmb();
cd0ff491 2085 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2086 netif_stop_queue(jme->dev);
52a46ba8 2087 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2088 smp_wmb();
cd0ff491
GFT		 2089 if (atomic_read(&txring->nr_free)
2090 >= (jme->tx_wake_threshold)) {
b3821cc5 2091 netif_wake_queue(jme->dev);
52a46ba8 2092 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2093 }
2094 }
2095
cd0ff491 2096 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2097 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2098 txbi->skb)) {
2099 netif_stop_queue(jme->dev);
52a46ba8
JP		 2100 netif_info(jme, tx_queued, jme->dev,
2101 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2102 }
b3821cc5
GFT		 2103}
2104
3bf61c55
GFT		 2105/*
2106 * This function is already protected by netif_tx_lock()
2107 */
cd0ff491 2108
c97b5740 2109static netdev_tx_t
3bf61c55 2110jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2111{
cd0ff491 2112 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2113 int idx;
d7699f87 2114
cd0ff491 2115 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2116 ++(NET_STAT(jme).tx_dropped);
2117 return NETDEV_TX_OK;
2118 }
2119
2120 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2121
cd0ff491 2122 if (unlikely(idx < 0)) {
b3821cc5 2123 netif_stop_queue(netdev);
52a46ba8
JP		 2124 netif_err(jme, tx_err, jme->dev,
2125 "BUG! Tx ring full when queue awake!\n");
d7699f87 2126
cd0ff491 2127 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2128 }
2129
94c5ea02 2130 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2131
4330c2f2
GFT		 2132 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2133 TXCS_SELECT_QUEUE0 |
2134 TXCS_QUEUE0S |
2135 TXCS_ENABLE);
d7699f87 2136
52a46ba8
JP		 2137 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2138 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2139 jme_stop_queue_if_full(jme);
2140
cd0ff491 2141 return NETDEV_TX_OK;
d7699f87
GFT		 2142}
2143
bb4c5c8c
GFT		 2144static void
2145jme_set_unicastaddr(struct net_device *netdev)
2146{
2147 struct jme_adapter *jme = netdev_priv(netdev);
2148 u32 val;
2149
2150 val = (netdev->dev_addr[3] & 0xff) << 24 |
2151 (netdev->dev_addr[2] & 0xff) << 16 |
2152 (netdev->dev_addr[1] & 0xff) << 8 |
2153 (netdev->dev_addr[0] & 0xff);
2154 jwrite32(jme, JME_RXUMA_LO, val);
2155 val = (netdev->dev_addr[5] & 0xff) << 8 |
2156 (netdev->dev_addr[4] & 0xff);
2157 jwrite32(jme, JME_RXUMA_HI, val);
2158}
2159
3bf61c55
GFT		 2160static int
2161jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2162{
cd0ff491 2163 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2164 struct sockaddr *addr = p;
d7699f87 2165
cd0ff491 2166 if (netif_running(netdev))
d7699f87
GFT		 2167 return -EBUSY;
2168
cd0ff491 2169 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2170 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
bb4c5c8c 2171 jme_set_unicastaddr(netdev);
cd0ff491 2172 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2173
2174 return 0;
2175}
2176
3bf61c55
GFT		 2177static void
2178jme_set_multi(struct net_device *netdev)
d7699f87 2179{
3bf61c55 2180 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2181 u32 mc_hash[2] = {};
d7699f87 2182
cd0ff491 2183 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2184
2185 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2186
cd0ff491 2187 if (netdev->flags & IFF_PROMISC) {
8c198884 2188 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2189 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2190 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2191 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2192 struct netdev_hw_addr *ha;
3bf61c55 2193 int bit_nr;
d7699f87 2194
8c198884 2195 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP		 2196 netdev_for_each_mc_addr(ha, netdev) {
2197 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT		 2198 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2199 }
d7699f87 2200
4330c2f2
GFT		 2201 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2202 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2203 }
2204
d7699f87 2205 wmb();
8c198884
GFT		 2206 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2207
cd0ff491 2208 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2209}
2210
3bf61c55 2211static int
8c198884 2212jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2213{
cd0ff491 2214 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2215
cd0ff491 2216 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2217 return 0;
2218
cd0ff491
GFT		 2219 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2220 ((new_mtu) < IPV6_MIN_MTU))
2221 return -EINVAL;
79ce639c 2222
cd0ff491 2223 if (new_mtu > 4000) {
79ce639c
GFT		 2224 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2225 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2226 jme_restart_rx_engine(jme);
cd0ff491 2227 } else {
79ce639c
GFT		 2228 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2229 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2230 jme_restart_rx_engine(jme);
2231 }
2232
cd0ff491 2233 netdev->mtu = new_mtu;
aa4d6a67
MM		 2234 netdev_update_features(netdev);
2235
cd0ff491 2236 jme_reset_link(jme);
79ce639c
GFT		 2237
2238 return 0;
d7699f87
GFT		 2239}
2240
8c198884
GFT		 2241static void
2242jme_tx_timeout(struct net_device *netdev)
2243{
cd0ff491 2244 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2245
cdcdc9eb
GFT		 2246 jme->phylink = 0;
2247 jme_reset_phy_processor(jme);
cd0ff491 2248 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2249 jme_set_settings(netdev, &jme->old_ecmd);
2250
8c198884 2251 /*
cdcdc9eb 2252 * Force to Reset the link again
8c198884 2253 */
29bdd921 2254 jme_reset_link(jme);
8c198884
GFT		 2255}
2256
f7f428e4
GFT		 2257static inline void jme_pause_rx(struct jme_adapter *jme)
2258{
2259 atomic_dec(&jme->link_changing);
2260
2261 jme_set_rx_pcc(jme, PCC_OFF);
2262 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2263 JME_NAPI_DISABLE(jme);
2264 } else {
2265 tasklet_disable(&jme->rxclean_task);
2266 tasklet_disable(&jme->rxempty_task);
2267 }
2268}
2269
2270static inline void jme_resume_rx(struct jme_adapter *jme)
2271{
2272 struct dynpcc_info *dpi = &(jme->dpi);
2273
2274 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2275 JME_NAPI_ENABLE(jme);
2276 } else {
2277 tasklet_hi_enable(&jme->rxclean_task);
2278 tasklet_hi_enable(&jme->rxempty_task);
2279 }
2280 dpi->cur = PCC_P1;
2281 dpi->attempt = PCC_P1;
2282 dpi->cnt = 0;
2283 jme_set_rx_pcc(jme, PCC_P1);
2284
2285 atomic_inc(&jme->link_changing);
2286}
2287
42b1055e
GFT		 2288static void
2289jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2290{
2291 struct jme_adapter *jme = netdev_priv(netdev);
2292
f7f428e4 2293 jme_pause_rx(jme);
42b1055e 2294 jme->vlgrp = grp;
f7f428e4 2295 jme_resume_rx(jme);
42b1055e
GFT		 2296}
2297
3bf61c55
GFT		 2298static void
2299jme_get_drvinfo(struct net_device *netdev,
2300 struct ethtool_drvinfo *info)
d7699f87 2301{
cd0ff491 2302 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2303
cd0ff491
GFT		 2304 strcpy(info->driver, DRV_NAME);
2305 strcpy(info->version, DRV_VERSION);
2306 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2307}
2308
8c198884
GFT		 2309static int
2310jme_get_regs_len(struct net_device *netdev)
2311{
cd0ff491 2312 return JME_REG_LEN;
8c198884
GFT		 2313}
2314
2315static void
cd0ff491 2316mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2317{
2318 int i;
2319
cd0ff491 2320 for (i = 0 ; i < len ; i += 4)
79ce639c 2321 p[i >> 2] = jread32(jme, reg + i);
186fc259 2322}
8c198884 2323
186fc259 2324static void
cd0ff491 2325mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2326{
2327 int i;
cd0ff491 2328 u16 *p16 = (u16 *)p;
186fc259 2329
cd0ff491 2330 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2331 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2332}
2333
2334static void
2335jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2336{
cd0ff491
GFT		 2337 struct jme_adapter *jme = netdev_priv(netdev);
2338 u32 *p32 = (u32 *)p;
8c198884 2339
186fc259 2340 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2341
2342 regs->version = 1;
2343 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2344
2345 p32 += 0x100 >> 2;
2346 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2347
2348 p32 += 0x100 >> 2;
2349 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2350
2351 p32 += 0x100 >> 2;
2352 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2353
186fc259
GFT		 2354 p32 += 0x100 >> 2;
2355 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2356}
2357
2358static int
2359jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2360{
2361 struct jme_adapter *jme = netdev_priv(netdev);
2362
8c198884
GFT		 2363 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2364 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2365
cd0ff491 2366 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2367 ecmd->use_adaptive_rx_coalesce = false;
2368 ecmd->rx_coalesce_usecs = 0;
2369 ecmd->rx_max_coalesced_frames = 0;
2370 return 0;
2371 }
2372
2373 ecmd->use_adaptive_rx_coalesce = true;
2374
cd0ff491 2375 switch (jme->dpi.cur) {
8c198884
GFT		 2376 case PCC_P1:
2377 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2378 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2379 break;
2380 case PCC_P2:
2381 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2382 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2383 break;
2384 case PCC_P3:
2385 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2386 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2387 break;
2388 default:
2389 break;
2390 }
2391
2392 return 0;
2393}
2394
192570e0
GFT		 2395static int
2396jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2397{
2398 struct jme_adapter *jme = netdev_priv(netdev);
2399 struct dynpcc_info *dpi = &(jme->dpi);
2400
cd0ff491 2401 if (netif_running(netdev))
cdcdc9eb
GFT		 2402 return -EBUSY;
2403
c97b5740
GFT		 2404 if (ecmd->use_adaptive_rx_coalesce &&
2405 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2406 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2407 jme->jme_rx = netif_rx;
2408 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2409 dpi->cur = PCC_P1;
2410 dpi->attempt = PCC_P1;
2411 dpi->cnt = 0;
2412 jme_set_rx_pcc(jme, PCC_P1);
2413 jme_interrupt_mode(jme);
c97b5740
GFT		 2414 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2415 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2416 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2417 jme->jme_rx = netif_receive_skb;
2418 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2419 jme_interrupt_mode(jme);
2420 }
2421
2422 return 0;
2423}
2424
8c198884
GFT		 2425static void
2426jme_get_pauseparam(struct net_device *netdev,
2427 struct ethtool_pauseparam *ecmd)
2428{
2429 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2430 u32 val;
8c198884
GFT		 2431
2432 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2433 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2434
cd0ff491
GFT		 2435 spin_lock_bh(&jme->phy_lock);
2436 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2437 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2438
2439 ecmd->autoneg =
2440 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2441}
2442
2443static int
2444jme_set_pauseparam(struct net_device *netdev,
2445 struct ethtool_pauseparam *ecmd)
2446{
2447 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2448 u32 val;
8c198884 2449
cd0ff491 2450 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2451 (ecmd->tx_pause != 0)) {
2452
cd0ff491 2453 if (ecmd->tx_pause)
8c198884
GFT		 2454 jme->reg_txpfc |= TXPFC_PF_EN;
2455 else
2456 jme->reg_txpfc &= ~TXPFC_PF_EN;
2457
2458 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2459 }
2460
cd0ff491
GFT		 2461 spin_lock_bh(&jme->rxmcs_lock);
2462 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2463 (ecmd->rx_pause != 0)) {
2464
cd0ff491 2465 if (ecmd->rx_pause)
8c198884
GFT		 2466 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2467 else
2468 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2469
2470 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2471 }
cd0ff491 2472 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2473
cd0ff491
GFT		 2474 spin_lock_bh(&jme->phy_lock);
2475 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2476 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2477 (ecmd->autoneg != 0)) {
2478
cd0ff491 2479 if (ecmd->autoneg)
8c198884
GFT		 2480 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2481 else
2482 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2483
b3821cc5
GFT		 2484 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2485 MII_ADVERTISE, val);
8c198884 2486 }
cd0ff491 2487 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2488
2489 return 0;
2490}
2491
29bdd921
GFT		 2492static void
2493jme_get_wol(struct net_device *netdev,
2494 struct ethtool_wolinfo *wol)
2495{
2496 struct jme_adapter *jme = netdev_priv(netdev);
2497
2498 wol->supported = WAKE_MAGIC | WAKE_PHY;
2499
2500 wol->wolopts = 0;
2501
cd0ff491 2502 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2503 wol->wolopts |= WAKE_PHY;
2504
cd0ff491 2505 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2506 wol->wolopts |= WAKE_MAGIC;
2507
2508}
2509
2510static int
2511jme_set_wol(struct net_device *netdev,
2512 struct ethtool_wolinfo *wol)
2513{
2514 struct jme_adapter *jme = netdev_priv(netdev);
2515
cd0ff491 2516 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2517 WAKE_UCAST |
2518 WAKE_MCAST |
2519 WAKE_BCAST |
2520 WAKE_ARP))
2521 return -EOPNOTSUPP;
2522
2523 jme->reg_pmcs = 0;
2524
cd0ff491 2525 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2526 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2527
cd0ff491 2528 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2529 jme->reg_pmcs |= PMCS_MFEN;
2530
cd0ff491 2531 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2532
8ad2ddac
RW		 2533 device_set_wakeup_enable(&jme->pdev->dev, jme->reg_pmcs);
2534
29bdd921
GFT		 2535 return 0;
2536}
b3821cc5 2537
3bf61c55
GFT		 2538static int
2539jme_get_settings(struct net_device *netdev,
2540 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2541{
2542 struct jme_adapter *jme = netdev_priv(netdev);
2543 int rc;
8c198884 2544
cd0ff491 2545 spin_lock_bh(&jme->phy_lock);
d7699f87 2546 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2547 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2548 return rc;
2549}
2550
3bf61c55
GFT		 2551static int
2552jme_set_settings(struct net_device *netdev,
2553 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2554{
2555 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2556 int rc, fdc = 0;
fcf45b4c 2557
035550c9
DD		 2558 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2559 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2560 return -EINVAL;
2561
f79361a6
GFT		 2562 /*
2563 * Check If user changed duplex only while force_media.
2564 * Hardware would not generate link change interrupt.
2565 */
cd0ff491 2566 if (jme->mii_if.force_media &&
79ce639c
GFT		 2567 ecmd->autoneg != AUTONEG_ENABLE &&
2568 (jme->mii_if.full_duplex != ecmd->duplex))
2569 fdc = 1;
2570
cd0ff491 2571 spin_lock_bh(&jme->phy_lock);
d7699f87 2572 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2573 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2574
cd0ff491 2575 if (!rc) {
f79361a6
GFT		 2576 if (fdc)
2577 jme_reset_link(jme);
29bdd921 2578 jme->old_ecmd = *ecmd;
43e4651b
GFT		 2579 set_bit(JME_FLAG_SSET, &jme->flags);
2580 }
2581
2582 return rc;
2583}
2584
2585static int
2586jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2587{
2588 int rc;
2589 struct jme_adapter *jme = netdev_priv(netdev);
2590 struct mii_ioctl_data *mii_data = if_mii(rq);
2591 unsigned int duplex_chg;
2592
2593 if (cmd == SIOCSMIIREG) {
2594 u16 val = mii_data->val_in;
2595 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2596 (val & BMCR_SPEED1000))
2597 return -EINVAL;
2598 }
2599
2600 spin_lock_bh(&jme->phy_lock);
2601 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2602 spin_unlock_bh(&jme->phy_lock);
2603
2604 if (!rc && (cmd == SIOCSMIIREG)) {
2605 if (duplex_chg)
2606 jme_reset_link(jme);
2607 jme_get_settings(netdev, &jme->old_ecmd);
2608 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2609 }
2610
d7699f87
GFT		 2611 return rc;
2612}
2613
cd0ff491 2614static u32
3bf61c55
GFT		 2615jme_get_link(struct net_device *netdev)
2616{
d7699f87
GFT		 2617 struct jme_adapter *jme = netdev_priv(netdev);
2618 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2619}
2620
8c198884 2621static u32
cd0ff491
GFT		 2622jme_get_msglevel(struct net_device *netdev)
2623{
2624 struct jme_adapter *jme = netdev_priv(netdev);
2625 return jme->msg_enable;
2626}
2627
2628static void
2629jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2630{
cd0ff491
GFT		 2631 struct jme_adapter *jme = netdev_priv(netdev);
2632 jme->msg_enable = value;
2633}
8c198884 2634
cd0ff491 2635static u32
aa4d6a67 2636jme_fix_features(struct net_device *netdev, u32 features)
cd0ff491 2637{
aa4d6a67
MM		 2638 if (netdev->mtu > 1900)
2639 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2640 return features;
8c198884
GFT		 2641}
2642
2643static int
aa4d6a67 2644jme_set_features(struct net_device *netdev, u32 features)
8c198884 2645{
cd0ff491 2646 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2647
cd0ff491 2648 spin_lock_bh(&jme->rxmcs_lock);
aa4d6a67 2649 if (features & NETIF_F_RXCSUM)
8c198884
GFT		 2650 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2651 else
2652 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2653 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2654 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2655
2656 return 0;
2657}
2658
8c198884
GFT		 2659static int
2660jme_nway_reset(struct net_device *netdev)
2661{
cd0ff491 2662 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2663 jme_restart_an(jme);
2664 return 0;
2665}
2666
cd0ff491 2667static u8
186fc259
GFT		 2668jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2669{
cd0ff491 2670 u32 val;
186fc259
GFT		 2671 int to;
2672
2673 val = jread32(jme, JME_SMBCSR);
2674 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2675 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2676 msleep(1);
2677 val = jread32(jme, JME_SMBCSR);
2678 }
cd0ff491 2679 if (!to) {
52a46ba8 2680 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2681 return 0xFF;
2682 }
2683
2684 jwrite32(jme, JME_SMBINTF,
2685 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2686 SMBINTF_HWRWN_READ |
2687 SMBINTF_HWCMD);
2688
2689 val = jread32(jme, JME_SMBINTF);
2690 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2691 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2692 msleep(1);
2693 val = jread32(jme, JME_SMBINTF);
2694 }
cd0ff491 2695 if (!to) {
52a46ba8 2696 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2697 return 0xFF;
2698 }
2699
2700 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2701}
2702
2703static void
cd0ff491 2704jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2705{
cd0ff491 2706 u32 val;
186fc259
GFT		 2707 int to;
2708
2709 val = jread32(jme, JME_SMBCSR);
2710 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2711 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2712 msleep(1);
2713 val = jread32(jme, JME_SMBCSR);
2714 }
cd0ff491 2715 if (!to) {
52a46ba8 2716 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2717 return;
2718 }
2719
2720 jwrite32(jme, JME_SMBINTF,
2721 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2722 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2723 SMBINTF_HWRWN_WRITE |
2724 SMBINTF_HWCMD);
2725
2726 val = jread32(jme, JME_SMBINTF);
2727 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2728 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2729 msleep(1);
2730 val = jread32(jme, JME_SMBINTF);
2731 }
cd0ff491 2732 if (!to) {
52a46ba8 2733 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2734 return;
2735 }
2736
2737 mdelay(2);
2738}
2739
2740static int
2741jme_get_eeprom_len(struct net_device *netdev)
2742{
cd0ff491
GFT		 2743 struct jme_adapter *jme = netdev_priv(netdev);
2744 u32 val;
186fc259 2745 val = jread32(jme, JME_SMBCSR);
cd0ff491 2746 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2747}
2748
2749static int
2750jme_get_eeprom(struct net_device *netdev,
2751 struct ethtool_eeprom *eeprom, u8 *data)
2752{
cd0ff491 2753 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2754 int i, offset = eeprom->offset, len = eeprom->len;
2755
2756 /*
8d27293f 2757 * ethtool will check the boundary for us
186fc259
GFT		 2758 */
2759 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2760 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2761 data[i] = jme_smb_read(jme, i + offset);
2762
2763 return 0;
2764}
2765
2766static int
2767jme_set_eeprom(struct net_device *netdev,
2768 struct ethtool_eeprom *eeprom, u8 *data)
2769{
cd0ff491 2770 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2771 int i, offset = eeprom->offset, len = eeprom->len;
2772
2773 if (eeprom->magic != JME_EEPROM_MAGIC)
2774 return -EINVAL;
2775
2776 /*
8d27293f 2777 * ethtool will check the boundary for us
186fc259 2778 */
cd0ff491 2779 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2780 jme_smb_write(jme, i + offset, data[i]);
2781
2782 return 0;
2783}
2784
d7699f87 2785static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2786 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2787 .get_regs_len = jme_get_regs_len,
2788 .get_regs = jme_get_regs,
2789 .get_coalesce = jme_get_coalesce,
192570e0 2790 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2791 .get_pauseparam = jme_get_pauseparam,
2792 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2793 .get_wol = jme_get_wol,
2794 .set_wol = jme_set_wol,
d7699f87
GFT		 2795 .get_settings = jme_get_settings,
2796 .set_settings = jme_set_settings,
2797 .get_link = jme_get_link,
cd0ff491
GFT		 2798 .get_msglevel = jme_get_msglevel,
2799 .set_msglevel = jme_set_msglevel,
8c198884 2800 .nway_reset = jme_nway_reset,
186fc259
GFT		 2801 .get_eeprom_len = jme_get_eeprom_len,
2802 .get_eeprom = jme_get_eeprom,
2803 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2804};
2805
3bf61c55
GFT		 2806static int
2807jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2808{
94c5ea02 2809 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2810 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2811 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT		 2812 return 1;
2813
94c5ea02 2814 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2815 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2816 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT		 2817 return 1;
2818
fa97b924
GFT		 2819 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2820 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT		 2821 return 0;
2822
2823 return -1;
2824}
2825
cd0ff491 2826static inline void
cdcdc9eb
GFT		 2827jme_phy_init(struct jme_adapter *jme)
2828{
cd0ff491 2829 u16 reg26;
cdcdc9eb
GFT		 2830
2831 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2832 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2833}
2834
cd0ff491 2835static inline void
cdcdc9eb 2836jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2837{
cd0ff491 2838 u32 chipmode;
cdcdc9eb
GFT		 2839
2840 chipmode = jread32(jme, JME_CHIPMODE);
2841
2842 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2843 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
4400ae98
GFT		 2844 jme->chip_main_rev = jme->chiprev & 0xF;
2845 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 2846}
2847
94c5ea02
GFT		 2848static const struct net_device_ops jme_netdev_ops = {
2849 .ndo_open = jme_open,
2850 .ndo_stop = jme_close,
2851 .ndo_validate_addr = eth_validate_addr,
43e4651b 2852 .ndo_do_ioctl = jme_ioctl,
94c5ea02
GFT		 2853 .ndo_start_xmit = jme_start_xmit,
2854 .ndo_set_mac_address = jme_set_macaddr,
2855 .ndo_set_multicast_list = jme_set_multi,
2856 .ndo_change_mtu = jme_change_mtu,
2857 .ndo_tx_timeout = jme_tx_timeout,
2858 .ndo_vlan_rx_register = jme_vlan_rx_register,
aa4d6a67
MM		 2859 .ndo_fix_features = jme_fix_features,
2860 .ndo_set_features = jme_set_features,
94c5ea02
GFT		 2861};
2862
3bf61c55
GFT		 2863static int __devinit
2864jme_init_one(struct pci_dev *pdev,
2865 const struct pci_device_id *ent)
2866{
cdcdc9eb 2867 int rc = 0, using_dac, i;
d7699f87
GFT		 2868 struct net_device *netdev;
2869 struct jme_adapter *jme;
cd0ff491
GFT		 2870 u16 bmcr, bmsr;
2871 u32 apmc;
d7699f87
GFT		 2872
2873 /*
2874 * set up PCI device basics
2875 */
4330c2f2 2876 rc = pci_enable_device(pdev);
cd0ff491 2877 if (rc) {
52a46ba8 2878 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 2879 goto err_out;
2880 }
d7699f87 2881
3bf61c55 2882 using_dac = jme_pci_dma64(pdev);
cd0ff491 2883 if (using_dac < 0) {
52a46ba8 2884 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 2885 rc = -EIO;
2886 goto err_out_disable_pdev;
2887 }
2888
cd0ff491 2889 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
52a46ba8 2890 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 2891 rc = -ENOMEM;
2892 goto err_out_disable_pdev;
2893 }
d7699f87 2894
4330c2f2 2895 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2896 if (rc) {
52a46ba8 2897 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 2898 goto err_out_disable_pdev;
2899 }
d7699f87
GFT		 2900
2901 pci_set_master(pdev);
2902
2903 /*
2904 * alloc and init net device
2905 */
3bf61c55 2906 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2907 if (!netdev) {
52a46ba8 2908 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 2909 rc = -ENOMEM;
2910 goto err_out_release_regions;
d7699f87 2911 }
94c5ea02 2912 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2913 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2914 netdev->watchdog_timeo = TX_TIMEOUT;
aa4d6a67
MM		 2915 netdev->hw_features = NETIF_F_IP_CSUM |
2916 NETIF_F_IPV6_CSUM |
2917 NETIF_F_SG |
2918 NETIF_F_TSO |
2919 NETIF_F_TSO6 |
2920 NETIF_F_RXCSUM;
9a08cd10
MM		 2921 netdev->features = NETIF_F_IP_CSUM |
2922 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 2923 NETIF_F_SG |
2924 NETIF_F_TSO |
2925 NETIF_F_TSO6 |
42b1055e
GFT		 2926 NETIF_F_HW_VLAN_TX |
2927 NETIF_F_HW_VLAN_RX;
cd0ff491 2928 if (using_dac)
8c198884 2929 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 2930
2931 SET_NETDEV_DEV(netdev, &pdev->dev);
2932 pci_set_drvdata(pdev, netdev);
2933
2934 /*
2935 * init adapter info
2936 */
2937 jme = netdev_priv(netdev);
2938 jme->pdev = pdev;
2939 jme->dev = netdev;
cdcdc9eb
GFT		 2940 jme->jme_rx = netif_rx;
2941 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2942 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2943 jme->phylink = 0;
b3821cc5
GFT		 2944 jme->tx_ring_size = 1 << 10;
2945 jme->tx_ring_mask = jme->tx_ring_size - 1;
2946 jme->tx_wake_threshold = 1 << 9;
2947 jme->rx_ring_size = 1 << 9;
2948 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2949 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 2950 jme->regs = ioremap(pci_resource_start(pdev, 0),
2951 pci_resource_len(pdev, 0));
4330c2f2 2952 if (!(jme->regs)) {
52a46ba8 2953 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 2954 rc = -ENOMEM;
2955 goto err_out_free_netdev;
2956 }
4330c2f2 2957
cd0ff491
GFT		 2958 if (no_pseudohp) {
2959 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2960 jwrite32(jme, JME_APMC, apmc);
2961 } else if (force_pseudohp) {
2962 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2963 jwrite32(jme, JME_APMC, apmc);
2964 }
2965
cdcdc9eb 2966 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2967
d7699f87 2968 spin_lock_init(&jme->phy_lock);
fcf45b4c 2969 spin_lock_init(&jme->macaddr_lock);
8c198884 2970 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2971
fcf45b4c
GFT		 2972 atomic_set(&jme->link_changing, 1);
2973 atomic_set(&jme->rx_cleaning, 1);
2974 atomic_set(&jme->tx_cleaning, 1);
192570e0 2975 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2976
79ce639c 2977 tasklet_init(&jme->pcc_task,
c97b5740 2978 jme_pcc_tasklet,
79ce639c 2979 (unsigned long) jme);
4330c2f2 2980 tasklet_init(&jme->linkch_task,
c97b5740 2981 jme_link_change_tasklet,
4330c2f2
GFT		 2982 (unsigned long) jme);
2983 tasklet_init(&jme->txclean_task,
c97b5740 2984 jme_tx_clean_tasklet,
4330c2f2
GFT		 2985 (unsigned long) jme);
2986 tasklet_init(&jme->rxclean_task,
c97b5740 2987 jme_rx_clean_tasklet,
4330c2f2 2988 (unsigned long) jme);
fcf45b4c 2989 tasklet_init(&jme->rxempty_task,
c97b5740 2990 jme_rx_empty_tasklet,
fcf45b4c 2991 (unsigned long) jme);
fa97b924 2992 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 2993 tasklet_disable_nosync(&jme->txclean_task);
2994 tasklet_disable_nosync(&jme->rxclean_task);
2995 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 2996 jme->dpi.cur = PCC_P1;
2997
cd0ff491 2998 jme->reg_ghc = 0;
79ce639c 2999 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3000 jme->reg_rxmcs = RXMCS_DEFAULT;
3001 jme->reg_txpfc = 0;
47220951 3002 jme->reg_pmcs = PMCS_MFEN;
ed830419 3003 jme->reg_gpreg1 = GPREG1_DEFAULT;
aa4d6a67
MM		 3004
3005 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3006 netdev->features |= NETIF_F_RXCSUM;
192570e0 3007
fcf45b4c
GFT		 3008 /*
3009 * Get Max Read Req Size from PCI Config Space
3010 */
cd0ff491
GFT		 3011 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3012 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3013 switch (jme->mrrs) {
3014 case MRRS_128B:
3015 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3016 break;
3017 case MRRS_256B:
3018 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3019 break;
3020 default:
3021 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3022 break;
06527f9b 3023 }
fcf45b4c 3024
d7699f87 3025 /*
cdcdc9eb 3026 * Must check before reset_mac_processor
d7699f87 3027 */
cdcdc9eb
GFT		 3028 jme_check_hw_ver(jme);
3029 jme->mii_if.dev = netdev;
cd0ff491 3030 if (jme->fpgaver) {
cdcdc9eb 3031 jme->mii_if.phy_id = 0;
cd0ff491 3032 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3033 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3034 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3035 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3036 jme->mii_if.phy_id = i;
3037 break;
3038 }
3039 }
3040
cd0ff491 3041 if (!jme->mii_if.phy_id) {
cdcdc9eb 3042 rc = -EIO;
52a46ba8
JP		 3043 pr_err("Can not find phy_id\n");
3044 goto err_out_unmap;
cdcdc9eb
GFT		 3045 }
3046
3047 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3048 } else {
cdcdc9eb
GFT		 3049 jme->mii_if.phy_id = 1;
3050 }
cd0ff491 3051 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3052 jme->mii_if.supports_gmii = true;
3053 else
3054 jme->mii_if.supports_gmii = false;
43e4651b
GFT		 3055 jme->mii_if.phy_id_mask = 0x1F;
3056 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3057 jme->mii_if.mdio_read = jme_mdio_read;
3058 jme->mii_if.mdio_write = jme_mdio_write;
3059
d7699f87 3060 jme_clear_pm(jme);
06168a20 3061 jme_set_phyfifo_5level(jme);
6db67aa5 3062 jme->pcirev = pdev->revision;
cd0ff491 3063 if (!jme->fpgaver)
cdcdc9eb 3064 jme_phy_init(jme);
42b1055e 3065 jme_phy_off(jme);
cdcdc9eb
GFT		 3066
3067 /*
3068 * Reset MAC processor and reload EEPROM for MAC Address
3069 */
d7699f87 3070 jme_reset_mac_processor(jme);
4330c2f2 3071 rc = jme_reload_eeprom(jme);
cd0ff491 3072 if (rc) {
52a46ba8 3073 pr_err("Reload eeprom for reading MAC Address error\n");
fa97b924 3074 goto err_out_unmap;
4330c2f2 3075 }
d7699f87
GFT		 3076 jme_load_macaddr(netdev);
3077
d7699f87
GFT		 3078 /*
3079 * Tell stack that we are not ready to work until open()
3080 */
3081 netif_carrier_off(netdev);
d7699f87 3082
4330c2f2 3083 rc = register_netdev(netdev);
cd0ff491 3084 if (rc) {
52a46ba8 3085 pr_err("Cannot register net device\n");
fa97b924 3086 goto err_out_unmap;
4330c2f2 3087 }
d7699f87 3088
4400ae98 3089 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
c97b5740
GFT		 3090 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3091 "JMC250 Gigabit Ethernet" :
3092 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3093 "JMC260 Fast Ethernet" : "Unknown",
3094 (jme->fpgaver != 0) ? " (FPGA)" : "",
3095 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
4400ae98 3096 jme->pcirev, netdev->dev_addr);
d7699f87
GFT		 3097
3098 return 0;
3099
3100err_out_unmap:
3101 iounmap(jme->regs);
3102err_out_free_netdev:
3103 pci_set_drvdata(pdev, NULL);
3104 free_netdev(netdev);
4330c2f2
GFT		 3105err_out_release_regions:
3106 pci_release_regions(pdev);
d7699f87 3107err_out_disable_pdev:
cd0ff491 3108 pci_disable_device(pdev);
d7699f87 3109err_out:
4330c2f2 3110 return rc;
d7699f87
GFT		 3111}
3112
3bf61c55
GFT		 3113static void __devexit
3114jme_remove_one(struct pci_dev *pdev)
3115{
d7699f87
GFT		 3116 struct net_device *netdev = pci_get_drvdata(pdev);
3117 struct jme_adapter *jme = netdev_priv(netdev);
3118
3119 unregister_netdev(netdev);
3120 iounmap(jme->regs);
3121 pci_set_drvdata(pdev, NULL);
3122 free_netdev(netdev);
3123 pci_release_regions(pdev);
3124 pci_disable_device(pdev);
3125
3126}
3127
fba4bc0c
GFT		 3128static void
3129jme_shutdown(struct pci_dev *pdev)
3130{
3131 struct net_device *netdev = pci_get_drvdata(pdev);
3132 struct jme_adapter *jme = netdev_priv(netdev);
3133
3134 jme_powersave_phy(jme);
3135 pci_pme_active(pdev, true);
3136}
3137
e10cd037 3138#ifdef CONFIG_PM_SLEEP
8ad2ddac 3139static int jme_suspend(struct device *dev)
29bdd921 3140{
8ad2ddac 3141 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT		 3142 struct net_device *netdev = pci_get_drvdata(pdev);
3143 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3144
3145 atomic_dec(&jme->link_changing);
3146
3147 netif_device_detach(netdev);
3148 netif_stop_queue(netdev);
3149 jme_stop_irq(jme);
29bdd921 3150
cd0ff491
GFT		 3151 tasklet_disable(&jme->txclean_task);
3152 tasklet_disable(&jme->rxclean_task);
3153 tasklet_disable(&jme->rxempty_task);
3154
cd0ff491
GFT		 3155 if (netif_carrier_ok(netdev)) {
3156 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3157 jme_polling_mode(jme);
3158
29bdd921 3159 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3160 jme_disable_rx_engine(jme);
3161 jme_disable_tx_engine(jme);
29bdd921
GFT		 3162 jme_reset_mac_processor(jme);
3163 jme_free_rx_resources(jme);
3164 jme_free_tx_resources(jme);
3165 netif_carrier_off(netdev);
3166 jme->phylink = 0;
3167 }
3168
cd0ff491
GFT		 3169 tasklet_enable(&jme->txclean_task);
3170 tasklet_hi_enable(&jme->rxclean_task);
3171 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3172
fba4bc0c 3173 jme_powersave_phy(jme);
29bdd921
GFT		 3174
3175 return 0;
3176}
3177
8ad2ddac 3178static int jme_resume(struct device *dev)
29bdd921 3179{
8ad2ddac 3180 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT		 3181 struct net_device *netdev = pci_get_drvdata(pdev);
3182 struct jme_adapter *jme = netdev_priv(netdev);
3183
8ad2ddac 3184 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
29bdd921 3185
e4610a83
GFT		 3186 jme_phy_on(jme);
3187 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3188 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 3189 else
29bdd921
GFT		 3190 jme_reset_phy_processor(jme);
3191
29bdd921
GFT		 3192 jme_start_irq(jme);
3193 netif_device_attach(netdev);
3194
3195 atomic_inc(&jme->link_changing);
3196
3197 jme_reset_link(jme);
3198
3199 return 0;
3200}
8ad2ddac
RW		 3201
3202static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3203#define JME_PM_OPS (&jme_pm_ops)
3204
3205#else
3206
3207#define JME_PM_OPS NULL
9b9d55de 3208#endif
29bdd921 3209
c97b5740 3210static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT		 3211 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3212 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3213 { }
3214};
3215
3216static struct pci_driver jme_driver = {
cd0ff491
GFT		 3217 .name = DRV_NAME,
3218 .id_table = jme_pci_tbl,
3219 .probe = jme_init_one,
3220 .remove = __devexit_p(jme_remove_one),
fba4bc0c 3221 .shutdown = jme_shutdown,
8ad2ddac 3222 .driver.pm = JME_PM_OPS,
d7699f87
GFT		 3223};
3224
3bf61c55
GFT		 3225static int __init
3226jme_init_module(void)
d7699f87 3227{
52a46ba8 3228 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3229 return pci_register_driver(&jme_driver);
3230}
3231
3bf61c55
GFT		 3232static void __exit
3233jme_cleanup_module(void)
d7699f87
GFT		 3234{
3235 pci_unregister_driver(&jme_driver);
3236}
3237
3238module_init(jme_init_module);
3239module_exit(jme_cleanup_module);
3240
3bf61c55 3241MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3242MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3243MODULE_LICENSE("GPL");
3244MODULE_VERSION(DRV_VERSION);
3245MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3246
JMicron Ethernet Linux driver