Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (21 commits)
  EDAC, MCE: Fix shift warning on 32-bit
  EDAC, MCE: Add a BIT_64() macro
  EDAC, MCE: Enable MCE decoding on F12h
  EDAC, MCE: Add F12h NB MCE decoder
  EDAC, MCE: Add F12h IC MCE decoder
  EDAC, MCE: Add F12h DC MCE decoder
  EDAC, MCE: Add support for F11h MCEs
  EDAC, MCE: Enable MCE decoding on F14h
  EDAC, MCE: Fix FR MCEs decoding
  EDAC, MCE: Complete NB MCE decoders
  EDAC, MCE: Warn about LS MCEs on F14h
  EDAC, MCE: Adjust IC decoders to F14h
  EDAC, MCE: Adjust DC decoders to F14h
  EDAC, MCE: Rename files
  EDAC, MCE: Rework MCE injection
  EDAC: Export edac sysfs class to users.
  EDAC, MCE: Pass complete MCE info to decoders
  EDAC, MCE: Sanitize error codes
  EDAC, MCE: Remove unused function parameter
  EDAC, MCE: Add HW_ERR prefix
  ...

diff --combined drivers/edac/Kconfig
index 734e2e062374aee94879e6d0bc5f981a6381c9dc,3bb3a671baa036b03e756e2bd0450f80911580d2..9dbb28b9559f7d794dd7f6899a5ff52056ce4017
--- 1/drivers/edac/Kconfig
--- 2/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@@ -39,7 -39,7 +39,7 @@@ config EDAC_DEBU
          there're four debug levels (x=0,1,2,3 from low to high).
          Usually you should select 'N'.
  
-  config EDAC_DECODE_MCE
+ config EDAC_DECODE_MCE
        tristate "Decode MCEs in human-readable form (only on AMD for now)"
        depends on CPU_SUP_AMD && X86_MCE
        default y
@@@ -51,6 -51,16 +51,16 @@@
          which occur really early upon boot, before the module infrastructure
          has been initialized.
  
+ config EDAC_MCE_INJ
+       tristate "Simple MCE injection interface over /sysfs"
+       depends on EDAC_DECODE_MCE
+       default n
+       help
+         This is a simple interface to inject MCEs over /sysfs and test
+         the MCE decoding code in EDAC.
+ 
+         This is currently AMD-only.
+ 
  config EDAC_MM_EDAC
        tristate "Main Memory EDAC (Error Detection And Correction) reporting"
        help
@@@ -66,13 -76,13 +76,13 @@@ config EDAC_MC
  
  config EDAC_AMD64
        tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
 -      depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
 +      depends on EDAC_MM_EDAC && AMD_NB && X86_64 && PCI && EDAC_DECODE_MCE
        help
          Support for error detection and correction on the AMD 64
          Families of Memory Controllers (K8, F10h and F11h)
  
  config EDAC_AMD64_ERROR_INJECTION
-       bool "Sysfs Error Injection facilities"
+       bool "Sysfs HW Error injection facilities"
        depends on EDAC_AMD64
        help
          Recent Opterons (Family 10h and later) provide for Memory Error

diff --combined drivers/edac/amd64_edac.c
index 09fcc5282327a163e46d50ec7323559eae60f58e,76f7cc0ee14977f8a940b24e4b19eaeb6888b8cf..8521401bbd751406e6f2752e10868f63c7e3b48a
--- 1/drivers/edac/amd64_edac.c
--- 2/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@@ -1,5 -1,5 +1,5 @@@
  #include "amd64_edac.h"
 -#include <asm/k8.h>
 +#include <asm/amd_nb.h>
  
  static struct edac_pci_ctl_info *amd64_ctl_pci;
  
@@@ -2073,11 -2073,18 +2073,18 @@@ static inline void __amd64_decode_bus_e
                amd64_handle_ue(mci, info);
  }
  
- void amd64_decode_bus_error(int node_id, struct err_regs *regs)
+ void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg)
  {
        struct mem_ctl_info *mci = mci_lookup[node_id];
+       struct err_regs regs;
  
-       __amd64_decode_bus_error(mci, regs);
+       regs.nbsl  = (u32) m->status;
+       regs.nbsh  = (u32)(m->status >> 32);
+       regs.nbeal = (u32) m->addr;
+       regs.nbeah = (u32)(m->addr >> 32);
+       regs.nbcfg = nbcfg;
+ 
+       __amd64_decode_bus_error(mci, &regs);
  
        /*
         * Check the UE bit of the NB status high register, if set generate some
@@@ -2086,7 -2093,7 +2093,7 @@@
         *
         * FIXME: this should go somewhere else, if at all.
         */
-       if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors)
+       if (regs.nbsh & K8_NBSH_UC_ERR && !report_gart_errors)
                edac_mc_handle_ue_no_info(mci, "UE bit is set");
  
  }
@@@ -2927,7 -2934,7 +2934,7 @@@ static int __init amd64_edac_init(void
         * to finish initialization of the MC instances.
         */
        err = -ENODEV;
 -      for (nb = 0; nb < num_k8_northbridges; nb++) {
 +      for (nb = 0; nb < k8_northbridges.num; nb++) {
                if (!pvt_lookup[nb])
                        continue;