]> bbs.cooldavid.org Git - net-next-2.6.git/commitdiff
Blackfin: BF54x: tweak DMAC MMR naming to match other ports
authorMike Frysinger <vapier@gentoo.org>
Thu, 29 Jul 2010 02:04:42 +0000 (02:04 +0000)
committerMike Frysinger <vapier@gentoo.org>
Fri, 6 Aug 2010 16:55:55 +0000 (12:55 -0400)
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h

index 32f71e6a7c15c52c268b81ded5904f9e0a7cc22d..ea3ec4ea9e2bc3e699fe8c6b8ece46109e6270e2 100644 (file)
 
 /* DMAC0 Registers */
 
-#define bfin_read_DMAC0_TCPER()                bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()                bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define bfin_read_DMAC0_TC_PER()               bfin_read16(DMAC0_TC_PER)
+#define bfin_write_DMAC0_TC_PER(val)   bfin_write16(DMAC0_TC_PER, val)
+#define bfin_read_DMAC0_TC_CNT()               bfin_read16(DMAC0_TC_CNT)
+#define bfin_write_DMAC0_TC_CNT(val)   bfin_write16(DMAC0_TC_CNT, val)
 
 /* DMA Channel 0 Registers */
 
 
 /* DMAC1 Registers */
 
-#define bfin_read_DMAC1_TCPER()                        bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)            bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()                        bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)            bfin_write16(DMAC1_TCCNT, val)
+#define bfin_read_DMAC1_TC_PER()                       bfin_read16(DMAC1_TC_PER)
+#define bfin_write_DMAC1_TC_PER(val)           bfin_write16(DMAC1_TC_PER, val)
+#define bfin_read_DMAC1_TC_CNT()                       bfin_read16(DMAC1_TC_CNT)
+#define bfin_write_DMAC1_TC_CNT(val)           bfin_write16(DMAC1_TC_CNT, val)
 
 /* DMA Channel 12 Registers */
 
index 01d52fade45e044c7a0d331925f6c875416f6caf..4b33b18de0bb2c5363ee42e5f8e878f1ecc98639 100644 (file)
 
 /* DMAC0 Registers */
 
-#define                      DMAC0_TCPER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
-#define                      DMAC0_TCCNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
+#define                     DMAC0_TC_PER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
+#define                     DMAC0_TC_CNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
 
 /* DMA Channel 0 Registers */
 
 
 /* DMAC1 Registers */
 
-#define                      DMAC1_TCPER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
-#define                      DMAC1_TCCNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
+#define                     DMAC1_TC_PER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
+#define                     DMAC1_TC_CNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
 
 /* DMA Channel 12 Registers */