Staging: brcm80211: remove BCMATTACHFN macro

[net-next-2.6.git] / drivers / staging / brcm80211 / util / nicpci.c

diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index 75bea1805db00d40701252c15c93e9b151cc5214..ff96948d7d77c4d35ea4613f60971abb8c96d106 100644 (file)
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -37,12 +37,12 @@ typedef struct {
 
        si_t *sih;              /* System interconnect handle */
        osl_t *osh;             /* OSL handle */
-       uint8 pciecap_lcreg_offset;     /* PCIE capability LCreg offset in the config space */
+       u8 pciecap_lcreg_offset;        /* PCIE capability LCreg offset in the config space */
        bool pcie_pr42767;
-       uint8 pcie_polarity;
-       uint8 pcie_war_aspm_ovr;        /* Override ASPM/Clkreq settings */
+       u8 pcie_polarity;
+       u8 pcie_war_aspm_ovr;   /* Override ASPM/Clkreq settings */
 
-       uint8 pmecap_offset;    /* PM Capability offset in the config space */
+       u8 pmecap_offset;       /* PM Capability offset in the config space */
        bool pmecap;            /* Capable of generating PME */
 } pcicore_info_t;
 
@@ -89,14 +89,14 @@ static bool pcicore_pmecap(pcicore_info_t *pi);
        (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff)
 
 #define write_pci_cfg_byte(a, val) do { \
-       uint32 tmpval; \
+       u32 tmpval; \
        tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \
                val << BYTE_POS(a); \
        OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
        } while (0)
 
 #define write_pci_cfg_word(a, val) do { \
-       uint32 tmpval; \
+       u32 tmpval; \
        tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \
                val << WORD_POS(a); \
        OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
@@ -128,7 +128,7 @@ void *pcicore_init(si_t *sih, osl_t *osh, void *regs)
        pi->osh = osh;
 
        if (sih->buscoretype == PCIE_CORE_ID) {
-               uint8 cap_ptr;
+               u8 cap_ptr;
                pi->regs.pcieregs = (sbpcieregs_t *) regs;
                cap_ptr =
                    pcicore_find_pci_capability(pi->osh, PCI_CAP_PCIECAP_ID,
@@ -152,14 +152,14 @@ void pcicore_deinit(void *pch)
 
 /* return cap_offset if requested capability exists in the PCI config space */
 /* Note that it's caller's responsibility to make sure it's a pci bus */
-uint8
-pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id, uchar *buf,
-                           uint32 *buflen)
+u8
+pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, unsigned char *buf,
+                           u32 *buflen)
 {
-       uint8 cap_id;
-       uint8 cap_ptr = 0;
-       uint32 bufsize;
-       uint8 byte_val;
+       u8 cap_id;
+       u8 cap_ptr = 0;
+       u32 bufsize;
+       u8 byte_val;
 
        /* check for Header type 0 */
        byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
@@ -191,7 +191,7 @@ pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id, uchar *buf,
        }
        /* found the caller requested capability */
        if ((buf != NULL) && (buflen != NULL)) {
-               uint8 cap_data;
+               u8 cap_data;
 
                bufsize = *buflen;
                if (!bufsize)
@@ -367,25 +367,25 @@ pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
 }
 
 /* ***** Support functions ***** */
-uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val)
+u8 pcie_clkreq(void *pch, u32 mask, u32 val)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
-       uint32 reg_val;
-       uint8 offset;
+       u32 reg_val;
+       u8 offset;
 
        offset = pi->pciecap_lcreg_offset;
        if (!offset)
                return 0;
 
-       reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
+       reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
        /* set operation */
        if (mask) {
                if (val)
                        reg_val |= PCIE_CLKREQ_ENAB;
                else
                        reg_val &= ~PCIE_CLKREQ_ENAB;
-               OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
-               reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
+               OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), reg_val);
+               reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
        }
        if (reg_val & PCIE_CLKREQ_ENAB)
                return 1;
@@ -395,7 +395,7 @@ uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val)
 
 static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
 {
-       uint32 w;
+       u32 w;
        si_t *sih = pi->sih;
        osl_t *osh = pi->osh;
        sbpcieregs_t *pcieregs = pi->regs.pcieregs;
@@ -426,10 +426,10 @@ static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
        case SI_PCIDOWN:
                if (sih->buscorerev == 6) {     /* turn on serdes PLL down */
                        si_corereg(sih, SI_CC_IDX,
-                                  OFFSETOF(chipcregs_t, chipcontrol_addr), ~0,
+                                  offsetof(chipcregs_t, chipcontrol_addr), ~0,
                                   0);
                        si_corereg(sih, SI_CC_IDX,
-                                  OFFSETOF(chipcregs_t, chipcontrol_data),
+                                  offsetof(chipcregs_t, chipcontrol_data),
                                   ~0x40, 0);
                } else if (pi->pcie_pr42767) {
                        pcie_clkreq((void *)pi, 1, 1);
@@ -438,10 +438,10 @@ static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
        case SI_PCIUP:
                if (sih->buscorerev == 6) {     /* turn off serdes PLL down */
                        si_corereg(sih, SI_CC_IDX,
-                                  OFFSETOF(chipcregs_t, chipcontrol_addr), ~0,
+                                  offsetof(chipcregs_t, chipcontrol_addr), ~0,
                                   0);
                        si_corereg(sih, SI_CC_IDX,
-                                  OFFSETOF(chipcregs_t, chipcontrol_data),
+                                  offsetof(chipcregs_t, chipcontrol_data),
                                   ~0x40, 0x40);
                } else if (PCIE_ASPM(sih)) {    /* disable clkreq */
                        pcie_clkreq((void *)pi, 1, 0);
@@ -457,7 +457,7 @@ static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
 /* Done only once at attach time */
 static void pcie_war_polarity(pcicore_info_t *pi)
 {
-       uint32 w;
+       u32 w;
 
        if (pi->pcie_polarity != 0)
                return;
@@ -484,8 +484,8 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
 {
        sbpcieregs_t *pcieregs = pi->regs.pcieregs;
        si_t *sih = pi->sih;
-       uint16 val16, *reg16;
-       uint32 w;
+       u16 val16, *reg16;
+       u32 w;
 
        if (!PCIE_ASPM(sih))
                return;
@@ -507,11 +507,11 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
                W_REG(pi->osh, reg16, val16);
 
                w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
-                                       sizeof(uint32));
+                                       sizeof(u32));
                w &= ~PCIE_ASPM_ENAB;
                w |= pi->pcie_war_aspm_ovr;
                OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
-                                    sizeof(uint32), w);
+                                    sizeof(u32), w);
        }
 
        reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
@@ -530,7 +530,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
 /* Needs to happen when coming out of 'standby'/'hibernate' */
 static void pcie_war_serdes(pcicore_info_t *pi)
 {
-       uint32 w = 0;
+       u32 w = 0;
 
        if (pi->pcie_polarity != 0)
                pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
@@ -548,7 +548,7 @@ static void pcie_war_serdes(pcicore_info_t *pi)
 static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi)
 {
        sbpcieregs_t *pcieregs = pi->regs.pcieregs;
-       uint16 val16, *reg16;
+       u16 val16, *reg16;
 
        reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
        val16 = R_REG(pi->osh, reg16);
@@ -564,12 +564,12 @@ static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi)
 static void pcie_war_noplldown(pcicore_info_t *pi)
 {
        sbpcieregs_t *pcieregs = pi->regs.pcieregs;
-       uint16 *reg16;
+       u16 *reg16;
 
        ASSERT(pi->sih->buscorerev == 7);
 
        /* turn off serdes PLL down */
-       si_corereg(pi->sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
+       si_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
                   CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
 
        /*  clear srom shadow backdoor */
@@ -583,7 +583,7 @@ static void pcie_war_pci_setup(pcicore_info_t *pi)
        si_t *sih = pi->sih;
        osl_t *osh = pi->osh;
        sbpcieregs_t *pcieregs = pi->regs.pcieregs;
-       uint32 w;
+       u32 w;
 
        if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
                w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
@@ -623,7 +623,7 @@ static void pcie_war_pci_setup(pcicore_info_t *pi)
                pcie_misc_config_fixup(pi);
 }
 
-void pcie_war_ovr_aspm_update(void *pch, uint8 aspm)
+void pcie_war_ovr_aspm_update(void *pch, u8 aspm)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
 
@@ -641,14 +641,14 @@ void pcie_war_ovr_aspm_update(void *pch, uint8 aspm)
 }
 
 /* ***** Functions called during driver state changes ***** */
-void BCMATTACHFN(pcicore_attach) (void *pch, char *pvars, int state)
+void pcicore_attach(void *pch, char *pvars, int state)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
        si_t *sih = pi->sih;
 
        /* Determine if this board needs override */
        if (PCIE_ASPM(sih)) {
-               if ((uint32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
+               if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
                        pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
                } else {
                        pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
@@ -693,15 +693,15 @@ void pcicore_up(void *pch, int state)
 void pcicore_sleep(void *pch)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
-       uint32 w;
+       u32 w;
 
        if (!pi || !PCIE_ASPM(pi->sih))
                return;
 
        w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
-                               sizeof(uint32));
+                               sizeof(u32));
        w &= ~PCIE_CAP_LCREG_ASPML1;
-       OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32),
+       OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(u32),
                             w);
 
        pi->pcie_pr42767 = FALSE;
@@ -724,8 +724,8 @@ void pcicore_down(void *pch, int state)
 /* Just uses PCI config accesses to find out, when needed before sb_attach is done */
 bool pcicore_pmecap_fast(osl_t *osh)
 {
-       uint8 cap_ptr;
-       uint32 pmecap;
+       u8 cap_ptr;
+       u32 pmecap;
 
        cap_ptr =
            pcicore_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID, NULL,
@@ -734,7 +734,7 @@ bool pcicore_pmecap_fast(osl_t *osh)
        if (!cap_ptr)
                return FALSE;
 
-       pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32));
+       pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(u32));
 
        return (pmecap & PME_CAP_PM_STATES) != 0;
 }
@@ -744,8 +744,8 @@ bool pcicore_pmecap_fast(osl_t *osh)
  */
 static bool pcicore_pmecap(pcicore_info_t *pi)
 {
-       uint8 cap_ptr;
-       uint32 pmecap;
+       u8 cap_ptr;
+       u32 pmecap;
 
        if (!pi->pmecap_offset) {
                cap_ptr =
@@ -759,7 +759,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi)
 
                pmecap =
                    OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset,
-                                       sizeof(uint32));
+                                       sizeof(u32));
 
                /* At least one state can generate PME */
                pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
@@ -772,17 +772,17 @@ static bool pcicore_pmecap(pcicore_info_t *pi)
 void pcicore_pmeen(void *pch)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
-       uint32 w;
+       u32 w;
 
        /* if not pmecapable return */
        if (!pcicore_pmecap(pi))
                return;
 
        w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
-                               sizeof(uint32));
+                               sizeof(u32));
        w |= (PME_CSR_PME_EN);
        OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
-                            sizeof(uint32), w);
+                            sizeof(u32), w);
 }
 
 /*
@@ -791,13 +791,13 @@ void pcicore_pmeen(void *pch)
 bool pcicore_pmestat(void *pch)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
-       uint32 w;
+       u32 w;
 
        if (!pcicore_pmecap(pi))
                return FALSE;
 
        w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
-                               sizeof(uint32));
+                               sizeof(u32));
 
        return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
 }
@@ -807,13 +807,13 @@ bool pcicore_pmestat(void *pch)
 void pcicore_pmeclr(void *pch)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
-       uint32 w;
+       u32 w;
 
        if (!pcicore_pmecap(pi))
                return;
 
        w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
-                               sizeof(uint32));
+                               sizeof(u32));
 
        PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
 
@@ -821,13 +821,13 @@ void pcicore_pmeclr(void *pch)
        w &= ~(PME_CSR_PME_EN);
 
        OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
-                            sizeof(uint32), w);
+                            sizeof(u32), w);
 }
 
-uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val)
+u32 pcie_lcreg(void *pch, u32 mask, u32 val)
 {
        pcicore_info_t *pi = (pcicore_info_t *) pch;
-       uint8 offset;
+       u8 offset;
 
        offset = pi->pciecap_lcreg_offset;
        if (!offset)
@@ -835,15 +835,15 @@ uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val)
 
        /* set operation */
        if (mask)
-               OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), val);
+               OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), val);
 
-       return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
+       return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
 }
 
-uint32
-pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type)
+u32
+pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
 {
-       uint32 reg_val = 0;
+       u32 reg_val = 0;
        pcicore_info_t *pi = (pcicore_info_t *) pch;
        sbpcieregs_t *pcieregs = pi->regs.pcieregs;
        osl_t *osh = pi->osh;
@@ -864,11 +864,11 @@ pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type)
        return reg_val;
 }
 
-uint32
-pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, uint32 mask,
-                     uint32 val)
+u32
+pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
+                     u32 val)
 {
-       uint32 reg_val = 0;
+       u32 reg_val = 0;
        pcicore_info_t *pi = (pcicore_info_t *) pch;
 
        if (mask) {