[INET]: local port range robustness

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 5c21f49026c9929507aab64083d6eb233e54d585..d8e829f6fcb2b8a5049a257b5b679cb861f64617 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -57,32 +57,7 @@
 #define TG3PCI_IRQ_PIN                 0x0000003d
 #define TG3PCI_MIN_GNT                 0x0000003e
 #define TG3PCI_MAX_LAT                 0x0000003f
-#define TG3PCI_X_CAPS                  0x00000040
-#define  PCIX_CAPS_RELAXED_ORDERING     0x00020000
-#define  PCIX_CAPS_SPLIT_MASK           0x00700000
-#define  PCIX_CAPS_SPLIT_SHIFT          20
-#define  PCIX_CAPS_BURST_MASK           0x000c0000
-#define  PCIX_CAPS_BURST_SHIFT          18
-#define  PCIX_CAPS_MAX_BURST_CPIOB      2
-#define TG3PCI_PM_CAP_PTR              0x00000041
-#define TG3PCI_X_COMMAND               0x00000042
-#define TG3PCI_X_STATUS                        0x00000044
-#define TG3PCI_PM_CAP_ID               0x00000048
-#define TG3PCI_VPD_CAP_PTR             0x00000049
-#define TG3PCI_PM_CAPS                 0x0000004a
-#define TG3PCI_PM_CTRL_STAT            0x0000004c
-#define TG3PCI_BR_SUPP_EXT             0x0000004e
-#define TG3PCI_PM_DATA                 0x0000004f
-#define TG3PCI_VPD_CAP_ID              0x00000050
-#define TG3PCI_MSI_CAP_PTR             0x00000051
-#define TG3PCI_VPD_ADDR_FLAG           0x00000052
-#define  VPD_ADDR_FLAG_WRITE           0x00008000
-#define TG3PCI_VPD_DATA                        0x00000054
-#define TG3PCI_MSI_CAP_ID              0x00000058
-#define TG3PCI_NXT_CAP_PTR             0x00000059
-#define TG3PCI_MSI_CTRL                        0x0000005a
-#define TG3PCI_MSI_ADDR_LOW            0x0000005c
-#define TG3PCI_MSI_ADDR_HIGH           0x00000060
+/* 0x40 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
 #define TG3PCI_MISC_HOST_CTRL          0x00000068
@@ -133,6 +108,7 @@
 #define  CHIPREV_ID_5752_A1             0x6001
 #define  CHIPREV_ID_5714_A2             0x9002
 #define  CHIPREV_ID_5906_A1             0xc001
+#define  CHIPREV_ID_5784_A0             0x5784000
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -146,6 +122,8 @@
 #define   ASIC_REV_5755                         0x0a
 #define   ASIC_REV_5787                         0x0b
 #define   ASIC_REV_5906                         0x0c
+#define   ASIC_REV_USE_PROD_ID_REG      0x0f
+#define   ASIC_REV_5784                         0x5784
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -239,7 +217,9 @@
 #define TG3PCI_DUAL_MAC_CTRL           0x000000b8
 #define  DUAL_MAC_CTRL_CH_MASK          0x00000003
 #define  DUAL_MAC_CTRL_ID               0x00000004
-/* 0xbc --> 0x100 unused */
+#define TG3PCI_PRODID_ASICREV          0x000000bc
+#define  PROD_ID_ASIC_REV_MASK          0x0fffffff
+/* 0xc0 --> 0x100 unused */
 
 /* 0x100 --> 0x200 unused */
 
@@ -865,7 +845,13 @@
 #define  RCVLSC_MODE_ATTN_ENABLE        0x00000004
 #define RCVLSC_STATUS                  0x00003404
 #define  RCVLSC_STATUS_ERROR_ATTN       0x00000004
-/* 0x3408 --> 0x3800 unused */
+/* 0x3408 --> 0x3600 unused */
+
+/* CPMU registers */
+#define TG3_CPMU_CTRL                  0x00003600
+#define  CPMU_CTRL_LINK_IDLE_MODE       0x00000200
+#define  CPMU_CTRL_LINK_AWARE_MODE      0x00000400
+/* 0x3604 --> 0x3800 unused */
 
 /* Mbuf cluster free registers */
 #define MBFREE_MODE                    0x00003800
@@ -1045,7 +1031,10 @@
 #define  RDMAC_MODE_FIFOOREAD_ENAB      0x00000100
 #define  RDMAC_MODE_LNGREAD_ENAB        0x00000200
 #define  RDMAC_MODE_SPLIT_ENABLE        0x00000800
+#define  RDMAC_MODE_BD_SBD_CRPT_ENAB    0x00000800
 #define  RDMAC_MODE_SPLIT_RESET                 0x00001000
+#define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB  0x00001000
+#define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB  0x00002000
 #define  RDMAC_MODE_FIFO_SIZE_128       0x00020000
 #define  RDMAC_MODE_FIFO_LONG_BURST     0x00030000
 #define RDMAC_STATUS                   0x00004804
@@ -2176,6 +2165,7 @@ struct tg3 {
        dma_addr_t                      tx_desc_mapping;
 
        /* begin "rx thread" cacheline section */
+       struct napi_struct              napi;
        void                            (*write32_rx_mbox) (struct tg3 *, u32,
                                                            u32);
        u32                             rx_rcb_ptr;
@@ -2237,7 +2227,7 @@ struct tg3 {
 #define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
-
+#define TG3_FLAG_CPMU_PRESENT          0x04000000
 #define TG3_FLAG_40BIT_DMA_BUG         0x08000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
 #define TG3_FLAG_SUPPORT_MSI           0x20000000
@@ -2309,7 +2299,7 @@ struct tg3 {
        u32                             pwrmgmt_thresh;
 
        /* PCI block */
-       u16                             pci_chip_rev_id;
+       u32                             pci_chip_rev_id;
        u8                              pci_cacheline_sz;
        u8                              pci_lat_timer;
        u8                              pci_hdr_type;
@@ -2317,6 +2307,7 @@ struct tg3 {
 
        int                             pm_cap;
        int                             msi_cap;
+       int                             pcix_cap;
 
        /* PHY info */
        u32                             phy_id;
@@ -2335,6 +2326,7 @@ struct tg3 {
 #define PHY_ID_BCM5755                 0xbc050cc0
 #define PHY_ID_BCM5787                 0xbc050ce0
 #define PHY_ID_BCM5756                 0xbc050ed0
+#define PHY_ID_BCM5784                 0xbc050fa0
 #define PHY_ID_BCM5906                 0xdc00ac40
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff