tg3: Create MII_TG3_FET namespace

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index b3347c41a1a3df0652b119cb3626407f2b71306d..b8339c9ae0e32eb4cdb082d763f069170a6e2d34 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -43,7 +43,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57780     0x1692
 #define  TG3PCI_DEVICE_TIGON3_57760     0x1690
 #define  TG3PCI_DEVICE_TIGON3_57790     0x1694
-#define  TG3PCI_DEVICE_TIGON3_57720     0x168c
+#define  TG3PCI_DEVICE_TIGON3_57788     0x1691
 /* 0x04 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
@@ -214,9 +214,11 @@
 #define  DUAL_MAC_CTRL_ID               0x00000004
 #define TG3PCI_PRODID_ASICREV          0x000000bc
 #define  PROD_ID_ASIC_REV_MASK          0x0fffffff
-/* 0xc0 --> 0x100 unused */
+/* 0xc0 --> 0x110 unused */
 
-/* 0x100 --> 0x200 unused */
+#define TG3_CORR_ERR_STAT              0x00000110
+#define  TG3_CORR_ERR_STAT_CLEAR       0xffffffff
+/* 0x114 --> 0x200 unused */
 
 /* Mailbox registers */
 #define MAILBOX_INTERRUPT_0            0x00000200 /* 64-bit */
@@ -522,6 +524,10 @@
 /* 0x598 --> 0x5a0 unused */
 #define MAC_PHYCFG1                    0x000005a0
 #define  MAC_PHYCFG1_RGMII_INT          0x00000001
+#define  MAC_PHYCFG1_RXCLK_TO_MASK      0x00001ff0
+#define  MAC_PHYCFG1_RXCLK_TIMEOUT      0x00001000
+#define  MAC_PHYCFG1_TXCLK_TO_MASK      0x01ff0000
+#define  MAC_PHYCFG1_TXCLK_TIMEOUT      0x01000000
 #define  MAC_PHYCFG1_RGMII_EXT_RX_DEC   0x02000000
 #define  MAC_PHYCFG1_RGMII_SND_STAT_EN  0x04000000
 #define  MAC_PHYCFG1_TXC_DRV            0x20000000
@@ -864,6 +870,7 @@
 #define  RCVLPC_STATSCTRL_ENABLE        0x00000001
 #define  RCVLPC_STATSCTRL_FASTUPD       0x00000002
 #define RCVLPC_STATS_ENABLE            0x00002018
+#define  RCVLPC_STATSENAB_ASF_FIX       0x00000002
 #define  RCVLPC_STATSENAB_DACK_FIX      0x00040000
 #define  RCVLPC_STATSENAB_LNGBRST_RFIX  0x00400000
 #define RCVLPC_STATS_INCMASK           0x0000201c
@@ -1696,11 +1703,23 @@
 #define PCIE_TRANSACTION_CFG           0x00007c04
 #define PCIE_TRANS_CFG_1SHOT_MSI        0x20000000
 #define PCIE_TRANS_CFG_LOM              0x00000020
+/* 0x7c08 --> 0x7d28 unused */
 
 #define PCIE_PWR_MGMT_THRESH           0x00007d28
 #define PCIE_PWR_MGMT_L1_THRESH_MSK     0x0000ff00
 #define PCIE_PWR_MGMT_L1_THRESH_4MS     0x0000ff00
 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN   0x01000000
+/* 0x7d2c --> 0x7d54 unused */
+
+#define TG3_PCIE_LNKCTL                        0x00007d54
+#define  TG3_PCIE_LNKCTL_L1_PLL_PD_EN   0x00000008
+#define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS  0x00000080
+/* 0x7d58 --> 0x7e70 unused */
+
+#define TG3_PCIE_EIDLE_DELAY           0x00007e70
+#define  TG3_PCIE_EIDLE_DELAY_MASK      0x0000001f
+#define  TG3_PCIE_EIDLE_DELAY_13_CLKS   0x0000000c
+/* 0x7e74 --> 0x8000 unused */
 
 
 /* OTP bit definitions */
@@ -1890,7 +1909,6 @@
 
 #define MII_TG3_DSP_RW_PORT            0x15 /* DSP coefficient read/write port */
 
-#define MII_TG3_EPHY_PTEST             0x17 /* 5906 PHY register */
 #define MII_TG3_DSP_ADDRESS            0x17 /* DSP address register */
 
 #define MII_TG3_DSP_TAP1               0x0001
@@ -1957,17 +1975,23 @@
 #define MII_TG3_MISC_SHDW_SCR5_LPED    0x0010
 #define MII_TG3_MISC_SHDW_SCR5_SEL     0x1400
 
-
-#define MII_TG3_EPHY_TEST              0x1f /* 5906 PHY register */
-#define MII_TG3_EPHY_SHADOW_EN         0x80
-
-#define MII_TG3_EPHYTST_MISCCTRL       0x10 /* 5906 EPHY misc ctrl shadow register */
-#define MII_TG3_EPHYTST_MISCCTRL_MDIX  0x4000
-
 #define MII_TG3_TEST1                  0x1e
 #define MII_TG3_TEST1_TRIM_EN          0x0010
 #define MII_TG3_TEST1_CRC_EN           0x8000
 
+
+/* Fast Ethernet Tranceiver definitions */
+#define MII_TG3_FET_PTEST              0x17
+#define MII_TG3_FET_TEST               0x1f
+#define  MII_TG3_FET_SHADOW_EN         0x0080
+
+#define MII_TG3_FET_SHDW_MISCCTRL      0x10
+#define  MII_TG3_FET_SHDW_MISCCTRL_MDIX        0x4000
+
+#define MII_TG3_FET_SHDW_AUXSTAT2      0x1b
+#define  MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
+
+
 /* APE registers.  Accessible through BAR1 */
 #define TG3_APE_EVENT                  0x000c
 #define  APE_EVENT_1                    0x00000001
@@ -2641,6 +2665,7 @@ struct tg3 {
 #define TG3_FLG3_PHY_ENABLE_APD                0x00001000
 #define TG3_FLG3_5755_PLUS             0x00002000
 #define TG3_FLG3_NO_NVRAM              0x00004000
+#define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000
 
        struct timer_list               timer;
        u16                             timer_counter;