Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/gregkh/driver...

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d48887d9032501413515a7b53fcb183737de490f..8de6f21037bae13910b0f9c8f075a8d38b89db69 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -125,6 +125,9 @@
 #define  CHIPREV_ID_5750_A0             0x4000
 #define  CHIPREV_ID_5750_A1             0x4001
 #define  CHIPREV_ID_5750_A3             0x4003
+#define  CHIPREV_ID_5752_A0_HW          0x5000
+#define  CHIPREV_ID_5752_A0             0x6000
+#define  CHIPREV_ID_5752_A1             0x6001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -132,6 +135,7 @@
 #define   ASIC_REV_5704                         0x02
 #define   ASIC_REV_5705                         0x03
 #define   ASIC_REV_5750                         0x04
+#define   ASIC_REV_5752                         0x06
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -1307,6 +1311,9 @@
 #define  GRC_LCLCTRL_CLEARINT          0x00000002
 #define  GRC_LCLCTRL_SETINT            0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN       0x00000008
+#define  GRC_LCLCTRL_GPIO_INPUT3       0x00000020
+#define  GRC_LCLCTRL_GPIO_OE3          0x00000040
+#define  GRC_LCLCTRL_GPIO_OUTPUT3      0x00000080
 #define  GRC_LCLCTRL_GPIO_INPUT0       0x00000100
 #define  GRC_LCLCTRL_GPIO_INPUT1       0x00000200
 #define  GRC_LCLCTRL_GPIO_INPUT2       0x00000400
@@ -1392,6 +1399,20 @@
 #define  FLASH_VENDOR_SAIFUN            0x01000003
 #define  FLASH_VENDOR_SST_SMALL                 0x00000001
 #define  FLASH_VENDOR_SST_LARGE                 0x02000001
+#define  NVRAM_CFG1_5752VENDOR_MASK     0x03c00003
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ    0x00000000
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ   0x02000000
+#define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED  0x02000003
+#define  FLASH_5752VENDOR_ST_M45PE10    0x02400000
+#define  FLASH_5752VENDOR_ST_M45PE20    0x02400002
+#define  FLASH_5752VENDOR_ST_M45PE40    0x02400001
+#define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
+#define  FLASH_5752PAGE_SIZE_256        0x00000000
+#define  FLASH_5752PAGE_SIZE_512        0x10000000
+#define  FLASH_5752PAGE_SIZE_1K                 0x20000000
+#define  FLASH_5752PAGE_SIZE_2K                 0x30000000
+#define  FLASH_5752PAGE_SIZE_4K                 0x40000000
+#define  FLASH_5752PAGE_SIZE_264        0x50000000
 #define NVRAM_CFG2                     0x00007018
 #define NVRAM_CFG3                     0x0000701c
 #define NVRAM_SWARB                    0x00007020
@@ -2100,6 +2121,9 @@ struct tg3 {
 #define TG3_FLG2_HW_TSO                        0x00010000
 #define TG3_FLG2_SERDES_PREEMPHASIS    0x00020000
 #define TG3_FLG2_5705_PLUS             0x00040000
+#define TG3_FLG2_5750_PLUS             0x00080000
+#define TG3_FLG2_PROTECTED_NVRAM       0x00100000
+#define TG3_FLG2_USING_MSI             0x00200000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2145,6 +2169,7 @@ struct tg3 {
 #define PHY_ID_BCM5704                 0x60008190
 #define PHY_ID_BCM5705                 0x600081a0
 #define PHY_ID_BCM5750                 0x60008180
+#define PHY_ID_BCM5752                 0x60008100
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
 #define PHY_ID_REV_MASK                        0x0000000f