tg3: Disable CLKREQ in L2

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 574a1cc4d3535fd878d100acf0aeb83d36a8531d..8a6012ab23ffff3d7448344e6da286768167646b 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -23,7 +23,7 @@
 #define TG3_BDINFO_NIC_ADDR            0xcUL /* 32-bit */
 #define TG3_BDINFO_SIZE                        0x10UL
 
-#define RX_COPY_THRESHOLD              256
+#define RX_COPY_THRESHOLD              256
 
 #define TG3_RX_INTERNAL_RING_SZ_5906   32
 
@@ -252,7 +252,7 @@
 /* 0x94 --> 0x98 unused */
 #define TG3PCI_STD_RING_PROD_IDX       0x00000098 /* 64-bit */
 #define TG3PCI_RCV_RET_RING_CON_IDX    0x000000a0 /* 64-bit */
-/* 0xa0 --> 0xb8 unused */
+/* 0xa8 --> 0xb8 unused */
 #define TG3PCI_DUAL_MAC_CTRL           0x000000b8
 #define  DUAL_MAC_CTRL_CH_MASK          0x00000003
 #define  DUAL_MAC_CTRL_ID               0x00000004
@@ -1854,6 +1854,8 @@
 #define TG3_PCIE_TLDLPL_PORT           0x00007c00
 #define TG3_PCIE_PL_LO_PHYCTL1          0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN        0x00001000
+#define TG3_PCIE_PL_LO_PHYCTL5          0x00000014
+#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ      0x80000000
 
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK            0x000000e0
@@ -2082,7 +2084,7 @@
 #define MII_TG3_DSP_AADJ1CH0           0x001f
 #define MII_TG3_DSP_AADJ1CH3           0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
-#define MII_TG3_DSP_EXP8               0x0708
+#define MII_TG3_DSP_EXP8               0x0f08
 #define  MII_TG3_DSP_EXP8_REJ2MHz      0x0001
 #define  MII_TG3_DSP_EXP8_AEDW         0x0200
 #define MII_TG3_DSP_EXP75              0x0f75
@@ -2561,7 +2563,7 @@ struct tg3_bufmgr_config {
 
 struct tg3_ethtool_stats {
        /* Statistics maintained by Receive MAC. */
-       u64             rx_octets;
+       u64             rx_octets;
        u64             rx_fragments;
        u64             rx_ucast_packets;
        u64             rx_mcast_packets;