tg3: Add 5719 PCI device and phy IDs

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index ce9c4918c3181cbaf2de835b3e42411d65d71f18..6b6af7698b3878910fafa44618eb71dffe88cd92 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -53,6 +53,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57765     0x16b4
 #define  TG3PCI_DEVICE_TIGON3_57791     0x16b2
 #define  TG3PCI_DEVICE_TIGON3_57795     0x16b6
+#define  TG3PCI_DEVICE_TIGON3_5719      0x1657
 /* 0x04 --> 0x2c unused */
 #define TG3PCI_SUBVENDOR_ID_BROADCOM           PCI_VENDOR_ID_BROADCOM
 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6   0x1644
@@ -160,6 +161,7 @@
 #define   ASIC_REV_57780                0x57780
 #define   ASIC_REV_5717                         0x5717
 #define   ASIC_REV_57765                0x57785
+#define   ASIC_REV_5719                         0x5719
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -231,6 +233,7 @@
 #define  PCISTATE_RETRY_SAME_DMA        0x00002000
 #define  PCISTATE_ALLOW_APE_CTLSPC_WR   0x00010000
 #define  PCISTATE_ALLOW_APE_SHMEM_WR    0x00020000
+#define  PCISTATE_ALLOW_APE_PSPACE_WR   0x00040000
 #define TG3PCI_CLOCK_CTRL              0x00000074
 #define  CLOCK_CTRL_CORECLK_DISABLE     0x00000200
 #define  CLOCK_CTRL_RXCLK_DISABLE       0x00000400
@@ -468,6 +471,7 @@
 #define  TX_MODE_FLOW_CTRL_ENABLE       0x00000010
 #define  TX_MODE_BIG_BCKOFF_ENABLE      0x00000020
 #define  TX_MODE_LONG_PAUSE_ENABLE      0x00000040
+#define  TX_MODE_MBUF_LOCKUP_FIX        0x00000100
 #define MAC_TX_STATUS                  0x00000460
 #define  TX_STATUS_XOFFED               0x00000001
 #define  TX_STATUS_SENT_XOFF            0x00000002
@@ -1071,10 +1075,8 @@
 #define TG3_CPMU_HST_ACC               0x0000361c
 #define  CPMU_HST_ACC_MACCLK_MASK       0x001f0000
 #define  CPMU_HST_ACC_MACCLK_6_25       0x00130000
-/* 0x3620 --> 0x362c unused */
+/* 0x3620 --> 0x3630 unused */
 
-#define TG3_CPMU_STATUS                        0x0000362c
-#define  TG3_CPMU_STATUS_PCIE_FUNC      0x20000000
 #define TG3_CPMU_CLCK_STAT             0x00003630
 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000
@@ -2209,6 +2211,11 @@
 #define  APE_EVENT_STATUS_STATE_SUSPEND         0x00040000
 #define  APE_EVENT_STATUS_EVENT_PENDING         0x80000000
 
+#define TG3_APE_PER_LOCK_REQ           0x8400
+#define  APE_LOCK_PER_REQ_DRIVER        0x00001000
+#define TG3_APE_PER_LOCK_GRANT         0x8420
+#define  APE_PER_LOCK_GRANT_DRIVER      0x00001000
+
 /* APE convenience enumerations. */
 #define TG3_APE_LOCK_GRC                1
 #define TG3_APE_LOCK_MEM                4
@@ -2942,6 +2949,7 @@ struct tg3 {
 #define TG3_PHY_ID_BCM5718C            0x5c0d8a00
 #define TG3_PHY_ID_BCM5718S            0xbc050ff0
 #define TG3_PHY_ID_BCM57765            0x5c0d8a40
+#define TG3_PHY_ID_BCM5719C            0x5c0d8a20
 #define TG3_PHY_ID_BCM5906             0xdc00ac40
 #define TG3_PHY_ID_BCM8002             0x60010140
 #define TG3_PHY_ID_INVALID             0xffffffff
@@ -2965,7 +2973,8 @@ struct tg3 {
         (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
         (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
         (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
-        (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
+        (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
+        (X) == TG3_PHY_ID_BCM8002)
 
        u32                             led_ctrl;
        u32                             phy_otp;