tg3: Add 57765 asic rev

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d770da124b850912177bc553af55ad51c7391579..6a2c31071cafbfb33066ecbd4b14a09f291b8ae8 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -46,10 +46,15 @@
 #define  TG3PCI_DEVICE_TIGON3_57788     0x1691
 #define  TG3PCI_DEVICE_TIGON3_5785_G    0x1699 /* GPHY */
 #define  TG3PCI_DEVICE_TIGON3_5785_F    0x16a0 /* 10/100 only */
-#define  TG3PCI_DEVICE_TIGON3_5717C     0x1655
-#define  TG3PCI_DEVICE_TIGON3_5717S     0x1656
-#define  TG3PCI_DEVICE_TIGON3_5718C     0x1665
-#define  TG3PCI_DEVICE_TIGON3_5718S     0x1666
+#define  TG3PCI_DEVICE_TIGON3_5717      0x1655
+#define  TG3PCI_DEVICE_TIGON3_5718      0x1656
+#define  TG3PCI_DEVICE_TIGON3_5724      0x165c
+#define  TG3PCI_DEVICE_TIGON3_57781     0x16b1
+#define  TG3PCI_DEVICE_TIGON3_57785     0x16b5
+#define  TG3PCI_DEVICE_TIGON3_57761     0x16b0
+#define  TG3PCI_DEVICE_TIGON3_57765     0x16b4
+#define  TG3PCI_DEVICE_TIGON3_57791     0x16b2
+#define  TG3PCI_DEVICE_TIGON3_57795     0x16b6
 /* 0x04 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
@@ -103,6 +108,7 @@
 #define  CHIPREV_ID_5906_A1             0xc001
 #define  CHIPREV_ID_57780_A0            0x57780000
 #define  CHIPREV_ID_57780_A1            0x57780001
+#define  CHIPREV_ID_5717_A0             0x05717000
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -122,6 +128,7 @@
 #define   ASIC_REV_5785                         0x5785
 #define   ASIC_REV_57780                0x57780
 #define   ASIC_REV_5717                         0x5717
+#define   ASIC_REV_57765                0x57785
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -141,8 +148,7 @@
 #define   METAL_REV_B1                  0x01
 #define   METAL_REV_B2                  0x02
 #define TG3PCI_DMA_RW_CTRL             0x0000006c
-#define  DMA_RWCTRL_MIN_DMA             0x000000ff
-#define  DMA_RWCTRL_MIN_DMA_SHIFT       0
+#define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
 #define  DMA_RWCTRL_READ_BNDRY_MASK     0x00000700
 #define  DMA_RWCTRL_READ_BNDRY_DISAB    0x00000000
 #define  DMA_RWCTRL_READ_BNDRY_16       0x00000100
@@ -221,6 +227,7 @@
 /* 0xc0 --> 0xf4 unused */
 
 #define TG3PCI_GEN2_PRODID_ASICREV     0x000000f4
+#define TG3PCI_GEN15_PRODID_ASICREV    0x000000fc
 /* 0xf8 --> 0x200 unused */
 
 #define TG3_CORR_ERR_STAT              0x00000110
@@ -242,7 +249,11 @@
 #define MAILBOX_GENERAL_7              0x00000258 /* 64-bit */
 #define MAILBOX_RELOAD_STAT            0x00000260 /* 64-bit */
 #define MAILBOX_RCV_STD_PROD_IDX       0x00000268 /* 64-bit */
+#define TG3_RX_STD_PROD_IDX_REG                (MAILBOX_RCV_STD_PROD_IDX + \
+                                        TG3_64BIT_REG_LOW)
 #define MAILBOX_RCV_JUMBO_PROD_IDX     0x00000270 /* 64-bit */
+#define TG3_RX_JMB_PROD_IDX_REG                (MAILBOX_RCV_JUMBO_PROD_IDX + \
+                                        TG3_64BIT_REG_LOW)
 #define MAILBOX_RCV_MINI_PROD_IDX      0x00000278 /* 64-bit */
 #define MAILBOX_RCVRET_CON_IDX_0       0x00000280 /* 64-bit */
 #define MAILBOX_RCVRET_CON_IDX_1       0x00000288 /* 64-bit */
@@ -2438,10 +2449,6 @@ struct ring_info {
        DECLARE_PCI_UNMAP_ADDR(mapping)
 };
 
-struct tx_ring_info {
-       struct sk_buff                  *skb;
-};
-
 struct tg3_config_info {
        u32                             flags;
 };
@@ -2570,8 +2577,10 @@ struct tg3_ethtool_stats {
 };
 
 struct tg3_rx_prodring_set {
-       u32                             rx_std_ptr;
-       u32                             rx_jmb_ptr;
+       u32                             rx_std_prod_idx;
+       u32                             rx_std_cons_idx;
+       u32                             rx_jmb_prod_idx;
+       u32                             rx_jmb_cons_idx;
        struct tg3_rx_buffer_desc       *rx_std;
        struct tg3_ext_rx_buffer_desc   *rx_jmb;
        struct ring_info                *rx_std_buffers;
@@ -2599,10 +2608,11 @@ struct tg3_napi {
        u32                             consmbox;
        u32                             rx_rcb_ptr;
        u16                             *rx_rcb_prod_idx;
+       struct tg3_rx_prodring_set      *prodring;
 
        struct tg3_rx_buffer_desc       *rx_rcb;
        struct tg3_tx_buffer_desc       *tx_ring;
-       struct tx_ring_info             *tx_buffers;
+       struct ring_info                *tx_buffers;
 
        dma_addr_t                      status_mapping;
        dma_addr_t                      rx_rcb_mapping;
@@ -2682,7 +2692,7 @@ struct tg3 {
        struct vlan_group               *vlgrp;
 #endif
 
-       struct tg3_rx_prodring_set      prodring[1];
+       struct tg3_rx_prodring_set      prodring[TG3_IRQ_MAX_VECS - 1];
 
 
        /* begin "everything else" cacheline(s) section */
@@ -2753,7 +2763,7 @@ struct tg3 {
 #define TG3_FLG2_SERDES_PREEMPHASIS    0x00020000
 #define TG3_FLG2_5705_PLUS             0x00040000
 #define TG3_FLG2_5750_PLUS             0x00080000
-#define TG3_FLG2_PROTECTED_NVRAM       0x00100000
+#define TG3_FLG2_HW_TSO_3              0x00100000
 #define TG3_FLG2_USING_MSI             0x00200000
 #define TG3_FLG2_USING_MSIX            0x00400000
 #define TG3_FLG2_USING_MSI_OR_MSIX     (TG3_FLG2_USING_MSI | \
@@ -2765,7 +2775,9 @@ struct tg3 {
 #define TG3_FLG2_ICH_WORKAROUND                0x02000000
 #define TG3_FLG2_5780_CLASS            0x04000000
 #define TG3_FLG2_HW_TSO_2              0x08000000
-#define TG3_FLG2_HW_TSO                        (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
+#define TG3_FLG2_HW_TSO                        (TG3_FLG2_HW_TSO_1 | \
+                                        TG3_FLG2_HW_TSO_2 | \
+                                        TG3_FLG2_HW_TSO_3)
 #define TG3_FLG2_1SHOT_MSI             0x10000000
 #define TG3_FLG2_PHY_JITTER_BUG                0x20000000
 #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
@@ -2773,6 +2785,7 @@ struct tg3 {
        u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS   0x00000001
 #define TG3_FLG3_ENABLE_APE            0x00000002
+#define TG3_FLG3_PROTECTED_NVRAM       0x00000004
 #define TG3_FLG3_5701_DMA_BUG          0x00000008
 #define TG3_FLG3_USE_PHYLIB            0x00000010
 #define TG3_FLG3_MDIOBUS_INITED                0x00000020
@@ -2786,9 +2799,11 @@ struct tg3 {
 #define TG3_FLG3_NO_NVRAM              0x00004000
 #define TG3_FLG3_PHY_IS_FET            0x00010000
 #define TG3_FLG3_ENABLE_RSS            0x00020000
+#define TG3_FLG3_ENABLE_TSS            0x00040000
 #define TG3_FLG3_4G_DMA_BNDRY_BUG      0x00080000
 #define TG3_FLG3_40BIT_DMA_LIMIT_BUG   0x00100000
 #define TG3_FLG3_SHORT_DMA_BUG         0x00200000
+#define TG3_FLG3_USE_JUMBO_BDFLAG      0x00400000
 
        struct timer_list               timer;
        u16                             timer_counter;
@@ -2855,6 +2870,7 @@ struct tg3 {
 #define PHY_ID_BCM5756                 0xbc050ed0
 #define PHY_ID_BCM5784                 0xbc050fa0
 #define PHY_ID_BCM5761                 0xbc050fd0
+#define PHY_ID_BCM5717                 0x5c0d8a00
 #define PHY_ID_BCM5906                 0xdc00ac40
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
@@ -2896,7 +2912,7 @@ struct tg3 {
         (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
         (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
         (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
-        (X) == PHY_ID_BCM8002)
+        (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002)
 
        struct tg3_hw_stats             *hw_stats;
        dma_addr_t                      stats_mapping;