[TG3]: consolidate all DMA water mark settings

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 99c5f9675a560f06ee89a8f11e1e7cf787cea366..0a277c1e75d127fdfdeae270363bae37df73e311 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -136,6 +136,7 @@
 #define   ASIC_REV_5705                         0x03
 #define   ASIC_REV_5750                         0x04
 #define   ASIC_REV_5752                         0x06
+#define   ASIC_REV_5780                         0x08
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -879,31 +880,41 @@
 #define  LOW_RXCOL_TICKS_CLRTCKS        0x00000014
 #define  DEFAULT_RXCOL_TICKS            0x00000048
 #define  HIGH_RXCOL_TICKS               0x00000096
+#define  MAX_RXCOL_TICKS                0x000003ff
 #define HOSTCC_TXCOL_TICKS             0x00003c0c
 #define  LOW_TXCOL_TICKS                0x00000096
 #define  LOW_TXCOL_TICKS_CLRTCKS        0x00000048
 #define  DEFAULT_TXCOL_TICKS            0x0000012c
 #define  HIGH_TXCOL_TICKS               0x00000145
+#define  MAX_TXCOL_TICKS                0x000003ff
 #define HOSTCC_RXMAX_FRAMES            0x00003c10
 #define  LOW_RXMAX_FRAMES               0x00000005
 #define  DEFAULT_RXMAX_FRAMES           0x00000008
 #define  HIGH_RXMAX_FRAMES              0x00000012
+#define  MAX_RXMAX_FRAMES               0x000000ff
 #define HOSTCC_TXMAX_FRAMES            0x00003c14
 #define  LOW_TXMAX_FRAMES               0x00000035
 #define  DEFAULT_TXMAX_FRAMES           0x0000004b
 #define  HIGH_TXMAX_FRAMES              0x00000052
+#define  MAX_TXMAX_FRAMES               0x000000ff
 #define HOSTCC_RXCOAL_TICK_INT         0x00003c18
 #define  DEFAULT_RXCOAL_TICK_INT        0x00000019
 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
+#define  MAX_RXCOAL_TICK_INT            0x000003ff
 #define HOSTCC_TXCOAL_TICK_INT         0x00003c1c
 #define  DEFAULT_TXCOAL_TICK_INT        0x00000019
 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
+#define  MAX_TXCOAL_TICK_INT            0x000003ff
 #define HOSTCC_RXCOAL_MAXF_INT         0x00003c20
 #define  DEFAULT_RXCOAL_MAXF_INT        0x00000005
+#define  MAX_RXCOAL_MAXF_INT            0x000000ff
 #define HOSTCC_TXCOAL_MAXF_INT         0x00003c24
 #define  DEFAULT_TXCOAL_MAXF_INT        0x00000005
+#define  MAX_TXCOAL_MAXF_INT            0x000000ff
 #define HOSTCC_STAT_COAL_TICKS         0x00003c28
 #define  DEFAULT_STAT_COAL_TICKS        0x000f4240
+#define  MAX_STAT_COAL_TICKS            0xd693d400
+#define  MIN_STAT_COAL_TICKS            0x00000064
 /* 0x3c2c --> 0x3c30 unused */
 #define HOSTCC_STATS_BLK_HOST_ADDR     0x00003c30 /* 64-bit */
 #define HOSTCC_STATUS_BLK_HOST_ADDR    0x00003c38 /* 64-bit */
@@ -974,14 +985,17 @@
 #define  DEFAULT_MB_RDMA_LOW_WATER      0x00000050
 #define  DEFAULT_MB_RDMA_LOW_WATER_5705         0x00000000
 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
+#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
 #define BUFMGR_MB_MACRX_LOW_WATER      0x00004414
 #define  DEFAULT_MB_MACRX_LOW_WATER      0x00000020
 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
+#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
 #define BUFMGR_MB_HIGH_WATER           0x00004418
 #define  DEFAULT_MB_HIGH_WATER          0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5705     0x00000060
 #define  DEFAULT_MB_HIGH_WATER_JUMBO    0x0000017c
+#define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
 #define BUFMGR_RX_MB_ALLOC_REQ         0x0000441c
 #define  BUFMGR_MB_ALLOC_BIT            0x10000000
 #define BUFMGR_RX_MB_ALLOC_RESP                0x00004420
@@ -2077,6 +2091,8 @@ struct tg3 {
        struct tg3_rx_buffer_desc       *rx_rcb;
        dma_addr_t                      rx_rcb_mapping;
 
+       u32                             rx_pkt_buf_sz;
+
        /* begin "everything else" cacheline(s) section */
        struct net_device_stats         net_stats;
        struct net_device_stats         net_stats_prev;
@@ -2114,7 +2130,7 @@ struct tg3 {
 #define TG3_FLAG_NO_TX_PSEUDO_CSUM     0x00100000
 #define TG3_FLAG_NO_RX_PSEUDO_CSUM     0x00200000
 #define TG3_FLAG_SERDES_WOL_CAP                0x00400000
-#define TG3_FLAG_JUMBO_ENABLE          0x00800000
+#define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
@@ -2144,6 +2160,7 @@ struct tg3 {
 #define TG3_FLG2_5750_PLUS             0x00080000
 #define TG3_FLG2_PROTECTED_NVRAM       0x00100000
 #define TG3_FLG2_USING_MSI             0x00200000
+#define TG3_FLG2_JUMBO_CAPABLE         0x00400000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2177,6 +2194,7 @@ struct tg3 {
        u8                              pci_bist;
 
        int                             pm_cap;
+       int                             msi_cap;
 
        /* PHY info */
        u32                             phy_id;
@@ -2190,6 +2208,7 @@ struct tg3 {
 #define PHY_ID_BCM5705                 0x600081a0
 #define PHY_ID_BCM5750                 0x60008180
 #define PHY_ID_BCM5752                 0x60008100
+#define PHY_ID_BCM5780                 0x60008350
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
 #define PHY_ID_REV_MASK                        0x0000000f