tg3: Add 5784 ASIC rev to earlier PCIe MPS fix

[net-next-2.6.git] / drivers / net / tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index aa2d64f58ed3cec3f1c963b0f78dfa6731aba299..98ca0d20d20662f379d5cd5e7cf70fb8f360c044 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -18,6 +18,7 @@
 
 #include <linux/module.h>
 #include <linux/moduleparam.h>
+#include <linux/stringify.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/compiler.h>
@@ -67,8 +68,11 @@
 #include "tg3.h"
 
 #define DRV_MODULE_NAME                "tg3"
-#define DRV_MODULE_VERSION     "3.111"
-#define DRV_MODULE_RELDATE     "June 5, 2010"
+#define TG3_MAJ_NUM                    3
+#define TG3_MIN_NUM                    112
+#define DRV_MODULE_VERSION     \
+       __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
+#define DRV_MODULE_RELDATE     "July 11, 2010"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
@@ -5570,8 +5574,8 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
 
        entry = tnapi->tx_prod;
        base_flags = 0;
-       mss = 0;
-       if ((mss = skb_shinfo(skb)->gso_size) != 0) {
+       mss = skb_shinfo(skb)->gso_size;
+       if (mss) {
                int tcp_opt_len, ip_tcp_len;
                u32 hdrlen;
 
@@ -5777,9 +5781,10 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
        if (skb->ip_summed == CHECKSUM_PARTIAL)
                base_flags |= TXD_FLAG_TCPUDP_CSUM;
 
-       if ((mss = skb_shinfo(skb)->gso_size) != 0) {
+       mss = skb_shinfo(skb)->gso_size;
+       if (mss) {
                struct iphdr *iph;
-               u32 tcp_opt_len, ip_tcp_len, hdr_len;
+               u32 tcp_opt_len, hdr_len;
 
                if (skb_header_cloned(skb) &&
                    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
@@ -5787,10 +5792,21 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                        goto out_unlock;
                }
 
+               iph = ip_hdr(skb);
                tcp_opt_len = tcp_optlen(skb);
-               ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
 
-               hdr_len = ip_tcp_len + tcp_opt_len;
+               if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
+                       hdr_len = skb_headlen(skb) - ETH_HLEN;
+               } else {
+                       u32 ip_tcp_len;
+
+                       ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
+                       hdr_len = ip_tcp_len + tcp_opt_len;
+
+                       iph->check = 0;
+                       iph->tot_len = htons(mss + hdr_len);
+               }
+
                if (unlikely((ETH_HLEN + hdr_len) > 80) &&
                             (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
                        return tg3_tso_bug(tp, skb);
@@ -5798,9 +5814,6 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                base_flags |= (TXD_FLAG_CPU_PRE_DMA |
                               TXD_FLAG_CPU_POST_DMA);
 
-               iph = ip_hdr(skb);
-               iph->check = 0;
-               iph->tot_len = htons(mss + hdr_len);
                if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
                        tcp_hdr(skb)->check = 0;
                        base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
@@ -6621,7 +6634,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
                apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
                tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
                tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
-                               APE_HOST_DRIVER_ID_MAGIC);
+                       APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
                tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
                                APE_HOST_BEHAV_NO_PHYLOCK);
 
@@ -6989,8 +7002,7 @@ static int tg3_chip_reset(struct tg3 *tp)
                 * Older PCIe devices only support the 128 byte
                 * MPS setting.  Enforce the restriction.
                 */
-               if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
-                   (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
+               if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
                        val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
                pci_write_config_word(tp->pdev,
                                      tp->pcie_cap + PCI_EXP_DEVCTL,
@@ -7060,30 +7072,6 @@ static int tg3_chip_reset(struct tg3 *tp)
 
        tg3_mdio_start(tp);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
-               u8 phy_addr;
-
-               phy_addr = tp->phy_addr;
-               tp->phy_addr = TG3_PHY_PCIE_ADDR;
-
-               tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
-                            TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
-               val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
-                     TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
-                     TG3_PCIEPHY_TX0CTRL1_NB_EN;
-               tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
-               udelay(10);
-
-               tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
-                            TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
-               val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
-                     TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
-               tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
-               udelay(10);
-
-               tp->phy_addr = phy_addr;
-       }
-
        if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
            tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
@@ -7447,7 +7435,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
                tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
        }
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
+       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
                tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
                tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
                tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
@@ -8237,7 +8225,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
                        int idx = i % sizeof(val);
 
-                       ent[idx] = (i % (tp->irq_cnt - 1)) + 1;
+                       ent[idx] = i % (tp->irq_cnt - 1);
                        if (idx == sizeof(val) - 1) {
                                tw32(reg, val);
                                reg += 4;
@@ -8526,7 +8514,7 @@ static void tg3_timer(unsigned long __opaque)
                            (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
                                need_setup = 1;
                        }
-                       if (! netif_carrier_ok(tp->dev) &&
+                       if (!netif_carrier_ok(tp->dev) &&
                            (mac_stat & (MAC_STATUS_PCS_SYNCED |
                                         MAC_STATUS_SIGNAL_DET))) {
                                need_setup = 1;
@@ -8543,7 +8531,7 @@ static void tg3_timer(unsigned long __opaque)
                                tg3_setup_phy(tp, 0);
                        }
                } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
-                          !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+                          (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
                        tg3_serdes_parallel_detect(tp);
                }
 
@@ -9384,7 +9372,7 @@ static void tg3_get_regs(struct net_device *dev,
        tg3_full_lock(tp, 0);
 
 #define __GET_REG32(reg)       (*(p)++ = tr32(reg))
-#define GET_REG32_LOOP(base,len)               \
+#define GET_REG32_LOOP(base, len)              \
 do {   p = (u32 *)(orig_p + (base));           \
        for (i = 0; i < len; i += 4)            \
                __GET_REG32((base) + i);        \
@@ -9477,7 +9465,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
                ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
                if (ret)
                        return ret;
-               memcpy(data, ((char*)&val) + b_offset, b_count);
+               memcpy(data, ((char *)&val) + b_offset, b_count);
                len -= b_count;
                offset += b_count;
                eeprom->len += b_count;
@@ -10597,8 +10585,8 @@ static int tg3_test_memory(struct tg3 *tp)
                mem_tbl = mem_tbl_570x;
 
        for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
-               if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
-                   mem_tbl[i].len)) != 0)
+               err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
+               if (err)
                        break;
        }
 
@@ -10943,7 +10931,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
                        return -EAGAIN;
                phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
-               return phy_mii_ioctl(phydev, data, cmd);
+               return phy_mii_ioctl(phydev, ifr, cmd);
        }
 
        switch (cmd) {
@@ -13419,8 +13407,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                return err;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
-           (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
-                (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
+           tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
                return -ENOTSUPP;
 
        /* Initialize data/descriptor byte/word swapping. */