tg3: 5717: Allow serdes link via parallel detect

[net-next-2.6.git] / drivers / net / tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 573054ae7b58687dbe52eee0be849f0436159e1c..2dcde1343cc79152e7fab8ef4831835f238363ad 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -145,8 +145,6 @@
 #define TG3_RX_JMB_BUFF_RING_SIZE \
        (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 
-#define TG3_RSS_MIN_NUM_MSIX_VECS      2
-
 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
  * that are at least dword aligned when used in PCIX mode.  The driver
  * works around this bug by double copying the packet.  This workaround
@@ -585,18 +583,23 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 static void tg3_ape_lock_init(struct tg3 *tp)
 {
        int i;
+       u32 regbase;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+               regbase = TG3_APE_LOCK_GRANT;
+       else
+               regbase = TG3_APE_PER_LOCK_GRANT;
 
        /* Make sure the driver hasn't any stale locks. */
        for (i = 0; i < 8; i++)
-               tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
-                               APE_LOCK_GRANT_DRIVER);
+               tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 }
 
 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 {
        int i, off;
        int ret = 0;
-       u32 status;
+       u32 status, req, gnt;
 
        if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
                return 0;
@@ -609,13 +612,21 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
                return -EINVAL;
        }
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
+               req = TG3_APE_LOCK_REQ;
+               gnt = TG3_APE_LOCK_GRANT;
+       } else {
+               req = TG3_APE_PER_LOCK_REQ;
+               gnt = TG3_APE_PER_LOCK_GRANT;
+       }
+
        off = 4 * locknum;
 
-       tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
+       tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 
        /* Wait for up to 1 millisecond to acquire lock. */
        for (i = 0; i < 100; i++) {
-               status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
+               status = tg3_ape_read32(tp, gnt + off);
                if (status == APE_LOCK_GRANT_DRIVER)
                        break;
                udelay(10);
@@ -623,7 +634,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
 
        if (status != APE_LOCK_GRANT_DRIVER) {
                /* Revoke the lock request. */
-               tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
+               tg3_ape_write32(tp, gnt + off,
                                APE_LOCK_GRANT_DRIVER);
 
                ret = -EBUSY;
@@ -634,7 +645,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
 
 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 {
-       int off;
+       u32 gnt;
 
        if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
                return;
@@ -647,8 +658,12 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
                return;
        }
 
-       off = 4 * locknum;
-       tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+               gnt = TG3_APE_LOCK_GRANT;
+       else
+               gnt = TG3_APE_PER_LOCK_GRANT;
+
+       tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 }
 
 static void tg3_disable_ints(struct tg3 *tp)
@@ -4191,6 +4206,8 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
                                        current_duplex = DUPLEX_FULL;
                                else
                                        current_duplex = DUPLEX_HALF;
+                       } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+                               /* Link is up via parallel detect */
                        } else {
                                current_link_up = 0;
                        }
@@ -6212,6 +6229,8 @@ static void tg3_free_rings(struct tg3 *tp)
        for (j = 0; j < tp->irq_cnt; j++) {
                struct tg3_napi *tnapi = &tp->napi[j];
 
+               tg3_rx_prodring_free(tp, &tp->prodring[j]);
+
                if (!tnapi->tx_buffers)
                        continue;
 
@@ -6247,8 +6266,6 @@ static void tg3_free_rings(struct tg3 *tp)
 
                        dev_kfree_skb_any(skb);
                }
-
-               tg3_rx_prodring_free(tp, &tp->prodring[j]);
        }
 }
 
@@ -6782,7 +6799,8 @@ static void tg3_restore_pci_state(struct tg3 *tp)
        /* Allow reads and writes to the APE register and memory space. */
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
                val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
-                      PCISTATE_ALLOW_APE_SHMEM_WR;
+                      PCISTATE_ALLOW_APE_SHMEM_WR |
+                      PCISTATE_ALLOW_APE_PSPACE_WR;
        pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
 
        pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
@@ -7720,7 +7738,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 */
                val = tr32(TG3PCI_PCISTATE);
                val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
-                      PCISTATE_ALLOW_APE_SHMEM_WR;
+                      PCISTATE_ALLOW_APE_SHMEM_WR |
+                      PCISTATE_ALLOW_APE_PSPACE_WR;
                tw32(TG3PCI_PCISTATE, val);
        }
 
@@ -8195,6 +8214,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        }
 
        tp->tx_mode = TX_MODE_ENABLE;
+       if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
+               tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
        tw32_f(MAC_TX_MODE, tp->tx_mode);
        udelay(100);
 
@@ -8206,7 +8228,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
                        int idx = i % sizeof(val);
 
-                       ent[idx] = i % (tp->irq_cnt - 1);
+                       ent[idx] = (i % (tp->irq_cnt - 1)) + 1;
                        if (idx == sizeof(val) - 1) {
                                tw32(reg, val);
                                reg += 4;
@@ -8511,8 +8533,10 @@ static void tg3_timer(unsigned long __opaque)
                                }
                                tg3_setup_phy(tp, 0);
                        }
-               } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
+               } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
+                          !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
                        tg3_serdes_parallel_detect(tp);
+               }
 
                tp->timer_counter = tp->timer_multiplier;
        }
@@ -8775,9 +8799,9 @@ static bool tg3_enable_msix(struct tg3 *tp)
        }
 
        rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
-       if (rc != 0) {
-               if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
-                       return false;
+       if (rc < 0) {
+               return false;
+       } else if (rc != 0) {
                if (pci_enable_msix(tp->pdev, msix_ent, rc))
                        return false;
                netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
@@ -8785,16 +8809,18 @@ static bool tg3_enable_msix(struct tg3 *tp)
                tp->irq_cnt = rc;
        }
 
-       tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
-
        for (i = 0; i < tp->irq_max; i++)
                tp->napi[i].irq_vec = msix_ent[i].vector;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
-               tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
-               tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
-       } else
-               tp->dev->real_num_tx_queues = 1;
+       tp->dev->real_num_tx_queues = 1;
+       if (tp->irq_cnt > 1) {
+               tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
+                       tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
+                       tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
+               }
+       }
 
        return true;
 }
@@ -13242,7 +13268,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                 * APE register and memory space.
                 */
                pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
-                                PCISTATE_ALLOW_APE_SHMEM_WR;
+                                PCISTATE_ALLOW_APE_SHMEM_WR |
+                                PCISTATE_ALLOW_APE_PSPACE_WR;
                pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
                                       pci_state_reg);
        }