ixgbe: cleanup ixgbe_map_rings_to_vectors

[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index dc4b97e5777f7d9a43a70f32fbbad4e1e12cea4f..ce43c935268106d8950bb9c237835afaa9fa4e3d 100644 (file)
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -159,6 +159,31 @@ struct ixgbe_rx_queue_stats {
        u64 alloc_rx_buff_failed;
 };
 
+enum ixbge_ring_state_t {
+       __IXGBE_TX_FDIR_INIT_DONE,
+       __IXGBE_TX_DETECT_HANG,
+       __IXGBE_RX_PS_ENABLED,
+       __IXGBE_RX_RSC_ENABLED,
+};
+
+#define ring_is_ps_enabled(ring) \
+       test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define set_ring_ps_enabled(ring) \
+       set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define clear_ring_ps_enabled(ring) \
+       clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define check_for_tx_hang(ring) \
+       test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define set_check_for_tx_hang(ring) \
+       set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define clear_check_for_tx_hang(ring) \
+       clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define ring_is_rsc_enabled(ring) \
+       test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
+#define set_ring_rsc_enabled(ring) \
+       set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
+#define clear_ring_rsc_enabled(ring) \
+       clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 struct ixgbe_ring {
        void *desc;                     /* descriptor ring memory */
        struct device *dev;             /* device for DMA mapping */
@@ -167,6 +192,7 @@ struct ixgbe_ring {
                struct ixgbe_tx_buffer *tx_buffer_info;
                struct ixgbe_rx_buffer *rx_buffer_info;
        };
+       unsigned long state;
        u8 atr_sample_rate;
        u8 atr_count;
        u16 count;                      /* amount of descriptors */
@@ -175,37 +201,30 @@ struct ixgbe_ring {
        u16 next_to_clean;
 
        u8 queue_index; /* needed for multiqueue queue management */
+       u8 reg_idx;                     /* holds the special value that gets
+                                        * the hardware register offset
+                                        * associated with this ring, which is
+                                        * different for DCB and RSS modes
+                                        */
+
+       u16 work_limit;                 /* max work per interrupt */
 
-#define IXGBE_RING_RX_PS_ENABLED                (u8)(1)
-       u8 flags;                       /* per ring feature flags */
        u8 __iomem *tail;
 
        unsigned int total_bytes;
        unsigned int total_packets;
 
-#ifdef CONFIG_IXGBE_DCA
-       /* cpu for tx queue */
-       int cpu;
-#endif
-
-       u16 work_limit;                 /* max work per interrupt */
-       u16 reg_idx;                    /* holds the special value that gets
-                                        * the hardware register offset
-                                        * associated with this ring, which is
-                                        * different for DCB and RSS modes
-                                        */
-
        struct ixgbe_queue_stats stats;
        struct u64_stats_sync syncp;
        union {
                struct ixgbe_tx_queue_stats tx_stats;
                struct ixgbe_rx_queue_stats rx_stats;
        };
-       unsigned long reinit_state;
        int numa_node;
        unsigned int size;              /* length in bytes */
        dma_addr_t dma;                 /* phys. address of descriptor ring */
        struct rcu_head rcu;
+       struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 } ____cacheline_internodealigned_in_smp;
 
 enum ixgbe_ring_f_enum {
@@ -251,6 +270,9 @@ struct ixgbe_q_vector {
        unsigned int v_idx; /* index of q_vector within array, also used for
                             * finding the bit in EICR and friends that
                             * represents the vector for this ring */
+#ifdef CONFIG_IXGBE_DCA
+       int cpu;            /* CPU for DCA */
+#endif
        struct napi_struct napi;
        DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
        DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
@@ -260,6 +282,7 @@ struct ixgbe_q_vector {
        u8 rx_itr;
        u32 eitr;
        cpumask_var_t affinity_mask;
+       char name[IFNAMSIZ + 9];
 };
 
 /* Helper macros to switch between ints/sec and what the register uses.
@@ -308,7 +331,6 @@ struct ixgbe_adapter {
        u16 bd_number;
        struct work_struct reset_task;
        struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
-       char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
        struct ixgbe_dcb_config dcb_cfg;
        struct ixgbe_dcb_config temp_dcb_cfg;
        u8 dcb_set_bitmap;
@@ -431,6 +453,7 @@ struct ixgbe_adapter {
        int node;
        struct work_struct check_overtemp_task;
        u32 interrupt_event;
+       char lsc_int_name[IFNAMSIZ + 9];
 
        /* SR-IOV */
        DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
@@ -442,10 +465,16 @@ enum ixbge_state_t {
        __IXGBE_TESTING,
        __IXGBE_RESETTING,
        __IXGBE_DOWN,
-       __IXGBE_FDIR_INIT_DONE,
        __IXGBE_SFP_MODULE_NOT_FOUND
 };
 
+struct ixgbe_rsc_cb {
+       dma_addr_t dma;
+       u16 skb_cnt;
+       bool delay_unmap;
+};
+#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
+
 enum ixgbe_boards {
        board_82598,
        board_82599,