ixgbe: add MAC and PHY support for x540

[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index e87b0ffd5832bb43d707be154de2cba94e5da4e4..4806736785a3834e08bab056cda2ade722d07bdb 100644 (file)
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -149,6 +149,8 @@ struct ixgbe_queue_stats {
 struct ixgbe_tx_queue_stats {
        u64 restart_queue;
        u64 tx_busy;
+       u64 completed;
+       u64 tx_done_old;
 };
 
 struct ixgbe_rx_queue_stats {
@@ -159,6 +161,32 @@ struct ixgbe_rx_queue_stats {
        u64 alloc_rx_buff_failed;
 };
 
+enum ixbge_ring_state_t {
+       __IXGBE_TX_FDIR_INIT_DONE,
+       __IXGBE_TX_DETECT_HANG,
+       __IXGBE_HANG_CHECK_ARMED,
+       __IXGBE_RX_PS_ENABLED,
+       __IXGBE_RX_RSC_ENABLED,
+};
+
+#define ring_is_ps_enabled(ring) \
+       test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define set_ring_ps_enabled(ring) \
+       set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define clear_ring_ps_enabled(ring) \
+       clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define check_for_tx_hang(ring) \
+       test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define set_check_for_tx_hang(ring) \
+       set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define clear_check_for_tx_hang(ring) \
+       clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define ring_is_rsc_enabled(ring) \
+       test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
+#define set_ring_rsc_enabled(ring) \
+       set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
+#define clear_ring_rsc_enabled(ring) \
+       clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 struct ixgbe_ring {
        void *desc;                     /* descriptor ring memory */
        struct device *dev;             /* device for DMA mapping */
@@ -167,6 +195,7 @@ struct ixgbe_ring {
                struct ixgbe_tx_buffer *tx_buffer_info;
                struct ixgbe_rx_buffer *rx_buffer_info;
        };
+       unsigned long state;
        u8 atr_sample_rate;
        u8 atr_count;
        u16 count;                      /* amount of descriptors */
@@ -175,28 +204,25 @@ struct ixgbe_ring {
        u16 next_to_clean;
 
        u8 queue_index; /* needed for multiqueue queue management */
+       u8 reg_idx;                     /* holds the special value that gets
+                                        * the hardware register offset
+                                        * associated with this ring, which is
+                                        * different for DCB and RSS modes
+                                        */
+
+       u16 work_limit;                 /* max work per interrupt */
 
-#define IXGBE_RING_RX_PS_ENABLED                (u8)(1)
-       u8 flags;                       /* per ring feature flags */
        u8 __iomem *tail;
 
        unsigned int total_bytes;
        unsigned int total_packets;
 
-       u16 work_limit;                 /* max work per interrupt */
-       u16 reg_idx;                    /* holds the special value that gets
-                                        * the hardware register offset
-                                        * associated with this ring, which is
-                                        * different for DCB and RSS modes
-                                        */
-
        struct ixgbe_queue_stats stats;
        struct u64_stats_sync syncp;
        union {
                struct ixgbe_tx_queue_stats tx_stats;
                struct ixgbe_rx_queue_stats rx_stats;
        };
-       unsigned long reinit_state;
        int numa_node;
        unsigned int size;              /* length in bytes */
        dma_addr_t dma;                 /* phys. address of descriptor ring */
@@ -259,6 +285,7 @@ struct ixgbe_q_vector {
        u8 rx_itr;
        u32 eitr;
        cpumask_var_t affinity_mask;
+       char name[IFNAMSIZ + 9];
 };
 
 /* Helper macros to switch between ints/sec and what the register uses.
@@ -307,7 +334,6 @@ struct ixgbe_adapter {
        u16 bd_number;
        struct work_struct reset_task;
        struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
-       char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
        struct ixgbe_dcb_config dcb_cfg;
        struct ixgbe_dcb_config temp_dcb_cfg;
        u8 dcb_set_bitmap;
@@ -430,6 +456,7 @@ struct ixgbe_adapter {
        int node;
        struct work_struct check_overtemp_task;
        u32 interrupt_event;
+       char lsc_int_name[IFNAMSIZ + 9];
 
        /* SR-IOV */
        DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
@@ -441,17 +468,25 @@ enum ixbge_state_t {
        __IXGBE_TESTING,
        __IXGBE_RESETTING,
        __IXGBE_DOWN,
-       __IXGBE_FDIR_INIT_DONE,
        __IXGBE_SFP_MODULE_NOT_FOUND
 };
 
+struct ixgbe_rsc_cb {
+       dma_addr_t dma;
+       u16 skb_cnt;
+       bool delay_unmap;
+};
+#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
+
 enum ixgbe_boards {
        board_82598,
        board_82599,
+       board_X540,
 };
 
 extern struct ixgbe_info ixgbe_82598_info;
 extern struct ixgbe_info ixgbe_82599_info;
+extern struct ixgbe_info ixgbe_X540_info;
 #ifdef CONFIG_IXGBE_DCB
 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
@@ -484,6 +519,7 @@ extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 extern int ethtool_ioctl(struct ifreq *ifr);
+extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);