drm/radeon/kms: avoid possible oops (call gart_fini before gart_disable)

[net-next-2.6.git] / drivers / gpu / drm / radeon / rs600.c

diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index c3818562a13eb64f647ec74922605bf673bdf0e6..30c4b46f35217a0a6492ea5e08d1bf438ecafe32 100644 (file)
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -37,6 +37,7 @@
  */
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rs600d.h"
 
@@ -45,23 +46,6 @@
 void rs600_gpu_init(struct radeon_device *rdev);
 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 
-int rs600_mc_init(struct radeon_device *rdev)
-{
-       /* read back the MC value from the hw */
-       int r;
-       u32 tmp;
-
-       /* Setup GPU memory space */
-       tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
-       rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
-       rdev->mc.gtt_location = 0xffffffffUL;
-       r = radeon_mc_setup(rdev);
-       rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
-       if (r)
-               return r;
-       return 0;
-}
-
 /* hpd for digital panel detect/disconnect */
 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 {
@@ -213,6 +197,7 @@ int rs600_gart_enable(struct radeon_device *rdev)
        r = radeon_gart_table_vram_pin(rdev);
        if (r)
                return r;
+       radeon_gart_restore(rdev);
        /* Enable bus master */
        tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
        WREG32(R_00004C_BUS_CNTL, tmp);
@@ -283,9 +268,9 @@ void rs600_gart_disable(struct radeon_device *rdev)
 
 void rs600_gart_fini(struct radeon_device *rdev)
 {
+       radeon_gart_fini(rdev);
        rs600_gart_disable(rdev);
        radeon_gart_table_vram_free(rdev);
-       radeon_gart_fini(rdev);
 }
 
 #define R600_PTE_VALID     (1 << 0)
@@ -406,10 +391,16 @@ int rs600_irq_process(struct radeon_device *rdev)
                if (G_000044_SW_INT(status))
                        radeon_fence_process(rdev);
                /* Vertical blank interrupts */
-               if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
+               if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
                        drm_handle_vblank(rdev->ddev, 0);
-               if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
+                       rdev->pm.vblank_sync = true;
+                       wake_up(&rdev->irq.vblank_queue);
+               }
+               if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
                        drm_handle_vblank(rdev->ddev, 1);
+                       rdev->pm.vblank_sync = true;
+                       wake_up(&rdev->irq.vblank_queue);
+               }
                if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
                        queue_hotplug = true;
                        DRM_DEBUG("HPD1\n");
@@ -470,22 +461,24 @@ void rs600_gpu_init(struct radeon_device *rdev)
                dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 }
 
-void rs600_vram_info(struct radeon_device *rdev)
+void rs600_mc_init(struct radeon_device *rdev)
 {
+       u64 base;
+
+       rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+       rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
        rdev->mc.vram_is_ddr = true;
        rdev->mc.vram_width = 128;
-
        rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
        rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
-
-       rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
-       rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-
-       if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
-               rdev->mc.mc_vram_size = rdev->mc.aper_size;
-
-       if (rdev->mc.real_vram_size > rdev->mc.aper_size)
-               rdev->mc.real_vram_size = rdev->mc.aper_size;
+       rdev->mc.visible_vram_size = rdev->mc.aper_size;
+       rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+       base = RREG32_MC(R_000004_MC_FB_LOCATION);
+       base = G_000004_MC_FB_START(base) << 16;
+       rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+       radeon_vram_location(rdev, &rdev->mc, base);
+       radeon_gtt_location(rdev, &rdev->mc);
+       radeon_update_bandwidth_info(rdev);
 }
 
 void rs600_bandwidth_update(struct radeon_device *rdev)
@@ -610,6 +603,7 @@ int rs600_suspend(struct radeon_device *rdev)
 
 void rs600_fini(struct radeon_device *rdev)
 {
+       radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
@@ -661,12 +655,8 @@ int rs600_init(struct radeon_device *rdev)
        radeon_get_clock_info(rdev->ddev);
        /* Initialize power management */
        radeon_pm_init(rdev);
-       /* Get vram informations */
-       rs600_vram_info(rdev);
-       /* Initialize memory controller (also test AGP) */
-       r = rs600_mc_init(rdev);
-       if (r)
-               return r;
+       /* initialize memory controller */
+       rs600_mc_init(rdev);
        rs600_debugfs(rdev);
        /* Fence driver */
        r = radeon_fence_driver_init(rdev);