]> bbs.cooldavid.org Git - net-next-2.6.git/blobdiff - drivers/gpu/drm/radeon/r520.c
drm/radeon/kms: Schedule host path read cache flush through the ring V2
[net-next-2.6.git] / drivers / gpu / drm / radeon / r520.c
index a555b7b19b48aefd3da033a2717b414fdbbccf97..9a189072f2b93e09299ff63b1464d32e260ba657 100644 (file)
@@ -185,8 +185,8 @@ static int r520_startup(struct radeon_device *rdev)
                        return r;
        }
        /* Enable IRQ */
-       rdev->irq.sw_int = true;
        rs600_irq_set(rdev);
+       rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
        /* 1M ring buffer */
        r = r100_cp_init(rdev, 1024 * 1024);
        if (r) {
@@ -221,6 +221,8 @@ int r520_resume(struct radeon_device *rdev)
        atom_asic_init(rdev->mode_info.atom_context);
        /* Resume clock after posting */
        rv515_clock_startup(rdev);
+       /* Initialize surface registers */
+       radeon_surface_init(rdev);
        return r520_startup(rdev);
 }
 
@@ -254,12 +256,17 @@ int r520_init(struct radeon_device *rdev)
                        RREG32(R_0007C0_CP_STAT));
        }
        /* check if cards are posted or not */
+       if (radeon_boot_test_post_card(rdev) == false)
+               return -EINVAL;
+
        if (!radeon_card_posted(rdev) && rdev->bios) {
                DRM_INFO("GPU not posted. posting now...\n");
                atom_asic_init(rdev->mode_info.atom_context);
        }
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
+       /* Initialize power management */
+       radeon_pm_init(rdev);
        /* Get vram informations */
        r520_vram_info(rdev);
        /* Initialize memory controller (also test AGP) */
@@ -275,7 +282,7 @@ int r520_init(struct radeon_device *rdev)
        if (r)
                return r;
        /* Memory manager */
-       r = radeon_object_init(rdev);
+       r = radeon_bo_init(rdev);
        if (r)
                return r;
        r = rv370_pcie_gart_init(rdev);