drm/i915/suspend: Flush register writes before busy-waiting.

[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_suspend.c

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 60a5800fba6e33c6638dc7fc455a33b041a3df8d..05acc26fabf7a30d3f89f0a7e188949dc2687355 100644 (file)
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -395,16 +395,20 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
                I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
                           ~DPLL_VCO_ENABLE);
-               DRM_UDELAY(150);
+               POSTING_READ(dpll_a_reg);
+               udelay(150);
        }
        I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
        I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
        /* Actually enable it */
        I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
-       DRM_UDELAY(150);
-       if (IS_I965G(dev) && !IS_IRONLAKE(dev))
+       POSTING_READ(dpll_a_reg);
+       udelay(150);
+       if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
                I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
-       DRM_UDELAY(150);
+               POSTING_READ(DPLL_A_MD);
+       }
+       udelay(150);
 
        /* Restore mode */
        I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
@@ -460,16 +464,20 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
                I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
                           ~DPLL_VCO_ENABLE);
-               DRM_UDELAY(150);
+               POSTING_READ(dpll_b_reg);
+               udelay(150);
        }
        I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
        I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
        /* Actually enable it */
        I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
-       DRM_UDELAY(150);
-       if (IS_I965G(dev) && !IS_IRONLAKE(dev))
+       POSTING_READ(dpll_b_reg);
+       udelay(150);
+       if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
-       DRM_UDELAY(150);
+               POSTING_READ(DPLL_B_MD);
+       }
+       udelay(150);
 
        /* Restore mode */
        I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
@@ -602,7 +610,9 @@ void i915_save_display(struct drm_device *dev)
 
        /* Only save FBC state on the platform that supports FBC */
        if (I915_HAS_FBC(dev)) {
-               if (IS_GM45(dev)) {
+               if (IS_IRONLAKE_M(dev)) {
+                       dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
+               } else if (IS_GM45(dev)) {
                        dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
                } else {
                        dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
@@ -706,7 +716,10 @@ void i915_restore_display(struct drm_device *dev)
 
        /* only restore FBC info on the platform that supports FBC*/
        if (I915_HAS_FBC(dev)) {
-               if (IS_GM45(dev)) {
+               if (IS_IRONLAKE_M(dev)) {
+                       ironlake_disable_fbc(dev);
+                       I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
+               } else if (IS_GM45(dev)) {
                        g4x_disable_fbc(dev);
                        I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
                } else {
@@ -725,7 +738,8 @@ void i915_restore_display(struct drm_device *dev)
        I915_WRITE(VGA0, dev_priv->saveVGA0);
        I915_WRITE(VGA1, dev_priv->saveVGA1);
        I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
-       DRM_UDELAY(150);
+       POSTING_READ(VGA_PD);
+       udelay(150);
 
        i915_restore_vga(dev);
 }