drm/i915: take struct_mutex in i915_dma_cleanup()

[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 12e92f2cc3a78067870f8d420c25ca2ec2834d28..19677ecfe2bf86ce71fcb4b8d9af855f0424c99b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -84,7 +84,6 @@ static void i915_free_hws(struct drm_device *dev)
 
        if (dev_priv->render_ring.status_page.gfx_addr) {
                dev_priv->render_ring.status_page.gfx_addr = 0;
-               dev_priv->status_gfx_addr = 0;
                drm_core_ioremapfree(&dev_priv->hws_map, dev);
        }
 
@@ -129,9 +128,11 @@ static int i915_dma_cleanup(struct drm_device * dev)
        if (dev->irq_enabled)
                drm_irq_uninstall(dev);
 
+       mutex_lock(&dev->struct_mutex);
        intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
        if (HAS_BSD(dev))
                intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
+       mutex_unlock(&dev->struct_mutex);
 
        /* Clear the HWS virtual address at teardown */
        if (I915_NEED_GFX_HWS(dev))
@@ -745,6 +746,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
                /* depends on GEM */
                value = dev_priv->has_gem;
                break;
+       case I915_PARAM_HAS_BSD:
+               value = HAS_BSD(dev);
+               break;
        default:
                DRM_DEBUG_DRIVER("Unknown parameter %d\n",
                                 param->param);
@@ -828,7 +832,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
        drm_core_ioremap_wc(&dev_priv->hws_map, dev);
        if (dev_priv->hws_map.handle == NULL) {
                i915_dma_cleanup(dev);
-               dev_priv->status_gfx_addr = 0;
+               ring->status_page.gfx_addr = 0;
                DRM_ERROR("can not ioremap virtual address for"
                                " G33 hw status page\n");
                return -ENOMEM;
@@ -838,9 +842,9 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
        I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 
        DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
-                       dev_priv->status_gfx_addr);
+                        ring->status_page.gfx_addr);
        DRM_DEBUG_DRIVER("load hws at %p\n",
-                       dev_priv->hw_status_page);
+                        ring->status_page.page_addr);
        return 0;
 }
 
@@ -1406,6 +1410,10 @@ static int i915_load_modeset_init(struct drm_device *dev,
        if (ret)
                goto destroy_ringbuffer;
 
+       /* IIR "flip pending" bit means done if this bit is set */
+       if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
+               dev_priv->flip_pending_is_done = true;
+
        intel_modeset_init(dev);
 
        ret = drm_irq_install(dev);
@@ -1491,6 +1499,10 @@ static void i915_pineview_get_mem_freq(struct drm_device *dev)
                dev_priv->mem_freq = 800;
                break;
        }
+
+       /* detect pineview DDR3 setting */
+       tmp = I915_READ(CSHRDDR3CTL);
+       dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 }
 
 static void i915_ironlake_get_mem_freq(struct drm_device *dev)