amd64_edac: dump DIMM sizes on K8 too

[net-next-2.6.git] / drivers / edac / amd64_edac.c

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c65ad2d57e06fd57b672cb871e75ad152c989249..c6d1aed2943fcbe341cdef2be9f4ed24c7ba890f 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -822,8 +822,7 @@ static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
 }
 
 
-static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
-                                        int ganged);
+static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt);
 
 static void amd64_dump_dramcfg_low(u32 dclr, int chan)
 {
@@ -875,8 +874,10 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
                (pvt->dhar & DHAR_VALID) ? "yes" : "no");
 
        /* everything below this point is Fam10h and above */
-       if (boot_cpu_data.x86 == 0xf)
+       if (boot_cpu_data.x86 == 0xf) {
+               amd64_debug_display_dimm_sizes(0, pvt);
                return;
+       }
 
        /* Only if NOT ganged does dclr1 have valid info */
        if (!dct_ganging_enabled(pvt))
@@ -888,10 +889,10 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
         */
        ganged = dct_ganging_enabled(pvt);
 
-       f10_debug_display_dimm_sizes(0, pvt, ganged);
+       amd64_debug_display_dimm_sizes(0, pvt);
 
        if (!ganged)
-               f10_debug_display_dimm_sizes(1, pvt, ganged);
+               amd64_debug_display_dimm_sizes(1, pvt);
 }
 
 /* Read in both of DBAM registers */
@@ -1726,23 +1727,31 @@ static int map_dbam_to_csrow_size(int index)
 }
 
 /*
- * debug routine to display the memory sizes of a DIMM (ganged or not) and it
+ * debug routine to display the memory sizes of all logical DIMMs and its
  * CSROWs as well
  */
-static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
-                                        int ganged)
+static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
 {
        int dimm, size0, size1;
        u32 dbam;
        u32 *dcsb;
 
-       debugf1("  dbam%d: 0x%8.08x  CSROW is %s\n", ctrl,
-                       ctrl ? pvt->dbam1 : pvt->dbam0,
-                       ganged ? "GANGED - dbam1 not used" : "NON-GANGED");
+       if (boot_cpu_data.x86 == 0xf) {
+               /* K8 families < revF not supported yet */
+              if (pvt->ext_model < OPTERON_CPU_REV_F)
+                       return;
+              else
+                      WARN_ON(ctrl != 0);
+       }
+
+       debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
+               ctrl, ctrl ? pvt->dbam1 : pvt->dbam0);
 
        dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
        dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0;
 
+       edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
+
        /* Dump memory sizes for DIMM and its CSROWs */
        for (dimm = 0; dimm < 4; dimm++) {
 
@@ -1754,15 +1763,8 @@ static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
                if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE)
                        size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam));
 
-               debugf1("     CTRL-%d DIMM-%d=%5dMB   CSROW-%d=%5dMB "
-                               "CSROW-%d=%5dMB\n",
-                               ctrl,
-                               dimm,
-                               size0 + size1,
-                               dimm * 2,
-                               size0,
-                               dimm * 2 + 1,
-                               size1);
+               edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n",
+                           dimm * 2, size0, dimm * 2 + 1, size1);
        }
 }