ARM: S5PV310: Bug fix on uclk1 and sclk_pwm

[net-next-2.6.git] / arch / arm / mach-s5pv310 / include / mach / regs-clock.h

diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 59e3a7e94d801c86e99dc6683466876d5b948567..4013553cd9be8de219ffb3cfbd51905b35f517c7 100644 (file)
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -15,48 +15,49 @@
 
 #include <mach/map.h>
 
-#define S5P_CLKREG(x)                  (S3C_VA_SYS + (x))
+#define S5P_CLKREG(x)                  (S5P_VA_CMU + (x))
 
 #define S5P_INFORM0                    S5P_CLKREG(0x800)
 
-#define S5P_EPLL_CON0                  S5P_CLKREG(0x1C110)
-#define S5P_EPLL_CON1                  S5P_CLKREG(0x1C114)
-#define S5P_VPLL_CON0                  S5P_CLKREG(0x1C120)
-#define S5P_VPLL_CON1                  S5P_CLKREG(0x1C124)
+#define S5P_EPLL_CON0                  S5P_CLKREG(0x0C110)
+#define S5P_EPLL_CON1                  S5P_CLKREG(0x0C114)
+#define S5P_VPLL_CON0                  S5P_CLKREG(0x0C120)
+#define S5P_VPLL_CON1                  S5P_CLKREG(0x0C124)
 
-#define S5P_CLKSRC_TOP0                        S5P_CLKREG(0x1C210)
-#define S5P_CLKSRC_TOP1                        S5P_CLKREG(0x1C214)
+#define S5P_CLKSRC_TOP0                        S5P_CLKREG(0x0C210)
+#define S5P_CLKSRC_TOP1                        S5P_CLKREG(0x0C214)
 
-#define S5P_CLKSRC_PERIL0              S5P_CLKREG(0x1C250)
+#define S5P_CLKSRC_PERIL0              S5P_CLKREG(0x0C250)
 
-#define S5P_CLKDIV_TOP                 S5P_CLKREG(0x1C510)
+#define S5P_CLKDIV_TOP                 S5P_CLKREG(0x0C510)
 
-#define S5P_CLKDIV_PERIL0              S5P_CLKREG(0x1C550)
-#define S5P_CLKDIV_PERIL1              S5P_CLKREG(0x1C554)
-#define S5P_CLKDIV_PERIL2              S5P_CLKREG(0x1C558)
-#define S5P_CLKDIV_PERIL3              S5P_CLKREG(0x1C55C)
-#define S5P_CLKDIV_PERIL4              S5P_CLKREG(0x1C560)
-#define S5P_CLKDIV_PERIL5              S5P_CLKREG(0x1C564)
+#define S5P_CLKDIV_PERIL0              S5P_CLKREG(0x0C550)
+#define S5P_CLKDIV_PERIL1              S5P_CLKREG(0x0C554)
+#define S5P_CLKDIV_PERIL2              S5P_CLKREG(0x0C558)
+#define S5P_CLKDIV_PERIL3              S5P_CLKREG(0x0C55C)
+#define S5P_CLKDIV_PERIL4              S5P_CLKREG(0x0C560)
+#define S5P_CLKDIV_PERIL5              S5P_CLKREG(0x0C564)
 
-#define S5P_CLKGATE_IP_PERIL           S5P_CLKREG(0x1C950)
+#define S5P_CLKSRC_MASK_PERIL0         S5P_CLKREG(0x0C350)
 
-#define S5P_CLKSRC_CORE                        S5P_CLKREG(0x20200)
+#define S5P_CLKGATE_IP_PERIL           S5P_CLKREG(0x0C950)
 
-#define S5P_CLKDIV_CORE0               S5P_CLKREG(0x20500)
+#define S5P_CLKSRC_CORE                        S5P_CLKREG(0x10200)
+#define S5P_CLKDIV_CORE0               S5P_CLKREG(0x10500)
 
-#define S5P_APLL_LOCK                  S5P_CLKREG(0x24000)
-#define S5P_MPLL_LOCK                  S5P_CLKREG(0x24004)
-#define S5P_APLL_CON0                  S5P_CLKREG(0x24100)
-#define S5P_APLL_CON1                  S5P_CLKREG(0x24104)
-#define S5P_MPLL_CON0                  S5P_CLKREG(0x24108)
-#define S5P_MPLL_CON1                  S5P_CLKREG(0x2410C)
+#define S5P_APLL_LOCK                  S5P_CLKREG(0x14000)
+#define S5P_MPLL_LOCK                  S5P_CLKREG(0x14004)
+#define S5P_APLL_CON0                  S5P_CLKREG(0x14100)
+#define S5P_APLL_CON1                  S5P_CLKREG(0x14104)
+#define S5P_MPLL_CON0                  S5P_CLKREG(0x14108)
+#define S5P_MPLL_CON1                  S5P_CLKREG(0x1410C)
 
-#define S5P_CLKSRC_CPU                 S5P_CLKREG(0x24200)
-#define S5P_CLKMUX_STATCPU             S5P_CLKREG(0x24400)
+#define S5P_CLKSRC_CPU                 S5P_CLKREG(0x14200)
+#define S5P_CLKMUX_STATCPU             S5P_CLKREG(0x14400)
 
-#define S5P_CLKDIV_CPU                 S5P_CLKREG(0x24500)
-#define S5P_CLKDIV_STATCPU             S5P_CLKREG(0x24600)
+#define S5P_CLKDIV_CPU                 S5P_CLKREG(0x14500)
+#define S5P_CLKDIV_STATCPU             S5P_CLKREG(0x14600)
 
-#define S5P_CLKGATE_SCLKCPU            S5P_CLKREG(0x24800)
+#define S5P_CLKGATE_SCLKCPU            S5P_CLKREG(0x14800)
 
 #endif /* __ASM_ARCH_REGS_CLOCK_H */