Merge branches 'clks' and 'pnx' into devel

[net-next-2.6.git] / arch / arm / include / asm / cacheflush.h

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index be8b4d79cf414690504a6e4d8669a8ed2b0a8e67..8148a009273a0d08c69dcc3f30cb16bb0a25d491 100644 (file)
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -154,16 +154,16 @@
  *     Please note that the implementation of these, and the required
  *     effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
- *     flush_cache_kern_all()
+ *     flush_kern_all()
  *
  *             Unconditionally clean and invalidate the entire cache.
  *
- *     flush_cache_user_mm(mm)
+ *     flush_user_all()
  *
  *             Clean and invalidate all user space cache entries
  *             before a change of page tables.
  *
- *     flush_cache_user_range(start, end, flags)
+ *     flush_user_range(start, end, flags)
  *
  *             Clean and invalidate a range of cache entries in the
  *             specified address space before a change of page tables.
@@ -179,6 +179,20 @@
  *             - start  - virtual start address
  *             - end    - virtual end address
  *
+ *     coherent_user_range(start, end)
+ *
+ *             Ensure coherency between the Icache and the Dcache in the
+ *             region described by start, end.  If you have non-snooping
+ *             Harvard caches, you need to implement this function.
+ *             - start  - virtual start address
+ *             - end    - virtual end address
+ *
+ *     flush_kern_dcache_area(kaddr, size)
+ *
+ *             Ensure that the data held in page is written back.
+ *             - kaddr  - page address
+ *             - size   - region size
+ *
  *     DMA Cache Coherency
  *     ===================
  *