select HAVE_IDE
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
+ select GENERIC_ATOMIC64 if (!CPU_32v6K)
select HAVE_OPROFILE
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_GENERIC_DMA_COHERENT
+ select HAVE_KERNEL_GZIP
+ select HAVE_KERNEL_LZO
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
help
bool
select GENERIC_ALLOCATOR
+config HAVE_PROC_CPU
+ bool
+
config NO_IOPORT
bool
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
+config ARM_L1_CACHE_SHIFT_6
+ bool
+ help
+ Setting ARM L1 cache line size to 64 Bytes.
+
if OPROFILE
config OPROFILE_ARMV6
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
+config ARCH_NUC93X
+ bool "Nuvoton NUC93X CPU"
+ select CPU_ARM926T
+ select HAVE_CLK
+ select COMMON_CLKDEV
+ help
+ Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
+ low-power and high performance MPEG-4/JPEG multimedia controller chip.
+
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
select GENERIC_GPIO
select HAVE_CLK
select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
help
Samsung S5PC1XX series based systems
select HAVE_IDE
select COMMON_CLKDEV
select GENERIC_ALLOCATOR
+ select ARCH_HAS_HOLES_MEMORYMODEL
help
Support for TI's DaVinci platform.
endchoice
+source "arch/arm/mach-aaec2000/Kconfig"
+
+source "arch/arm/mach-at91/Kconfig"
+
+source "arch/arm/mach-bcmring/Kconfig"
+
source "arch/arm/mach-clps711x/Kconfig"
+source "arch/arm/mach-davinci/Kconfig"
+
+source "arch/arm/mach-dove/Kconfig"
+
source "arch/arm/mach-ep93xx/Kconfig"
source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
+source "arch/arm/mach-h720x/Kconfig"
+
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-ixp23xx/Kconfig"
+source "arch/arm/mach-kirkwood/Kconfig"
+
+source "arch/arm/mach-ks8695/Kconfig"
+
+source "arch/arm/mach-lh7a40x/Kconfig"
+
source "arch/arm/mach-loki/Kconfig"
+source "arch/arm/mach-msm/Kconfig"
+
source "arch/arm/mach-mv78xx0/Kconfig"
-source "arch/arm/mach-pxa/Kconfig"
-source "arch/arm/plat-pxa/Kconfig"
+source "arch/arm/plat-mxc/Kconfig"
-source "arch/arm/mach-mmp/Kconfig"
+source "arch/arm/mach-netx/Kconfig"
-source "arch/arm/mach-sa1100/Kconfig"
+source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/plat-nomadik/Kconfig"
+
+source "arch/arm/mach-ns9xxx/Kconfig"
+
+source "arch/arm/mach-nuc93x/Kconfig"
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
-source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/mach-pxa/Kconfig"
+source "arch/arm/plat-pxa/Kconfig"
-source "arch/arm/mach-dove/Kconfig"
+source "arch/arm/mach-mmp/Kconfig"
+
+source "arch/arm/mach-realview/Kconfig"
+
+source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/mach-s5pc100/Kconfig"
endif
-source "arch/arm/mach-lh7a40x/Kconfig"
+source "arch/arm/mach-u300/Kconfig"
-source "arch/arm/mach-h720x/Kconfig"
+source "arch/arm/mach-ux500/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
-source "arch/arm/mach-aaec2000/Kconfig"
-
-source "arch/arm/mach-realview/Kconfig"
-
-source "arch/arm/mach-at91/Kconfig"
-
-source "arch/arm/plat-mxc/Kconfig"
-
-source "arch/arm/mach-nomadik/Kconfig"
-source "arch/arm/plat-nomadik/Kconfig"
-
-source "arch/arm/mach-netx/Kconfig"
-
-source "arch/arm/mach-ns9xxx/Kconfig"
-
-source "arch/arm/mach-davinci/Kconfig"
-
-source "arch/arm/mach-ks8695/Kconfig"
-
-source "arch/arm/mach-msm/Kconfig"
-
-source "arch/arm/mach-u300/Kconfig"
-
source "arch/arm/mach-w90x900/Kconfig"
-source "arch/arm/mach-bcmring/Kconfig"
-
-source "arch/arm/mach-ux500/Kconfig"
-
# Definitions to make life easier
config ARCH_ACORN
bool
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
+config PL310_ERRATA_588369
+ bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+ depends on CACHE_L2X0 && ARCH_OMAP4
+ help
+ The PL310 L2 cache controller implements three types of Clean &
+ Invalidate maintenance operations: by Physical Address
+ (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+ They are architecturally defined to behave as the execution of a
+ clean operation followed immediately by an invalidate operation,
+ both performing to the same memory location. This functionality
+ is not correctly implemented in PL310 as clean lines are not
+ invalidated as a result of these operations. Note that this errata
+ uses Texas Instrument's secure monitor api.
endmenu
source "arch/arm/common/Kconfig"
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
- depends on PERF_EVENTS && CPU_HAS_PMU && CPU_V6
+ depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
default y
help
Enable hardware performance counter support for perf events. If
bool
depends on CPU_CP15_MMU
default y if !ARCH_EBSA110
+ select HAVE_PROC_CPU if PROC_FS
help
ARM processors cannot fetch/store information which is not
naturally aligned on the bus, i.e., a 4 byte fetch must start at an
git://bbs.cooldavid.org / net-next-2.6.git / blobdiff