+ u32 phy_flags;
+#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
+#define TG3_PHYFLG_IS_CONNECTED 0x00000002
+#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
+#define TG3_PHYFLG_PHY_SERDES 0x00000010
+#define TG3_PHYFLG_MII_SERDES 0x00000020
+#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
+ TG3_PHYFLG_MII_SERDES)
+#define TG3_PHYFLG_IS_FET 0x00000040
+#define TG3_PHYFLG_10_100_ONLY 0x00000080
+#define TG3_PHYFLG_ENABLE_APD 0x00000100
+#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
+#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
+#define TG3_PHYFLG_JITTER_BUG 0x00000800
+#define TG3_PHYFLG_ADJUST_TRIM 0x00001000
+#define TG3_PHYFLG_ADC_BUG 0x00002000
+#define TG3_PHYFLG_5704_A0_BUG 0x00004000
+#define TG3_PHYFLG_BER_BUG 0x00008000
+#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
+#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
+