Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

[net-next-2.6.git] / arch / arm / Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 12115ffbbb309bc1799bc8760069de1ac8bc33dd..9b2ef2fb3caea4e10caa6d4688c3c04518973590 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -19,13 +19,17 @@ config ARM
        select HAVE_KPROBES if (!XIP_KERNEL)
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
        select HAVE_KPROBES if (!XIP_KERNEL)
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)

+       select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
+       select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)

        select HAVE_GENERIC_DMA_COHERENT
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZO
        select HAVE_KERNEL_LZMA
        select HAVE_GENERIC_DMA_COHERENT
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZO
        select HAVE_KERNEL_LZMA

+       select HAVE_IRQ_WORK

        select HAVE_PERF_EVENTS
        select PERF_USE_VMALLOC
        select HAVE_REGS_AND_STACK_ACCESS_API
        select HAVE_PERF_EVENTS
        select PERF_USE_VMALLOC
        select HAVE_REGS_AND_STACK_ACCESS_API

+       select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))

        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and


@@ -145,6 +149,9 @@ config ARCH_HAS_CPUFREQ
          and that the relevant menu configurations are displayed for
          it.
 
          and that the relevant menu configurations are displayed for
          it.
 

+config ARCH_HAS_CPU_IDLE_WAIT
+       def_bool y
+

 config GENERIC_HWEIGHT
        bool
        default y
 config GENERIC_HWEIGHT
        bool
        default y


@@ -271,7 +278,6 @@ config ARCH_AT91
        bool "Atmel AT91"
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_CLK
        bool "Atmel AT91"
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_CLK

-       select ARCH_USES_GETTIMEOFFSET

        help
          This enables support for systems based on the Atmel AT91RM9200,
          AT91SAM9 and AT91CAP9 processors.
        help
          This enables support for systems based on the Atmel AT91RM9200,
          AT91SAM9 and AT91CAP9 processors.


@@ -511,6 +517,7 @@ config ARCH_MMP
        select GENERIC_CLOCKEVENTS
        select TICK_ONESHOT
        select PLAT_PXA
        select GENERIC_CLOCKEVENTS
        select TICK_ONESHOT
        select PLAT_PXA

+       select SPARSE_IRQ

        help
          Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
        help
          Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 


@@ -566,6 +573,7 @@ config ARCH_TEGRA
        select HAVE_CLK
        select COMMON_CLKDEV
        select ARCH_HAS_BARRIERS if CACHE_L2X0
        select HAVE_CLK
        select COMMON_CLKDEV
        select ARCH_HAS_BARRIERS if CACHE_L2X0

+       select ARCH_HAS_CPUFREQ

        help
          This enables support for NVIDIA Tegra based systems (Tegra APX,
          Tegra 6xx and Tegra 2 series).
        help
          This enables support for NVIDIA Tegra based systems (Tegra APX,
          Tegra 6xx and Tegra 2 series).


@@ -588,6 +596,7 @@ config ARCH_PXA
        select GENERIC_CLOCKEVENTS
        select TICK_ONESHOT
        select PLAT_PXA
        select GENERIC_CLOCKEVENTS
        select TICK_ONESHOT
        select PLAT_PXA

+       select SPARSE_IRQ

        help
          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
        help
          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 


@@ -679,8 +688,8 @@ config ARCH_S3C64XX
        help
          Samsung S3C64XX series based systems
 
        help
          Samsung S3C64XX series based systems
 

-config ARCH_S5P6440
-       bool "Samsung S5P6440"
+config ARCH_S5P64X0
+       bool "Samsung S5P6440 S5P6450"

        select CPU_V6
        select GENERIC_GPIO
        select HAVE_CLK
        select CPU_V6
        select GENERIC_GPIO
        select HAVE_CLK


@@ -689,7 +698,8 @@ config ARCH_S5P6440
        select HAVE_S3C2410_I2C
        select HAVE_S3C_RTC
        help
        select HAVE_S3C2410_I2C
        select HAVE_S3C_RTC
        help

-         Samsung S5P6440 CPU based systems
+         Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
+         SMDK6450.

 
 config ARCH_S5P6442
        bool "Samsung S5P6442"
 
 config ARCH_S5P6442
        bool "Samsung S5P6442"


@@ -748,6 +758,15 @@ config ARCH_SHARK
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
 
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
 

+config ARCH_TCC_926
+       bool "Telechips TCC ARM926-based systems"
+       select CPU_ARM926T
+       select HAVE_CLK
+       select COMMON_CLKDEV
+       select GENERIC_CLOCKEVENTS
+       help
+         Support for Telechips TCC ARM926-based systems.
+

 config ARCH_LH7A40X
        bool "Sharp LH7A40X"
        select CPU_ARM922T
 config ARCH_LH7A40X
        bool "Sharp LH7A40X"
        select CPU_ARM922T


@@ -813,7 +832,7 @@ config ARCH_OMAP
        select GENERIC_CLOCKEVENTS
        select ARCH_HAS_HOLES_MEMORYMODEL
        help
        select GENERIC_CLOCKEVENTS
        select ARCH_HAS_HOLES_MEMORYMODEL
        help

-         Support for TI's OMAP platform (OMAP1 and OMAP2).
+         Support for TI's OMAP platform (OMAP1/2/3/4).

 
 config PLAT_SPEAR
        bool "ST SPEAr"
 
 config PLAT_SPEAR
        bool "ST SPEAr"


@@ -916,6 +935,8 @@ source "arch/arm/plat-s5p/Kconfig"
 
 source "arch/arm/plat-spear/Kconfig"
 
 
 source "arch/arm/plat-spear/Kconfig"
 

+source "arch/arm/plat-tcc/Kconfig"
+

 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"


@@ -929,7 +950,7 @@ if ARCH_S3C64XX
 source "arch/arm/mach-s3c64xx/Kconfig"
 endif
 
 source "arch/arm/mach-s3c64xx/Kconfig"
 endif
 

-source "arch/arm/mach-s5p6440/Kconfig"
+source "arch/arm/mach-s5p64x0/Kconfig"

 
 source "arch/arm/mach-s5p6442/Kconfig"
 
 
 source "arch/arm/mach-s5p6442/Kconfig"
 


@@ -1003,7 +1024,7 @@ endif
 
 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 
 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

-       depends on CPU_V6 && !SMP
+       depends on CPU_V6

        help
          Invalidation of the Instruction Cache operation can
          fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
        help
          Invalidation of the Instruction Cache operation can
          fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.


@@ -1051,6 +1072,32 @@ config ARM_ERRATA_460075
          ACTLR register. Note that setting specific bits in the ACTLR register
          may not be available in non-secure mode.
 
          ACTLR register. Note that setting specific bits in the ACTLR register
          may not be available in non-secure mode.
 

+config ARM_ERRATA_742230
+       bool "ARM errata: DMB operation may be faulty"
+       depends on CPU_V7 && SMP
+       help
+         This option enables the workaround for the 742230 Cortex-A9
+         (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
+         between two write operations may not ensure the correct visibility
+         ordering of the two writes. This workaround sets a specific bit in
+         the diagnostic register of the Cortex-A9 which causes the DMB
+         instruction to behave as a DSB, ensuring the correct behaviour of
+         the two writes.
+
+config ARM_ERRATA_742231
+       bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
+       depends on CPU_V7 && SMP
+       help
+         This option enables the workaround for the 742231 Cortex-A9
+         (r2p0..r2p2) erratum. Under certain conditions, specific to the
+         Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
+         accessing some data located in the same cache line, may get corrupted
+         data due to bad handling of the address hazard when the line gets
+         replaced from one of the CPUs at the same time as another CPU is
+         accessing it. This workaround sets specific bits in the diagnostic
+         register of the Cortex-A9 which reduces the linefill issuing
+         capabilities of the processor.
+

 config PL310_ERRATA_588369
        bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
        depends on CACHE_L2X0 && ARCH_OMAP4
 config PL310_ERRATA_588369
        bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
        depends on CACHE_L2X0 && ARCH_OMAP4


@@ -1076,6 +1123,20 @@ config ARM_ERRATA_720789
          invalidated are not, resulting in an incoherency in the system page
          tables. The workaround changes the TLB flushing routines to invalidate
          entries regardless of the ASID.
          invalidated are not, resulting in an incoherency in the system page
          tables. The workaround changes the TLB flushing routines to invalidate
          entries regardless of the ASID.

+
+config ARM_ERRATA_743622
+       bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 743622 Cortex-A9
+         (r2p0..r2p2) erratum. Under very rare conditions, a faulty
+         optimisation in the Cortex-A9 Store Buffer may lead to data
+         corruption. This workaround sets a specific bit in the diagnostic
+         register of the Cortex-A9 which disables the Store Buffer
+         optimisation, preventing the defect from occurring. This has no
+         visible impact on the overall performance or power consumption of the
+         processor.
+

 endmenu
 
 source "arch/arm/common/Kconfig"
 endmenu
 
 source "arch/arm/common/Kconfig"


@@ -1142,13 +1203,13 @@ source "kernel/time/Kconfig"
 
 config SMP
        bool "Symmetric Multi-Processing (EXPERIMENTAL)"
 
 config SMP
        bool "Symmetric Multi-Processing (EXPERIMENTAL)"

-       depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
-                MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-                ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+       depends on EXPERIMENTAL

        depends on GENERIC_CLOCKEVENTS
        depends on GENERIC_CLOCKEVENTS

+       depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
+                MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
+                ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4

        select USE_GENERIC_SMP_HELPERS
        select USE_GENERIC_SMP_HELPERS

-       select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\
-                ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+       select HAVE_ARM_SCU

        help
          This enables support for systems with more than one CPU. If you have
          a system with only one CPU, like most personal computers, say N. If
        help
          This enables support for systems with more than one CPU. If you have
          a system with only one CPU, like most personal computers, say N. If


@@ -1162,10 +1223,23 @@ config SMP
 
          See also <file:Documentation/i386/IO-APIC.txt>,
          <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
 
          See also <file:Documentation/i386/IO-APIC.txt>,
          <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at

-         <http://www.linuxdoc.org/docs.html#howto>.
+         <http://tldp.org/HOWTO/SMP-HOWTO.html>.

 
          If you don't know what to do here, say N.
 
 
          If you don't know what to do here, say N.
 

+config SMP_ON_UP
+       bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+       depends on EXPERIMENTAL
+       depends on SMP && !XIP && !THUMB2_KERNEL
+       default y
+       help
+         SMP kernels contain instructions which fail on non-SMP processors.
+         Enabling this option allows the kernel to modify itself to make
+         these instructions safe.  Disabling it allows about 1K of space
+         savings.
+
+         If you don't know what to do here, say Y.
+

 config HAVE_ARM_SCU
        bool
        depends on SMP
 config HAVE_ARM_SCU
        bool
        depends on SMP


@@ -1216,12 +1290,9 @@ config HOTPLUG_CPU
 
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
 
 config LOCAL_TIMERS
        bool "Use local timer interrupts"

-       depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-               REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
-               ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+       depends on SMP

        default y
        default y

-       select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 || \
-               ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS
+       select HAVE_ARM_TWD

        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system
        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system


@@ -1232,7 +1303,7 @@ source kernel/Kconfig.preempt
 
 config HZ
        int
 
 config HZ
        int

-       default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
+       default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \

                ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
        default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
        default AT91_TIMER_HZ if ARCH_AT91
                ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
        default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
        default AT91_TIMER_HZ if ARCH_AT91


@@ -1438,6 +1509,20 @@ config UACCESS_WITH_MEMCPY
          However, if the CPU data cache is using a write-allocate mode,
          this option is unlikely to provide any performance gain.
 
          However, if the CPU data cache is using a write-allocate mode,
          this option is unlikely to provide any performance gain.
 

+config SECCOMP
+       bool
+       prompt "Enable seccomp to safely compute untrusted bytecode"
+       ---help---
+         This kernel feature is useful for number crunching applications
+         that may need to compute untrusted bytecode during their
+         execution. By using pipes or other transports made available to
+         the process as file descriptors supporting the read/write
+         syscalls, it's possible to isolate those applications in
+         their own address space using seccomp. Once seccomp is
+         enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+         and the task is only allowed to execute a few safe syscalls
+         defined by each seccomp mode.
+

 config CC_STACKPROTECTOR
        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
        help
 config CC_STACKPROTECTOR
        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
        help