sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/slab.h>
  29
  30 #include <sound/core.h>
  31 #include <sound/pcm.h>
  32 #include <sound/pcm_params.h>
  33 #include <sound/soc.h>
  34 #include <sound/soc-dapm.h>
  35 #include <sound/tlv.h>
  36 #include <sound/initval.h>
  37 #include <asm/div64.h>
  38
  39 #include "wm8580.h"
  40
  41 /* WM8580 register space */
  42 #define WM8580_PLLA1                         0x00
  43 #define WM8580_PLLA2                         0x01
  44 #define WM8580_PLLA3                         0x02
  45 #define WM8580_PLLA4                         0x03
  46 #define WM8580_PLLB1                         0x04
  47 #define WM8580_PLLB2                         0x05
  48 #define WM8580_PLLB3                         0x06
  49 #define WM8580_PLLB4                         0x07
  50 #define WM8580_CLKSEL                        0x08
  51 #define WM8580_PAIF1                         0x09
  52 #define WM8580_PAIF2                         0x0A
  53 #define WM8580_SAIF1                         0x0B
  54 #define WM8580_PAIF3                         0x0C
  55 #define WM8580_PAIF4                         0x0D
  56 #define WM8580_SAIF2                         0x0E
  57 #define WM8580_DAC_CONTROL1                  0x0F
  58 #define WM8580_DAC_CONTROL2                  0x10
  59 #define WM8580_DAC_CONTROL3                  0x11
  60 #define WM8580_DAC_CONTROL4                  0x12
  61 #define WM8580_DAC_CONTROL5                  0x13
  62 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  63 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  64 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  65 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  66 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  67 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  68 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  69 #define WM8580_ADC_CONTROL1                  0x1D
  70 #define WM8580_SPDTXCHAN0                    0x1E
  71 #define WM8580_SPDTXCHAN1                    0x1F
  72 #define WM8580_SPDTXCHAN2                    0x20
  73 #define WM8580_SPDTXCHAN3                    0x21
  74 #define WM8580_SPDTXCHAN4                    0x22
  75 #define WM8580_SPDTXCHAN5                    0x23
  76 #define WM8580_SPDMODE                       0x24
  77 #define WM8580_INTMASK                       0x25
  78 #define WM8580_GPO1                          0x26
  79 #define WM8580_GPO2                          0x27
  80 #define WM8580_GPO3                          0x28
  81 #define WM8580_GPO4                          0x29
  82 #define WM8580_GPO5                          0x2A
  83 #define WM8580_INTSTAT                       0x2B
  84 #define WM8580_SPDRXCHAN1                    0x2C
  85 #define WM8580_SPDRXCHAN2                    0x2D
  86 #define WM8580_SPDRXCHAN3                    0x2E
  87 #define WM8580_SPDRXCHAN4                    0x2F
  88 #define WM8580_SPDRXCHAN5                    0x30
  89 #define WM8580_SPDSTAT                       0x31
  90 #define WM8580_PWRDN1                        0x32
  91 #define WM8580_PWRDN2                        0x33
  92 #define WM8580_READBACK                      0x34
  93 #define WM8580_RESET                         0x35
  94
  95 #define WM8580_MAX_REGISTER                  0x35
  96
  97 /* PLLB4 (register 7h) */
  98 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
  99 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 100 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 101 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 102
 103 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 104 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 105 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 106 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 107
 108 /* CLKSEL (register 8h) */
 109 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 110 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 111 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 112
 113 /* AIF control 1 (registers 9h-bh) */
 114 #define WM8580_AIF_RATE_MASK       0x7
 115 #define WM8580_AIF_BCLKSEL_MASK   0x18
 116
 117 #define WM8580_AIF_MS             0x20
 118
 119 #define WM8580_AIF_CLKSRC_MASK    0xc0
 120 #define WM8580_AIF_CLKSRC_PLLA    0x40
 121 #define WM8580_AIF_CLKSRC_PLLB    0x40
 122 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 123
 124 /* AIF control 2 (registers ch-eh) */
 125 #define WM8580_AIF_FMT_MASK    0x03
 126 #define WM8580_AIF_FMT_RIGHTJ  0x00
 127 #define WM8580_AIF_FMT_LEFTJ   0x01
 128 #define WM8580_AIF_FMT_I2S     0x02
 129 #define WM8580_AIF_FMT_DSP     0x03
 130
 131 #define WM8580_AIF_LENGTH_MASK   0x0c
 132 #define WM8580_AIF_LENGTH_16     0x00
 133 #define WM8580_AIF_LENGTH_20     0x04
 134 #define WM8580_AIF_LENGTH_24     0x08
 135 #define WM8580_AIF_LENGTH_32     0x0c
 136
 137 #define WM8580_AIF_LRP         0x10
 138 #define WM8580_AIF_BCP         0x20
 139
 140 /* Powerdown Register 1 (register 32h) */
 141 #define WM8580_PWRDN1_PWDN     0x001
 142 #define WM8580_PWRDN1_ALLDACPD 0x040
 143
 144 /* Powerdown Register 2 (register 33h) */
 145 #define WM8580_PWRDN2_OSSCPD   0x001
 146 #define WM8580_PWRDN2_PLLAPD   0x002
 147 #define WM8580_PWRDN2_PLLBPD   0x004
 148 #define WM8580_PWRDN2_SPDIFPD  0x008
 149 #define WM8580_PWRDN2_SPDIFTXD 0x010
 150 #define WM8580_PWRDN2_SPDIFRXD 0x020
 151
 152 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 153
 154 /*
 155  * wm8580 register cache
 156  * We can't read the WM8580 register space when we
 157  * are using 2 wire for device control, so we cache them instead.
 158  */
 159 static const u16 wm8580_reg[] = {
 160         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 161         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 162         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 163         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 164         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 165         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 166         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 167         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 168         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 169         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 170         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 171         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 172         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 173         0x0000, 0x0000 /*R53*/
 174 };
 175
 176 struct pll_state {
 177         unsigned int in;
 178         unsigned int out;
 179 };
 180
 181 #define WM8580_NUM_SUPPLIES 3
 182 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 183         "AVDD",
 184         "DVDD",
 185         "PVDD",
 186 };
 187
 188 /* codec private data */
 189 struct wm8580_priv {
 190         enum snd_soc_control_type control_type;
 191         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 192         u16 reg_cache[WM8580_MAX_REGISTER + 1];
 193         struct pll_state a;
 194         struct pll_state b;
 195 };
 196
 197 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 198
 199 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 200                          struct snd_ctl_elem_value *ucontrol)
 201 {
 202         struct soc_mixer_control *mc =
 203                 (struct soc_mixer_control *)kcontrol->private_value;
 204         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 205         u16 *reg_cache = codec->reg_cache;
 206         unsigned int reg = mc->reg;
 207         unsigned int reg2 = mc->rreg;
 208         int ret;
 209
 210         /* Clear the register cache so we write without VU set */
 211         reg_cache[reg] = 0;
 212         reg_cache[reg2] = 0;
 213
 214         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 215         if (ret < 0)
 216                 return ret;
 217
 218         /* Now write again with the volume update bit set */
 219         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 220         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 221
 222         return 0;
 223 }
 224
 225 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 226                                     xinvert, tlv_array)                 \
 227 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 228         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 229                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 230         .tlv.p = (tlv_array), \
 231         .info = snd_soc_info_volsw_2r, \
 232         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 233         .private_value = (unsigned long)&(struct soc_mixer_control) \
 234                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 235                 .max = xmax, .invert = xinvert} }
 236
 237 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 238 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 239                             WM8580_DIGITAL_ATTENUATION_DACL1,
 240                             WM8580_DIGITAL_ATTENUATION_DACR1,
 241                             0, 0xff, 0, dac_tlv),
 242 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 243                             WM8580_DIGITAL_ATTENUATION_DACL2,
 244                             WM8580_DIGITAL_ATTENUATION_DACR2,
 245                             0, 0xff, 0, dac_tlv),
 246 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 247                             WM8580_DIGITAL_ATTENUATION_DACL3,
 248                             WM8580_DIGITAL_ATTENUATION_DACR3,
 249                             0, 0xff, 0, dac_tlv),
 250
 251 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 252 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 253 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 254
 255 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 256 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 257 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 258
 259 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 260 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
 261 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
 262 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
 263
 264 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
 265 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 266 };
 267
 268 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 269 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 270 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 271 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 272
 273 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 274 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 275 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 276 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 277 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 278 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 279
 280 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 281
 282 SND_SOC_DAPM_INPUT("AINL"),
 283 SND_SOC_DAPM_INPUT("AINR"),
 284 };
 285
 286 static const struct snd_soc_dapm_route audio_map[] = {
 287         { "VOUT1L", NULL, "DAC1" },
 288         { "VOUT1R", NULL, "DAC1" },
 289
 290         { "VOUT2L", NULL, "DAC2" },
 291         { "VOUT2R", NULL, "DAC2" },
 292
 293         { "VOUT3L", NULL, "DAC3" },
 294         { "VOUT3R", NULL, "DAC3" },
 295
 296         { "ADC", NULL, "AINL" },
 297         { "ADC", NULL, "AINR" },
 298 };
 299
 300 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 301 {
 302         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 303                                   ARRAY_SIZE(wm8580_dapm_widgets));
 304
 305         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 306
 307         return 0;
 308 }
 309
 310 /* PLL divisors */
 311 struct _pll_div {
 312         u32 prescale:1;
 313         u32 postscale:1;
 314         u32 freqmode:2;
 315         u32 n:4;
 316         u32 k:24;
 317 };
 318
 319 /* The size in bits of the pll divide */
 320 #define FIXED_PLL_SIZE (1 << 22)
 321
 322 /* PLL rate to output rate divisions */
 323 static struct {
 324         unsigned int div;
 325         unsigned int freqmode;
 326         unsigned int postscale;
 327 } post_table[] = {
 328         {  2,  0, 0 },
 329         {  4,  0, 1 },
 330         {  4,  1, 0 },
 331         {  8,  1, 1 },
 332         {  8,  2, 0 },
 333         { 16,  2, 1 },
 334         { 12,  3, 0 },
 335         { 24,  3, 1 }
 336 };
 337
 338 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 339                        unsigned int source)
 340 {
 341         u64 Kpart;
 342         unsigned int K, Ndiv, Nmod;
 343         int i;
 344
 345         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 346
 347         /* Scale the output frequency up; the PLL should run in the
 348          * region of 90-100MHz.
 349          */
 350         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 351                 if (target * post_table[i].div >=  90000000 &&
 352                     target * post_table[i].div <= 100000000) {
 353                         pll_div->freqmode = post_table[i].freqmode;
 354                         pll_div->postscale = post_table[i].postscale;
 355                         target *= post_table[i].div;
 356                         break;
 357                 }
 358         }
 359
 360         if (i == ARRAY_SIZE(post_table)) {
 361                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 362                        "%u\n", target);
 363                 return -EINVAL;
 364         }
 365
 366         Ndiv = target / source;
 367
 368         if (Ndiv < 5) {
 369                 source /= 2;
 370                 pll_div->prescale = 1;
 371                 Ndiv = target / source;
 372         } else
 373                 pll_div->prescale = 0;
 374
 375         if ((Ndiv < 5) || (Ndiv > 13)) {
 376                 printk(KERN_ERR
 377                         "WM8580 N=%u outside supported range\n", Ndiv);
 378                 return -EINVAL;
 379         }
 380
 381         pll_div->n = Ndiv;
 382         Nmod = target % source;
 383         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 384
 385         do_div(Kpart, source);
 386
 387         K = Kpart & 0xFFFFFFFF;
 388
 389         pll_div->k = K;
 390
 391         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 392                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 393                  pll_div->postscale);
 394
 395         return 0;
 396 }
 397
 398 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 399                 int source, unsigned int freq_in, unsigned int freq_out)
 400 {
 401         int offset;
 402         struct snd_soc_codec *codec = codec_dai->codec;
 403         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 404         struct pll_state *state;
 405         struct _pll_div pll_div;
 406         unsigned int reg;
 407         unsigned int pwr_mask;
 408         int ret;
 409
 410         /* GCC isn't able to work out the ifs below for initialising/using
 411          * pll_div so suppress warnings.
 412          */
 413         memset(&pll_div, 0, sizeof(pll_div));
 414
 415         switch (pll_id) {
 416         case WM8580_PLLA:
 417                 state = &wm8580->a;
 418                 offset = 0;
 419                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 420                 break;
 421         case WM8580_PLLB:
 422                 state = &wm8580->b;
 423                 offset = 4;
 424                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 425                 break;
 426         default:
 427                 return -ENODEV;
 428         }
 429
 430         if (freq_in && freq_out) {
 431                 ret = pll_factors(&pll_div, freq_out, freq_in);
 432                 if (ret != 0)
 433                         return ret;
 434         }
 435
 436         state->in = freq_in;
 437         state->out = freq_out;
 438
 439         /* Always disable the PLL - it is not safe to leave it running
 440          * while reprogramming it.
 441          */
 442         reg = snd_soc_read(codec, WM8580_PWRDN2);
 443         snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 444
 445         if (!freq_in || !freq_out)
 446                 return 0;
 447
 448         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 449         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 450         snd_soc_write(codec, WM8580_PLLA3 + offset,
 451                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 452
 453         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 454         reg &= ~0x1b;
 455         reg |= pll_div.prescale | pll_div.postscale << 1 |
 456                 pll_div.freqmode << 3;
 457
 458         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 459
 460         /* All done, turn it on */
 461         reg = snd_soc_read(codec, WM8580_PWRDN2);
 462         snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 463
 464         return 0;
 465 }
 466
 467 /*
 468  * Set PCM DAI bit size and sample rate.
 469  */
 470 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 471                                  struct snd_pcm_hw_params *params,
 472                                  struct snd_soc_dai *dai)
 473 {
 474         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 475         struct snd_soc_codec *codec = rtd->codec;
 476         u16 paifb = 0;
 477
 478         /* bit size */
 479         switch (params_format(params)) {
 480         case SNDRV_PCM_FORMAT_S16_LE:
 481                 break;
 482         case SNDRV_PCM_FORMAT_S20_3LE:
 483                 paifb |= WM8580_AIF_LENGTH_20;
 484                 break;
 485         case SNDRV_PCM_FORMAT_S24_LE:
 486                 paifb |= WM8580_AIF_LENGTH_24;
 487                 break;
 488         case SNDRV_PCM_FORMAT_S32_LE:
 489                 paifb |= WM8580_AIF_LENGTH_24;
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
 496                             WM8580_AIF_LENGTH_MASK, paifb);
 497         return 0;
 498 }
 499
 500 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 501                                       unsigned int fmt)
 502 {
 503         struct snd_soc_codec *codec = codec_dai->codec;
 504         unsigned int aifa;
 505         unsigned int aifb;
 506         int can_invert_lrclk;
 507
 508         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
 509         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 510
 511         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 512
 513         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 514         case SND_SOC_DAIFMT_CBS_CFS:
 515                 aifa &= ~WM8580_AIF_MS;
 516                 break;
 517         case SND_SOC_DAIFMT_CBM_CFM:
 518                 aifa |= WM8580_AIF_MS;
 519                 break;
 520         default:
 521                 return -EINVAL;
 522         }
 523
 524         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 525         case SND_SOC_DAIFMT_I2S:
 526                 can_invert_lrclk = 1;
 527                 aifb |= WM8580_AIF_FMT_I2S;
 528                 break;
 529         case SND_SOC_DAIFMT_RIGHT_J:
 530                 can_invert_lrclk = 1;
 531                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 532                 break;
 533         case SND_SOC_DAIFMT_LEFT_J:
 534                 can_invert_lrclk = 1;
 535                 aifb |= WM8580_AIF_FMT_LEFTJ;
 536                 break;
 537         case SND_SOC_DAIFMT_DSP_A:
 538                 can_invert_lrclk = 0;
 539                 aifb |= WM8580_AIF_FMT_DSP;
 540                 break;
 541         case SND_SOC_DAIFMT_DSP_B:
 542                 can_invert_lrclk = 0;
 543                 aifb |= WM8580_AIF_FMT_DSP;
 544                 aifb |= WM8580_AIF_LRP;
 545                 break;
 546         default:
 547                 return -EINVAL;
 548         }
 549
 550         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 551         case SND_SOC_DAIFMT_NB_NF:
 552                 break;
 553
 554         case SND_SOC_DAIFMT_IB_IF:
 555                 if (!can_invert_lrclk)
 556                         return -EINVAL;
 557                 aifb |= WM8580_AIF_BCP;
 558                 aifb |= WM8580_AIF_LRP;
 559                 break;
 560
 561         case SND_SOC_DAIFMT_IB_NF:
 562                 aifb |= WM8580_AIF_BCP;
 563                 break;
 564
 565         case SND_SOC_DAIFMT_NB_IF:
 566                 if (!can_invert_lrclk)
 567                         return -EINVAL;
 568                 aifb |= WM8580_AIF_LRP;
 569                 break;
 570
 571         default:
 572                 return -EINVAL;
 573         }
 574
 575         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
 576         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 577
 578         return 0;
 579 }
 580
 581 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 582                                  int div_id, int div)
 583 {
 584         struct snd_soc_codec *codec = codec_dai->codec;
 585         unsigned int reg;
 586
 587         switch (div_id) {
 588         case WM8580_MCLK:
 589                 reg = snd_soc_read(codec, WM8580_PLLB4);
 590                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 591
 592                 switch (div) {
 593                 case WM8580_CLKSRC_MCLK:
 594                         /* Input */
 595                         break;
 596
 597                 case WM8580_CLKSRC_PLLA:
 598                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 599                         break;
 600                 case WM8580_CLKSRC_PLLB:
 601                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 602                         break;
 603
 604                 case WM8580_CLKSRC_OSC:
 605                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 606                         break;
 607
 608                 default:
 609                         return -EINVAL;
 610                 }
 611                 snd_soc_write(codec, WM8580_PLLB4, reg);
 612                 break;
 613
 614         case WM8580_DAC_CLKSEL:
 615                 reg = snd_soc_read(codec, WM8580_CLKSEL);
 616                 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
 617
 618                 switch (div) {
 619                 case WM8580_CLKSRC_MCLK:
 620                         break;
 621
 622                 case WM8580_CLKSRC_PLLA:
 623                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
 624                         break;
 625
 626                 case WM8580_CLKSRC_PLLB:
 627                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
 628                         break;
 629
 630                 default:
 631                         return -EINVAL;
 632                 }
 633                 snd_soc_write(codec, WM8580_CLKSEL, reg);
 634                 break;
 635
 636         case WM8580_CLKOUTSRC:
 637                 reg = snd_soc_read(codec, WM8580_PLLB4);
 638                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 639
 640                 switch (div) {
 641                 case WM8580_CLKSRC_NONE:
 642                         break;
 643
 644                 case WM8580_CLKSRC_PLLA:
 645                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 646                         break;
 647
 648                 case WM8580_CLKSRC_PLLB:
 649                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 650                         break;
 651
 652                 case WM8580_CLKSRC_OSC:
 653                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 654                         break;
 655
 656                 default:
 657                         return -EINVAL;
 658                 }
 659                 snd_soc_write(codec, WM8580_PLLB4, reg);
 660                 break;
 661
 662         default:
 663                 return -EINVAL;
 664         }
 665
 666         return 0;
 667 }
 668
 669 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 670 {
 671         struct snd_soc_codec *codec = codec_dai->codec;
 672         unsigned int reg;
 673
 674         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 675
 676         if (mute)
 677                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 678         else
 679                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 680
 681         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 682
 683         return 0;
 684 }
 685
 686 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 687         enum snd_soc_bias_level level)
 688 {
 689         u16 reg;
 690         switch (level) {
 691         case SND_SOC_BIAS_ON:
 692         case SND_SOC_BIAS_PREPARE:
 693                 break;
 694
 695         case SND_SOC_BIAS_STANDBY:
 696                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 697                         /* Power up and get individual control of the DACs */
 698                         reg = snd_soc_read(codec, WM8580_PWRDN1);
 699                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
 700                         snd_soc_write(codec, WM8580_PWRDN1, reg);
 701
 702                         /* Make VMID high impedence */
 703                         reg = snd_soc_read(codec,  WM8580_ADC_CONTROL1);
 704                         reg &= ~0x100;
 705                         snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
 706                 }
 707                 break;
 708
 709         case SND_SOC_BIAS_OFF:
 710                 reg = snd_soc_read(codec, WM8580_PWRDN1);
 711                 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 712                 break;
 713         }
 714         codec->bias_level = level;
 715         return 0;
 716 }
 717
 718 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 719                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 720
 721 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 722         .hw_params      = wm8580_paif_hw_params,
 723         .set_fmt        = wm8580_set_paif_dai_fmt,
 724         .set_clkdiv     = wm8580_set_dai_clkdiv,
 725         .set_pll        = wm8580_set_dai_pll,
 726         .digital_mute   = wm8580_digital_mute,
 727 };
 728
 729 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 730         .hw_params      = wm8580_paif_hw_params,
 731         .set_fmt        = wm8580_set_paif_dai_fmt,
 732         .set_clkdiv     = wm8580_set_dai_clkdiv,
 733         .set_pll        = wm8580_set_dai_pll,
 734 };
 735
 736 static struct snd_soc_dai_driver wm8580_dai[] = {
 737         {
 738                 .name = "wm8580-hifi-playback",
 739                 .id     = WM8580_DAI_PAIFRX,
 740                 .playback = {
 741                         .stream_name = "Playback",
 742                         .channels_min = 1,
 743                         .channels_max = 6,
 744                         .rates = SNDRV_PCM_RATE_8000_192000,
 745                         .formats = WM8580_FORMATS,
 746                 },
 747                 .ops = &wm8580_dai_ops_playback,
 748         },
 749         {
 750                 .name = "wm8580-hifi-capture",
 751                 .id     =       WM8580_DAI_PAIFTX,
 752                 .capture = {
 753                         .stream_name = "Capture",
 754                         .channels_min = 2,
 755                         .channels_max = 2,
 756                         .rates = SNDRV_PCM_RATE_8000_192000,
 757                         .formats = WM8580_FORMATS,
 758                 },
 759                 .ops = &wm8580_dai_ops_capture,
 760         },
 761 };
 762
 763 static int wm8580_probe(struct snd_soc_codec *codec)
 764 {
 765         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 766         int ret = 0,i;
 767
 768         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
 769         if (ret < 0) {
 770                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 771                 return ret;
 772         }
 773
 774         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 775                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 776
 777         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 778                                  wm8580->supplies);
 779         if (ret != 0) {
 780                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 781                 return ret;
 782         }
 783
 784         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 785                                     wm8580->supplies);
 786         if (ret != 0) {
 787                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 788                 goto err_regulator_get;
 789         }
 790
 791         /* Get the codec into a known state */
 792         ret = snd_soc_write(codec, WM8580_RESET, 0);
 793         if (ret != 0) {
 794                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 795                 goto err_regulator_enable;
 796         }
 797
 798         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 799
 800         snd_soc_add_controls(codec, wm8580_snd_controls,
 801                              ARRAY_SIZE(wm8580_snd_controls));
 802         wm8580_add_widgets(codec);
 803
 804         return 0;
 805
 806 err_regulator_enable:
 807         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 808 err_regulator_get:
 809         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 810         return ret;
 811 }
 812
 813 /* power down chip */
 814 static int wm8580_remove(struct snd_soc_codec *codec)
 815 {
 816         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 817
 818         wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
 819
 820         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 821         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 822
 823         return 0;
 824 }
 825
 826 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
 827         .probe =        wm8580_probe,
 828         .remove =       wm8580_remove,
 829         .set_bias_level = wm8580_set_bias_level,
 830         .reg_cache_size = sizeof(wm8580_reg),
 831         .reg_word_size = sizeof(u16),
 832         .reg_cache_default = &wm8580_reg,
 833 };
 834
 835 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 836 static int wm8580_i2c_probe(struct i2c_client *i2c,
 837                             const struct i2c_device_id *id)
 838 {
 839         struct wm8580_priv *wm8580;
 840         int ret;
 841
 842         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 843         if (wm8580 == NULL)
 844                 return -ENOMEM;
 845
 846         i2c_set_clientdata(i2c, wm8580);
 847         wm8580->control_type = SND_SOC_I2C;
 848
 849         ret =  snd_soc_register_codec(&i2c->dev,
 850                         &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
 851         if (ret < 0)
 852                 kfree(wm8580);
 853         return ret;
 854 }
 855
 856 static int wm8580_i2c_remove(struct i2c_client *client)
 857 {
 858         snd_soc_unregister_codec(&client->dev);
 859         kfree(i2c_get_clientdata(client));
 860         return 0;
 861 }
 862
 863 static const struct i2c_device_id wm8580_i2c_id[] = {
 864         { "wm8580", 0 },
 865         { }
 866 };
 867 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 868
 869 static struct i2c_driver wm8580_i2c_driver = {
 870         .driver = {
 871                 .name = "wm8580-codec",
 872                 .owner = THIS_MODULE,
 873         },
 874         .probe =    wm8580_i2c_probe,
 875         .remove =   wm8580_i2c_remove,
 876         .id_table = wm8580_i2c_id,
 877 };
 878 #endif
 879
 880 static int __init wm8580_modinit(void)
 881 {
 882         int ret = 0;
 883
 884 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 885         ret = i2c_add_driver(&wm8580_i2c_driver);
 886         if (ret != 0) {
 887                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 888         }
 889 #endif
 890
 891         return ret;
 892 }
 893 module_init(wm8580_modinit);
 894
 895 static void __exit wm8580_exit(void)
 896 {
 897 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 898         i2c_del_driver(&wm8580_i2c_driver);
 899 #endif
 900 }
 901 module_exit(wm8580_exit);
 902
 903 MODULE_DESCRIPTION("ASoC WM8580 driver");
 904 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 905 MODULE_LICENSE("GPL");