sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/slab.h>
  29
  30 #include <sound/core.h>
  31 #include <sound/pcm.h>
  32 #include <sound/pcm_params.h>
  33 #include <sound/soc.h>
  34 #include <sound/soc-dapm.h>
  35 #include <sound/tlv.h>
  36 #include <sound/initval.h>
  37 #include <asm/div64.h>
  38
  39 #include "wm8580.h"
  40
  41 /* WM8580 register space */
  42 #define WM8580_PLLA1                         0x00
  43 #define WM8580_PLLA2                         0x01
  44 #define WM8580_PLLA3                         0x02
  45 #define WM8580_PLLA4                         0x03
  46 #define WM8580_PLLB1                         0x04
  47 #define WM8580_PLLB2                         0x05
  48 #define WM8580_PLLB3                         0x06
  49 #define WM8580_PLLB4                         0x07
  50 #define WM8580_CLKSEL                        0x08
  51 #define WM8580_PAIF1                         0x09
  52 #define WM8580_PAIF2                         0x0A
  53 #define WM8580_SAIF1                         0x0B
  54 #define WM8580_PAIF3                         0x0C
  55 #define WM8580_PAIF4                         0x0D
  56 #define WM8580_SAIF2                         0x0E
  57 #define WM8580_DAC_CONTROL1                  0x0F
  58 #define WM8580_DAC_CONTROL2                  0x10
  59 #define WM8580_DAC_CONTROL3                  0x11
  60 #define WM8580_DAC_CONTROL4                  0x12
  61 #define WM8580_DAC_CONTROL5                  0x13
  62 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  63 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  64 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  65 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  66 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  67 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  68 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  69 #define WM8580_ADC_CONTROL1                  0x1D
  70 #define WM8580_SPDTXCHAN0                    0x1E
  71 #define WM8580_SPDTXCHAN1                    0x1F
  72 #define WM8580_SPDTXCHAN2                    0x20
  73 #define WM8580_SPDTXCHAN3                    0x21
  74 #define WM8580_SPDTXCHAN4                    0x22
  75 #define WM8580_SPDTXCHAN5                    0x23
  76 #define WM8580_SPDMODE                       0x24
  77 #define WM8580_INTMASK                       0x25
  78 #define WM8580_GPO1                          0x26
  79 #define WM8580_GPO2                          0x27
  80 #define WM8580_GPO3                          0x28
  81 #define WM8580_GPO4                          0x29
  82 #define WM8580_GPO5                          0x2A
  83 #define WM8580_INTSTAT                       0x2B
  84 #define WM8580_SPDRXCHAN1                    0x2C
  85 #define WM8580_SPDRXCHAN2                    0x2D
  86 #define WM8580_SPDRXCHAN3                    0x2E
  87 #define WM8580_SPDRXCHAN4                    0x2F
  88 #define WM8580_SPDRXCHAN5                    0x30
  89 #define WM8580_SPDSTAT                       0x31
  90 #define WM8580_PWRDN1                        0x32
  91 #define WM8580_PWRDN2                        0x33
  92 #define WM8580_READBACK                      0x34
  93 #define WM8580_RESET                         0x35
  94
  95 #define WM8580_MAX_REGISTER                  0x35
  96
  97 /* PLLB4 (register 7h) */
  98 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
  99 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 100 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 101 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 102
 103 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 104 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 105 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 106 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 107
 108 /* CLKSEL (register 8h) */
 109 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 110 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 111 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 112
 113 /* AIF control 1 (registers 9h-bh) */
 114 #define WM8580_AIF_RATE_MASK       0x7
 115 #define WM8580_AIF_BCLKSEL_MASK   0x18
 116
 117 #define WM8580_AIF_MS             0x20
 118
 119 #define WM8580_AIF_CLKSRC_MASK    0xc0
 120 #define WM8580_AIF_CLKSRC_PLLA    0x40
 121 #define WM8580_AIF_CLKSRC_PLLB    0x40
 122 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 123
 124 /* AIF control 2 (registers ch-eh) */
 125 #define WM8580_AIF_FMT_MASK    0x03
 126 #define WM8580_AIF_FMT_RIGHTJ  0x00
 127 #define WM8580_AIF_FMT_LEFTJ   0x01
 128 #define WM8580_AIF_FMT_I2S     0x02
 129 #define WM8580_AIF_FMT_DSP     0x03
 130
 131 #define WM8580_AIF_LENGTH_MASK   0x0c
 132 #define WM8580_AIF_LENGTH_16     0x00
 133 #define WM8580_AIF_LENGTH_20     0x04
 134 #define WM8580_AIF_LENGTH_24     0x08
 135 #define WM8580_AIF_LENGTH_32     0x0c
 136
 137 #define WM8580_AIF_LRP         0x10
 138 #define WM8580_AIF_BCP         0x20
 139
 140 /* Powerdown Register 1 (register 32h) */
 141 #define WM8580_PWRDN1_PWDN     0x001
 142 #define WM8580_PWRDN1_ALLDACPD 0x040
 143
 144 /* Powerdown Register 2 (register 33h) */
 145 #define WM8580_PWRDN2_OSSCPD   0x001
 146 #define WM8580_PWRDN2_PLLAPD   0x002
 147 #define WM8580_PWRDN2_PLLBPD   0x004
 148 #define WM8580_PWRDN2_SPDIFPD  0x008
 149 #define WM8580_PWRDN2_SPDIFTXD 0x010
 150 #define WM8580_PWRDN2_SPDIFRXD 0x020
 151
 152 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 153
 154 /*
 155  * wm8580 register cache
 156  * We can't read the WM8580 register space when we
 157  * are using 2 wire for device control, so we cache them instead.
 158  */
 159 static const u16 wm8580_reg[] = {
 160         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 161         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 162         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 163         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 164         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 165         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 166         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 167         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 168         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 169         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 170         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 171         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 172         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 173         0x0000, 0x0000 /*R53*/
 174 };
 175
 176 struct pll_state {
 177         unsigned int in;
 178         unsigned int out;
 179 };
 180
 181 #define WM8580_NUM_SUPPLIES 3
 182 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 183         "AVDD",
 184         "DVDD",
 185         "PVDD",
 186 };
 187
 188 /* codec private data */
 189 struct wm8580_priv {
 190         enum snd_soc_control_type control_type;
 191         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 192         u16 reg_cache[WM8580_MAX_REGISTER + 1];
 193         struct pll_state a;
 194         struct pll_state b;
 195         int sysclk[2];
 196 };
 197
 198 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 199
 200 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 201                          struct snd_ctl_elem_value *ucontrol)
 202 {
 203         struct soc_mixer_control *mc =
 204                 (struct soc_mixer_control *)kcontrol->private_value;
 205         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 206         u16 *reg_cache = codec->reg_cache;
 207         unsigned int reg = mc->reg;
 208         unsigned int reg2 = mc->rreg;
 209         int ret;
 210
 211         /* Clear the register cache so we write without VU set */
 212         reg_cache[reg] = 0;
 213         reg_cache[reg2] = 0;
 214
 215         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 216         if (ret < 0)
 217                 return ret;
 218
 219         /* Now write again with the volume update bit set */
 220         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 221         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 222
 223         return 0;
 224 }
 225
 226 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 227                                     xinvert, tlv_array)                 \
 228 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 229         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 230                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 231         .tlv.p = (tlv_array), \
 232         .info = snd_soc_info_volsw_2r, \
 233         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 234         .private_value = (unsigned long)&(struct soc_mixer_control) \
 235                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 236                 .max = xmax, .invert = xinvert} }
 237
 238 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 239 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 240                             WM8580_DIGITAL_ATTENUATION_DACL1,
 241                             WM8580_DIGITAL_ATTENUATION_DACR1,
 242                             0, 0xff, 0, dac_tlv),
 243 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 244                             WM8580_DIGITAL_ATTENUATION_DACL2,
 245                             WM8580_DIGITAL_ATTENUATION_DACR2,
 246                             0, 0xff, 0, dac_tlv),
 247 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 248                             WM8580_DIGITAL_ATTENUATION_DACL3,
 249                             WM8580_DIGITAL_ATTENUATION_DACR3,
 250                             0, 0xff, 0, dac_tlv),
 251
 252 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 253 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 254 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 255
 256 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 257 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 258 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 259
 260 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 261 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
 262 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
 263 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
 264
 265 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
 266 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 267 };
 268
 269 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 270 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 271 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 272 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 273
 274 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 275 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 276 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 277 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 278 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 279 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 280
 281 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 282
 283 SND_SOC_DAPM_INPUT("AINL"),
 284 SND_SOC_DAPM_INPUT("AINR"),
 285 };
 286
 287 static const struct snd_soc_dapm_route audio_map[] = {
 288         { "VOUT1L", NULL, "DAC1" },
 289         { "VOUT1R", NULL, "DAC1" },
 290
 291         { "VOUT2L", NULL, "DAC2" },
 292         { "VOUT2R", NULL, "DAC2" },
 293
 294         { "VOUT3L", NULL, "DAC3" },
 295         { "VOUT3R", NULL, "DAC3" },
 296
 297         { "ADC", NULL, "AINL" },
 298         { "ADC", NULL, "AINR" },
 299 };
 300
 301 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 302 {
 303         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 304                                   ARRAY_SIZE(wm8580_dapm_widgets));
 305
 306         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 307
 308         return 0;
 309 }
 310
 311 /* PLL divisors */
 312 struct _pll_div {
 313         u32 prescale:1;
 314         u32 postscale:1;
 315         u32 freqmode:2;
 316         u32 n:4;
 317         u32 k:24;
 318 };
 319
 320 /* The size in bits of the pll divide */
 321 #define FIXED_PLL_SIZE (1 << 22)
 322
 323 /* PLL rate to output rate divisions */
 324 static struct {
 325         unsigned int div;
 326         unsigned int freqmode;
 327         unsigned int postscale;
 328 } post_table[] = {
 329         {  2,  0, 0 },
 330         {  4,  0, 1 },
 331         {  4,  1, 0 },
 332         {  8,  1, 1 },
 333         {  8,  2, 0 },
 334         { 16,  2, 1 },
 335         { 12,  3, 0 },
 336         { 24,  3, 1 }
 337 };
 338
 339 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 340                        unsigned int source)
 341 {
 342         u64 Kpart;
 343         unsigned int K, Ndiv, Nmod;
 344         int i;
 345
 346         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 347
 348         /* Scale the output frequency up; the PLL should run in the
 349          * region of 90-100MHz.
 350          */
 351         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 352                 if (target * post_table[i].div >=  90000000 &&
 353                     target * post_table[i].div <= 100000000) {
 354                         pll_div->freqmode = post_table[i].freqmode;
 355                         pll_div->postscale = post_table[i].postscale;
 356                         target *= post_table[i].div;
 357                         break;
 358                 }
 359         }
 360
 361         if (i == ARRAY_SIZE(post_table)) {
 362                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 363                        "%u\n", target);
 364                 return -EINVAL;
 365         }
 366
 367         Ndiv = target / source;
 368
 369         if (Ndiv < 5) {
 370                 source /= 2;
 371                 pll_div->prescale = 1;
 372                 Ndiv = target / source;
 373         } else
 374                 pll_div->prescale = 0;
 375
 376         if ((Ndiv < 5) || (Ndiv > 13)) {
 377                 printk(KERN_ERR
 378                         "WM8580 N=%u outside supported range\n", Ndiv);
 379                 return -EINVAL;
 380         }
 381
 382         pll_div->n = Ndiv;
 383         Nmod = target % source;
 384         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 385
 386         do_div(Kpart, source);
 387
 388         K = Kpart & 0xFFFFFFFF;
 389
 390         pll_div->k = K;
 391
 392         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 393                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 394                  pll_div->postscale);
 395
 396         return 0;
 397 }
 398
 399 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 400                 int source, unsigned int freq_in, unsigned int freq_out)
 401 {
 402         int offset;
 403         struct snd_soc_codec *codec = codec_dai->codec;
 404         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 405         struct pll_state *state;
 406         struct _pll_div pll_div;
 407         unsigned int reg;
 408         unsigned int pwr_mask;
 409         int ret;
 410
 411         /* GCC isn't able to work out the ifs below for initialising/using
 412          * pll_div so suppress warnings.
 413          */
 414         memset(&pll_div, 0, sizeof(pll_div));
 415
 416         switch (pll_id) {
 417         case WM8580_PLLA:
 418                 state = &wm8580->a;
 419                 offset = 0;
 420                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 421                 break;
 422         case WM8580_PLLB:
 423                 state = &wm8580->b;
 424                 offset = 4;
 425                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 426                 break;
 427         default:
 428                 return -ENODEV;
 429         }
 430
 431         if (freq_in && freq_out) {
 432                 ret = pll_factors(&pll_div, freq_out, freq_in);
 433                 if (ret != 0)
 434                         return ret;
 435         }
 436
 437         state->in = freq_in;
 438         state->out = freq_out;
 439
 440         /* Always disable the PLL - it is not safe to leave it running
 441          * while reprogramming it.
 442          */
 443         reg = snd_soc_read(codec, WM8580_PWRDN2);
 444         snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 445
 446         if (!freq_in || !freq_out)
 447                 return 0;
 448
 449         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 450         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 451         snd_soc_write(codec, WM8580_PLLA3 + offset,
 452                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 453
 454         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 455         reg &= ~0x1b;
 456         reg |= pll_div.prescale | pll_div.postscale << 1 |
 457                 pll_div.freqmode << 3;
 458
 459         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 460
 461         /* All done, turn it on */
 462         reg = snd_soc_read(codec, WM8580_PWRDN2);
 463         snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 464
 465         return 0;
 466 }
 467
 468 static const int wm8580_sysclk_ratios[] = {
 469         128, 192, 256, 384, 512, 768, 1152,
 470 };
 471
 472 /*
 473  * Set PCM DAI bit size and sample rate.
 474  */
 475 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 476                                  struct snd_pcm_hw_params *params,
 477                                  struct snd_soc_dai *dai)
 478 {
 479         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 480         struct snd_soc_codec *codec = rtd->codec;
 481         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 482         u16 paifa = 0;
 483         u16 paifb = 0;
 484         int i, ratio;
 485
 486         /* bit size */
 487         switch (params_format(params)) {
 488         case SNDRV_PCM_FORMAT_S16_LE:
 489                 paifa |= 0x8;
 490                 break;
 491         case SNDRV_PCM_FORMAT_S20_3LE:
 492                 paifa |= 0x10;
 493                 paifb |= WM8580_AIF_LENGTH_20;
 494                 break;
 495         case SNDRV_PCM_FORMAT_S24_LE:
 496                 paifa |= 0x10;
 497                 paifb |= WM8580_AIF_LENGTH_24;
 498                 break;
 499         case SNDRV_PCM_FORMAT_S32_LE:
 500                 paifa |= 0x10;
 501                 paifb |= WM8580_AIF_LENGTH_24;
 502                 break;
 503         default:
 504                 return -EINVAL;
 505         }
 506
 507         /* Look up the SYSCLK ratio; accept only exact matches */
 508         ratio = wm8580->sysclk[dai->id] / params_rate(params);
 509         for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
 510                 if (ratio == wm8580_sysclk_ratios[i])
 511                         break;
 512         if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
 513                 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
 514                         wm8580->sysclk[dai->id], params_rate(params));
 515                 return -EINVAL;
 516         }
 517         paifa |= i;
 518         dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
 519                 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
 520
 521         snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
 522                             WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
 523                             paifa);
 524         snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
 525                             WM8580_AIF_LENGTH_MASK, paifb);
 526         return 0;
 527 }
 528
 529 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 530                                       unsigned int fmt)
 531 {
 532         struct snd_soc_codec *codec = codec_dai->codec;
 533         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 534         unsigned int aifa;
 535         unsigned int aifb;
 536         int can_invert_lrclk;
 537         int sysclk;
 538
 539         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
 540         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 541
 542         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 543
 544         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 545         case SND_SOC_DAIFMT_CBS_CFS:
 546                 aifa &= ~WM8580_AIF_MS;
 547                 break;
 548         case SND_SOC_DAIFMT_CBM_CFM:
 549                 aifa |= WM8580_AIF_MS;
 550                 break;
 551         default:
 552                 return -EINVAL;
 553         }
 554
 555         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 556         case SND_SOC_DAIFMT_I2S:
 557                 can_invert_lrclk = 1;
 558                 aifb |= WM8580_AIF_FMT_I2S;
 559                 break;
 560         case SND_SOC_DAIFMT_RIGHT_J:
 561                 can_invert_lrclk = 1;
 562                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 563                 break;
 564         case SND_SOC_DAIFMT_LEFT_J:
 565                 can_invert_lrclk = 1;
 566                 aifb |= WM8580_AIF_FMT_LEFTJ;
 567                 break;
 568         case SND_SOC_DAIFMT_DSP_A:
 569                 can_invert_lrclk = 0;
 570                 aifb |= WM8580_AIF_FMT_DSP;
 571                 break;
 572         case SND_SOC_DAIFMT_DSP_B:
 573                 can_invert_lrclk = 0;
 574                 aifb |= WM8580_AIF_FMT_DSP;
 575                 aifb |= WM8580_AIF_LRP;
 576                 break;
 577         default:
 578                 return -EINVAL;
 579         }
 580
 581         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 582         case SND_SOC_DAIFMT_NB_NF:
 583                 break;
 584
 585         case SND_SOC_DAIFMT_IB_IF:
 586                 if (!can_invert_lrclk)
 587                         return -EINVAL;
 588                 aifb |= WM8580_AIF_BCP;
 589                 aifb |= WM8580_AIF_LRP;
 590                 break;
 591
 592         case SND_SOC_DAIFMT_IB_NF:
 593                 aifb |= WM8580_AIF_BCP;
 594                 break;
 595
 596         case SND_SOC_DAIFMT_NB_IF:
 597                 if (!can_invert_lrclk)
 598                         return -EINVAL;
 599                 aifb |= WM8580_AIF_LRP;
 600                 break;
 601
 602         default:
 603                 return -EINVAL;
 604         }
 605
 606         sysclk = wm8580->sysclk[codec_dai->driver->id];
 607
 608         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
 609         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 610
 611         return 0;
 612 }
 613
 614 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 615                                  int div_id, int div)
 616 {
 617         struct snd_soc_codec *codec = codec_dai->codec;
 618         unsigned int reg;
 619
 620         switch (div_id) {
 621         case WM8580_MCLK:
 622                 reg = snd_soc_read(codec, WM8580_PLLB4);
 623                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 624
 625                 switch (div) {
 626                 case WM8580_CLKSRC_MCLK:
 627                         /* Input */
 628                         break;
 629
 630                 case WM8580_CLKSRC_PLLA:
 631                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 632                         break;
 633                 case WM8580_CLKSRC_PLLB:
 634                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 635                         break;
 636
 637                 case WM8580_CLKSRC_OSC:
 638                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 639                         break;
 640
 641                 default:
 642                         return -EINVAL;
 643                 }
 644                 snd_soc_write(codec, WM8580_PLLB4, reg);
 645                 break;
 646
 647         case WM8580_CLKOUTSRC:
 648                 reg = snd_soc_read(codec, WM8580_PLLB4);
 649                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 650
 651                 switch (div) {
 652                 case WM8580_CLKSRC_NONE:
 653                         break;
 654
 655                 case WM8580_CLKSRC_PLLA:
 656                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 657                         break;
 658
 659                 case WM8580_CLKSRC_PLLB:
 660                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 661                         break;
 662
 663                 case WM8580_CLKSRC_OSC:
 664                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 665                         break;
 666
 667                 default:
 668                         return -EINVAL;
 669                 }
 670                 snd_soc_write(codec, WM8580_PLLB4, reg);
 671                 break;
 672
 673         default:
 674                 return -EINVAL;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 681                              unsigned int freq, int dir)
 682 {
 683         struct snd_soc_codec *codec = dai->codec;
 684         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 685         int sel, sel_mask, sel_shift;
 686
 687         switch (dai->driver->id) {
 688         case WM8580_DAI_PAIFTX:
 689                 sel_mask = 0x3;
 690                 sel_shift = 0;
 691                 break;
 692
 693         case WM8580_DAI_PAIFRX:
 694                 sel_mask = 0xc;
 695                 sel_shift = 2;
 696                 break;
 697
 698         default:
 699                 BUG_ON("Unknown DAI driver ID\n");
 700                 return -EINVAL;
 701         }
 702
 703         switch (clk_id) {
 704         case WM8580_CLKSRC_ADCMCLK:
 705                 if (dai->id != WM8580_DAI_PAIFTX)
 706                         return -EINVAL;
 707                 sel = 0 << sel_shift;
 708                 break;
 709         case WM8580_CLKSRC_PLLA:
 710                 sel = 1 << sel_shift;
 711                 break;
 712         case WM8580_CLKSRC_PLLB:
 713                 sel = 2 << sel_shift;
 714                 break;
 715         case WM8580_CLKSRC_MCLK:
 716                 sel = 3 << sel_shift;
 717                 break;
 718         default:
 719                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
 720                 return -EINVAL;
 721         }
 722
 723         /* We really should validate PLL settings but not yet */
 724         wm8580->sysclk[dai->id] = freq;
 725
 726         return snd_soc_update_bits(codec, WM8580_CLKSEL, sel, sel_mask);
 727 }
 728
 729 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 730 {
 731         struct snd_soc_codec *codec = codec_dai->codec;
 732         unsigned int reg;
 733
 734         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 735
 736         if (mute)
 737                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 738         else
 739                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 740
 741         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 742
 743         return 0;
 744 }
 745
 746 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 747         enum snd_soc_bias_level level)
 748 {
 749         u16 reg;
 750         switch (level) {
 751         case SND_SOC_BIAS_ON:
 752         case SND_SOC_BIAS_PREPARE:
 753                 break;
 754
 755         case SND_SOC_BIAS_STANDBY:
 756                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 757                         /* Power up and get individual control of the DACs */
 758                         reg = snd_soc_read(codec, WM8580_PWRDN1);
 759                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
 760                         snd_soc_write(codec, WM8580_PWRDN1, reg);
 761
 762                         /* Make VMID high impedence */
 763                         reg = snd_soc_read(codec,  WM8580_ADC_CONTROL1);
 764                         reg &= ~0x100;
 765                         snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
 766                 }
 767                 break;
 768
 769         case SND_SOC_BIAS_OFF:
 770                 reg = snd_soc_read(codec, WM8580_PWRDN1);
 771                 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 772                 break;
 773         }
 774         codec->bias_level = level;
 775         return 0;
 776 }
 777
 778 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 779                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 780
 781 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 782         .set_sysclk     = wm8580_set_sysclk,
 783         .hw_params      = wm8580_paif_hw_params,
 784         .set_fmt        = wm8580_set_paif_dai_fmt,
 785         .set_clkdiv     = wm8580_set_dai_clkdiv,
 786         .set_pll        = wm8580_set_dai_pll,
 787         .digital_mute   = wm8580_digital_mute,
 788 };
 789
 790 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 791         .set_sysclk     = wm8580_set_sysclk,
 792         .hw_params      = wm8580_paif_hw_params,
 793         .set_fmt        = wm8580_set_paif_dai_fmt,
 794         .set_clkdiv     = wm8580_set_dai_clkdiv,
 795         .set_pll        = wm8580_set_dai_pll,
 796 };
 797
 798 static struct snd_soc_dai_driver wm8580_dai[] = {
 799         {
 800                 .name = "wm8580-hifi-playback",
 801                 .id     = WM8580_DAI_PAIFRX,
 802                 .playback = {
 803                         .stream_name = "Playback",
 804                         .channels_min = 1,
 805                         .channels_max = 6,
 806                         .rates = SNDRV_PCM_RATE_8000_192000,
 807                         .formats = WM8580_FORMATS,
 808                 },
 809                 .ops = &wm8580_dai_ops_playback,
 810         },
 811         {
 812                 .name = "wm8580-hifi-capture",
 813                 .id     =       WM8580_DAI_PAIFTX,
 814                 .capture = {
 815                         .stream_name = "Capture",
 816                         .channels_min = 2,
 817                         .channels_max = 2,
 818                         .rates = SNDRV_PCM_RATE_8000_192000,
 819                         .formats = WM8580_FORMATS,
 820                 },
 821                 .ops = &wm8580_dai_ops_capture,
 822         },
 823 };
 824
 825 static int wm8580_probe(struct snd_soc_codec *codec)
 826 {
 827         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 828         int ret = 0,i;
 829
 830         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
 831         if (ret < 0) {
 832                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 833                 return ret;
 834         }
 835
 836         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 837                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 838
 839         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 840                                  wm8580->supplies);
 841         if (ret != 0) {
 842                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 843                 return ret;
 844         }
 845
 846         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 847                                     wm8580->supplies);
 848         if (ret != 0) {
 849                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 850                 goto err_regulator_get;
 851         }
 852
 853         /* Get the codec into a known state */
 854         ret = snd_soc_write(codec, WM8580_RESET, 0);
 855         if (ret != 0) {
 856                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 857                 goto err_regulator_enable;
 858         }
 859
 860         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 861
 862         snd_soc_add_controls(codec, wm8580_snd_controls,
 863                              ARRAY_SIZE(wm8580_snd_controls));
 864         wm8580_add_widgets(codec);
 865
 866         return 0;
 867
 868 err_regulator_enable:
 869         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 870 err_regulator_get:
 871         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 872         return ret;
 873 }
 874
 875 /* power down chip */
 876 static int wm8580_remove(struct snd_soc_codec *codec)
 877 {
 878         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 879
 880         wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
 881
 882         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 883         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 884
 885         return 0;
 886 }
 887
 888 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
 889         .probe =        wm8580_probe,
 890         .remove =       wm8580_remove,
 891         .set_bias_level = wm8580_set_bias_level,
 892         .reg_cache_size = sizeof(wm8580_reg),
 893         .reg_word_size = sizeof(u16),
 894         .reg_cache_default = &wm8580_reg,
 895 };
 896
 897 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 898 static int wm8580_i2c_probe(struct i2c_client *i2c,
 899                             const struct i2c_device_id *id)
 900 {
 901         struct wm8580_priv *wm8580;
 902         int ret;
 903
 904         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 905         if (wm8580 == NULL)
 906                 return -ENOMEM;
 907
 908         i2c_set_clientdata(i2c, wm8580);
 909         wm8580->control_type = SND_SOC_I2C;
 910
 911         ret =  snd_soc_register_codec(&i2c->dev,
 912                         &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
 913         if (ret < 0)
 914                 kfree(wm8580);
 915         return ret;
 916 }
 917
 918 static int wm8580_i2c_remove(struct i2c_client *client)
 919 {
 920         snd_soc_unregister_codec(&client->dev);
 921         kfree(i2c_get_clientdata(client));
 922         return 0;
 923 }
 924
 925 static const struct i2c_device_id wm8580_i2c_id[] = {
 926         { "wm8580", 0 },
 927         { }
 928 };
 929 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 930
 931 static struct i2c_driver wm8580_i2c_driver = {
 932         .driver = {
 933                 .name = "wm8580-codec",
 934                 .owner = THIS_MODULE,
 935         },
 936         .probe =    wm8580_i2c_probe,
 937         .remove =   wm8580_i2c_remove,
 938         .id_table = wm8580_i2c_id,
 939 };
 940 #endif
 941
 942 static int __init wm8580_modinit(void)
 943 {
 944         int ret = 0;
 945
 946 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 947         ret = i2c_add_driver(&wm8580_i2c_driver);
 948         if (ret != 0) {
 949                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 950         }
 951 #endif
 952
 953         return ret;
 954 }
 955 module_init(wm8580_modinit);
 956
 957 static void __exit wm8580_exit(void)
 958 {
 959 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 960         i2c_del_driver(&wm8580_i2c_driver);
 961 #endif
 962 }
 963 module_exit(wm8580_exit);
 964
 965 MODULE_DESCRIPTION("ASoC WM8580 driver");
 966 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 967 MODULE_LICENSE("GPL");