sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <sound/core.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/soc.h>
  38 #include <sound/soc-dapm.h>
  39 #include <sound/initval.h>
  40 #include <sound/tlv.h>
  41
  42 #include <sound/tlv320dac33-plat.h>
  43 #include "tlv320dac33.h"
  44
  45 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  46                                                  * 6144 stereo */
  47 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  48
  49 #define NSAMPLE_MAX             5700
  50
  51 #define LATENCY_TIME_MS         20
  52
  53 static struct snd_soc_codec *tlv320dac33_codec;
  54
  55 enum dac33_state {
  56         DAC33_IDLE = 0,
  57         DAC33_PREFILL,
  58         DAC33_PLAYBACK,
  59         DAC33_FLUSH,
  60 };
  61
  62 enum dac33_fifo_modes {
  63         DAC33_FIFO_BYPASS = 0,
  64         DAC33_FIFO_MODE1,
  65         DAC33_FIFO_MODE7,
  66         DAC33_FIFO_LAST_MODE,
  67 };
  68
  69 #define DAC33_NUM_SUPPLIES 3
  70 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  71         "AVDD",
  72         "DVDD",
  73         "IOVDD",
  74 };
  75
  76 struct tlv320dac33_priv {
  77         struct mutex mutex;
  78         struct workqueue_struct *dac33_wq;
  79         struct work_struct work;
  80         struct snd_soc_codec codec;
  81         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  82         int power_gpio;
  83         int chip_power;
  84         int irq;
  85         unsigned int refclk;
  86
  87         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
  88         unsigned int nsample_min;       /* nsample should not be lower than
  89                                          * this */
  90         unsigned int nsample_max;       /* nsample should not be higher than
  91                                          * this */
  92         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
  93         unsigned int nsample;           /* burst read amount from host */
  94         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
  95
  96         int keep_bclk;                  /* Keep the BCLK continuously running
  97                                          * in FIFO modes */
  98         enum dac33_state state;
  99 };
 100
 101 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 102 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 103 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 104 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 105 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 106 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 107 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 108 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 109 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 110 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 111 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 112 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 113 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 114 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 115 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 116 0x00, 0x00,             /* 0x38 - 0x39 */
 117 /* Registers 0x3a - 0x3f are reserved  */
 118             0x00, 0x00, /* 0x3a - 0x3b */
 119 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 120
 121 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 122 0x00, 0x80,             /* 0x44 - 0x45 */
 123 /* Registers 0x46 - 0x47 are reserved  */
 124             0x80, 0x80, /* 0x46 - 0x47 */
 125
 126 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 127 /* Registers 0x4b - 0x7c are reserved  */
 128                   0x00, /* 0x4b        */
 129 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 130 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 131 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 132 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 133 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 134 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 136 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 137 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 138 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 140 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 141 0x00,                   /* 0x7c        */
 142
 143       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 144 };
 145
 146 /* Register read and write */
 147 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 148                                                 unsigned reg)
 149 {
 150         u8 *cache = codec->reg_cache;
 151         if (reg >= DAC33_CACHEREGNUM)
 152                 return 0;
 153
 154         return cache[reg];
 155 }
 156
 157 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 158                                          u8 reg, u8 value)
 159 {
 160         u8 *cache = codec->reg_cache;
 161         if (reg >= DAC33_CACHEREGNUM)
 162                 return;
 163
 164         cache[reg] = value;
 165 }
 166
 167 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 168                       u8 *value)
 169 {
 170         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 171         int val;
 172
 173         *value = reg & 0xff;
 174
 175         /* If powered off, return the cached value */
 176         if (dac33->chip_power) {
 177                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 178                 if (val < 0) {
 179                         dev_err(codec->dev, "Read failed (%d)\n", val);
 180                         value[0] = dac33_read_reg_cache(codec, reg);
 181                 } else {
 182                         value[0] = val;
 183                         dac33_write_reg_cache(codec, reg, val);
 184                 }
 185         } else {
 186                 value[0] = dac33_read_reg_cache(codec, reg);
 187         }
 188
 189         return 0;
 190 }
 191
 192 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 193                        unsigned int value)
 194 {
 195         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 196         u8 data[2];
 197         int ret = 0;
 198
 199         /*
 200          * data is
 201          *   D15..D8 dac33 register offset
 202          *   D7...D0 register data
 203          */
 204         data[0] = reg & 0xff;
 205         data[1] = value & 0xff;
 206
 207         dac33_write_reg_cache(codec, data[0], data[1]);
 208         if (dac33->chip_power) {
 209                 ret = codec->hw_write(codec->control_data, data, 2);
 210                 if (ret != 2)
 211                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 212                 else
 213                         ret = 0;
 214         }
 215
 216         return ret;
 217 }
 218
 219 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 220                        unsigned int value)
 221 {
 222         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 223         int ret;
 224
 225         mutex_lock(&dac33->mutex);
 226         ret = dac33_write(codec, reg, value);
 227         mutex_unlock(&dac33->mutex);
 228
 229         return ret;
 230 }
 231
 232 #define DAC33_I2C_ADDR_AUTOINC  0x80
 233 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 234                        unsigned int value)
 235 {
 236         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 237         u8 data[3];
 238         int ret = 0;
 239
 240         /*
 241          * data is
 242          *   D23..D16 dac33 register offset
 243          *   D15..D8  register data MSB
 244          *   D7...D0  register data LSB
 245          */
 246         data[0] = reg & 0xff;
 247         data[1] = (value >> 8) & 0xff;
 248         data[2] = value & 0xff;
 249
 250         dac33_write_reg_cache(codec, data[0], data[1]);
 251         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 252
 253         if (dac33->chip_power) {
 254                 /* We need to set autoincrement mode for 16 bit writes */
 255                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 256                 ret = codec->hw_write(codec->control_data, data, 3);
 257                 if (ret != 3)
 258                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 259                 else
 260                         ret = 0;
 261         }
 262
 263         return ret;
 264 }
 265
 266 static void dac33_restore_regs(struct snd_soc_codec *codec)
 267 {
 268         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 269         u8 *cache = codec->reg_cache;
 270         u8 data[2];
 271         int i, ret;
 272
 273         if (!dac33->chip_power)
 274                 return;
 275
 276         for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
 277                 data[0] = i;
 278                 data[1] = cache[i];
 279                 /* Skip the read only registers */
 280                 if ((i >= DAC33_INT_OSC_STATUS &&
 281                                 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
 282                     (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
 283                     i == DAC33_DAC_STATUS_FLAGS ||
 284                     i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
 285                     i == DAC33_SRC_EST_REF_CLK_RATIO_B)
 286                         continue;
 287                 ret = codec->hw_write(codec->control_data, data, 2);
 288                 if (ret != 2)
 289                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 290         }
 291         for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
 292                 data[0] = i;
 293                 data[1] = cache[i];
 294                 ret = codec->hw_write(codec->control_data, data, 2);
 295                 if (ret != 2)
 296                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 297         }
 298         for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
 299                 data[0] = i;
 300                 data[1] = cache[i];
 301                 ret = codec->hw_write(codec->control_data, data, 2);
 302                 if (ret != 2)
 303                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 304         }
 305 }
 306
 307 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 308 {
 309         u8 reg;
 310
 311         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 312         if (power)
 313                 reg |= DAC33_PDNALLB;
 314         else
 315                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 316                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 317         dac33_write(codec, DAC33_PWR_CTRL, reg);
 318 }
 319
 320 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 321 {
 322         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 323         int ret;
 324
 325         mutex_lock(&dac33->mutex);
 326         if (power) {
 327                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 328                                           dac33->supplies);
 329                 if (ret != 0) {
 330                         dev_err(codec->dev,
 331                                 "Failed to enable supplies: %d\n", ret);
 332                                 goto exit;
 333                 }
 334
 335                 if (dac33->power_gpio >= 0)
 336                         gpio_set_value(dac33->power_gpio, 1);
 337
 338                 dac33->chip_power = 1;
 339
 340                 /* Restore registers */
 341                 dac33_restore_regs(codec);
 342
 343                 dac33_soft_power(codec, 1);
 344         } else {
 345                 dac33_soft_power(codec, 0);
 346                 if (dac33->power_gpio >= 0)
 347                         gpio_set_value(dac33->power_gpio, 0);
 348
 349                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 350                                              dac33->supplies);
 351                 if (ret != 0) {
 352                         dev_err(codec->dev,
 353                                 "Failed to disable supplies: %d\n", ret);
 354                         goto exit;
 355                 }
 356
 357                 dac33->chip_power = 0;
 358         }
 359
 360 exit:
 361         mutex_unlock(&dac33->mutex);
 362         return ret;
 363 }
 364
 365 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 366                          struct snd_ctl_elem_value *ucontrol)
 367 {
 368         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 369         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 370
 371         ucontrol->value.integer.value[0] = dac33->nsample;
 372
 373         return 0;
 374 }
 375
 376 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 377                          struct snd_ctl_elem_value *ucontrol)
 378 {
 379         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 380         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 381         int ret = 0;
 382
 383         if (dac33->nsample == ucontrol->value.integer.value[0])
 384                 return 0;
 385
 386         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 387             ucontrol->value.integer.value[0] > dac33->nsample_max)
 388                 ret = -EINVAL;
 389         else
 390                 dac33->nsample = ucontrol->value.integer.value[0];
 391
 392         return ret;
 393 }
 394
 395 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 396                          struct snd_ctl_elem_value *ucontrol)
 397 {
 398         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 399         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 400
 401         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 402
 403         return 0;
 404 }
 405
 406 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 407                          struct snd_ctl_elem_value *ucontrol)
 408 {
 409         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 410         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 411         int ret = 0;
 412
 413         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 414                 return 0;
 415         /* Do not allow changes while stream is running*/
 416         if (codec->active)
 417                 return -EPERM;
 418
 419         if (ucontrol->value.integer.value[0] < 0 ||
 420             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 421                 ret = -EINVAL;
 422         else
 423                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 424
 425         return ret;
 426 }
 427
 428 /* Codec operation modes */
 429 static const char *dac33_fifo_mode_texts[] = {
 430         "Bypass", "Mode 1", "Mode 7"
 431 };
 432
 433 static const struct soc_enum dac33_fifo_mode_enum =
 434         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 435                             dac33_fifo_mode_texts);
 436
 437 /*
 438  * DACL/R digital volume control:
 439  * from 0 dB to -63.5 in 0.5 dB steps
 440  * Need to be inverted later on:
 441  * 0x00 == 0 dB
 442  * 0x7f == -63.5 dB
 443  */
 444 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 445
 446 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 447         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 448                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 449                 0, 0x7f, 1, dac_digivol_tlv),
 450         SOC_DOUBLE_R("DAC Digital Playback Switch",
 451                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 452         SOC_DOUBLE_R("Line to Line Out Volume",
 453                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 454 };
 455
 456 static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
 457         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 458                  dac33_get_nsample, dac33_set_nsample),
 459         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 460                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 461 };
 462
 463 /* Analog bypass */
 464 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 465         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 466
 467 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 468         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 469
 470 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 471         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 472         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 473
 474         SND_SOC_DAPM_INPUT("LINEL"),
 475         SND_SOC_DAPM_INPUT("LINER"),
 476
 477         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
 478         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
 479
 480         /* Analog bypass */
 481         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 482                                 &dac33_dapm_abypassl_control),
 483         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 484                                 &dac33_dapm_abypassr_control),
 485
 486         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
 487                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 488         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
 489                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 490 };
 491
 492 static const struct snd_soc_dapm_route audio_map[] = {
 493         /* Analog bypass */
 494         {"Analog Left Bypass", "Switch", "LINEL"},
 495         {"Analog Right Bypass", "Switch", "LINER"},
 496
 497         {"Output Left Amp Power", NULL, "DACL"},
 498         {"Output Right Amp Power", NULL, "DACR"},
 499
 500         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
 501         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
 502
 503         /* output */
 504         {"LEFT_LO", NULL, "Output Left Amp Power"},
 505         {"RIGHT_LO", NULL, "Output Right Amp Power"},
 506 };
 507
 508 static int dac33_add_widgets(struct snd_soc_codec *codec)
 509 {
 510         snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
 511                                   ARRAY_SIZE(dac33_dapm_widgets));
 512
 513         /* set up audio path interconnects */
 514         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 515
 516         return 0;
 517 }
 518
 519 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 520                                 enum snd_soc_bias_level level)
 521 {
 522         int ret;
 523
 524         switch (level) {
 525         case SND_SOC_BIAS_ON:
 526                 dac33_soft_power(codec, 1);
 527                 break;
 528         case SND_SOC_BIAS_PREPARE:
 529                 break;
 530         case SND_SOC_BIAS_STANDBY:
 531                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 532                         ret = dac33_hard_power(codec, 1);
 533                         if (ret != 0)
 534                                 return ret;
 535                 }
 536
 537                 dac33_soft_power(codec, 0);
 538                 break;
 539         case SND_SOC_BIAS_OFF:
 540                 ret = dac33_hard_power(codec, 0);
 541                 if (ret != 0)
 542                         return ret;
 543
 544                 break;
 545         }
 546         codec->bias_level = level;
 547
 548         return 0;
 549 }
 550
 551 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 552 {
 553         struct snd_soc_codec *codec;
 554
 555         codec = &dac33->codec;
 556
 557         switch (dac33->fifo_mode) {
 558         case DAC33_FIFO_MODE1:
 559                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 560                                 DAC33_THRREG(dac33->nsample));
 561                 dac33_write16(codec, DAC33_PREFILL_MSB,
 562                                 DAC33_THRREG(dac33->alarm_threshold));
 563                 break;
 564         case DAC33_FIFO_MODE7:
 565                 dac33_write16(codec, DAC33_PREFILL_MSB,
 566                                 DAC33_THRREG(10));
 567                 break;
 568         default:
 569                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 570                                                         dac33->fifo_mode);
 571                 break;
 572         }
 573 }
 574
 575 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 576 {
 577         struct snd_soc_codec *codec;
 578
 579         codec = &dac33->codec;
 580
 581         switch (dac33->fifo_mode) {
 582         case DAC33_FIFO_MODE1:
 583                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 584                                 DAC33_THRREG(dac33->nsample));
 585                 break;
 586         case DAC33_FIFO_MODE7:
 587                 /* At the moment we are not using interrupts in mode7 */
 588                 break;
 589         default:
 590                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 591                                                         dac33->fifo_mode);
 592                 break;
 593         }
 594 }
 595
 596 static void dac33_work(struct work_struct *work)
 597 {
 598         struct snd_soc_codec *codec;
 599         struct tlv320dac33_priv *dac33;
 600         u8 reg;
 601
 602         dac33 = container_of(work, struct tlv320dac33_priv, work);
 603         codec = &dac33->codec;
 604
 605         mutex_lock(&dac33->mutex);
 606         switch (dac33->state) {
 607         case DAC33_PREFILL:
 608                 dac33->state = DAC33_PLAYBACK;
 609                 dac33_prefill_handler(dac33);
 610                 break;
 611         case DAC33_PLAYBACK:
 612                 dac33_playback_handler(dac33);
 613                 break;
 614         case DAC33_IDLE:
 615                 break;
 616         case DAC33_FLUSH:
 617                 dac33->state = DAC33_IDLE;
 618                 /* Mask all interrupts from dac33 */
 619                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 620
 621                 /* flush fifo */
 622                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 623                 reg |= DAC33_FIFOFLUSH;
 624                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 625                 break;
 626         }
 627         mutex_unlock(&dac33->mutex);
 628 }
 629
 630 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 631 {
 632         struct snd_soc_codec *codec = dev;
 633         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 634
 635         queue_work(dac33->dac33_wq, &dac33->work);
 636
 637         return IRQ_HANDLED;
 638 }
 639
 640 static void dac33_oscwait(struct snd_soc_codec *codec)
 641 {
 642         int timeout = 20;
 643         u8 reg;
 644
 645         do {
 646                 msleep(1);
 647                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 648         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 649         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 650                 dev_err(codec->dev,
 651                         "internal oscillator calibration failed\n");
 652 }
 653
 654 static int dac33_hw_params(struct snd_pcm_substream *substream,
 655                            struct snd_pcm_hw_params *params,
 656                            struct snd_soc_dai *dai)
 657 {
 658         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 659         struct snd_soc_device *socdev = rtd->socdev;
 660         struct snd_soc_codec *codec = socdev->card->codec;
 661
 662         /* Check parameters for validity */
 663         switch (params_rate(params)) {
 664         case 44100:
 665         case 48000:
 666                 break;
 667         default:
 668                 dev_err(codec->dev, "unsupported rate %d\n",
 669                         params_rate(params));
 670                 return -EINVAL;
 671         }
 672
 673         switch (params_format(params)) {
 674         case SNDRV_PCM_FORMAT_S16_LE:
 675                 break;
 676         default:
 677                 dev_err(codec->dev, "unsupported format %d\n",
 678                         params_format(params));
 679                 return -EINVAL;
 680         }
 681
 682         return 0;
 683 }
 684
 685 #define CALC_OSCSET(rate, refclk) ( \
 686         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 687 #define CALC_RATIOSET(rate, refclk) ( \
 688         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 689
 690 /*
 691  * tlv320dac33 is strict on the sequence of the register writes, if the register
 692  * writes happens in different order, than dac33 might end up in unknown state.
 693  * Use the known, working sequence of register writes to initialize the dac33.
 694  */
 695 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 696 {
 697         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 698         struct snd_soc_device *socdev = rtd->socdev;
 699         struct snd_soc_codec *codec = socdev->card->codec;
 700         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 701         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 702         u8 aictrl_a, aictrl_b, fifoctrl_a;
 703
 704         switch (substream->runtime->rate) {
 705         case 44100:
 706         case 48000:
 707                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 708                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 709                                          dac33->refclk);
 710                 break;
 711         default:
 712                 dev_err(codec->dev, "unsupported rate %d\n",
 713                         substream->runtime->rate);
 714                 return -EINVAL;
 715         }
 716
 717
 718         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 719         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 720         /* Read FIFO control A, and clear FIFO flush bit */
 721         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 722         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 723
 724         fifoctrl_a &= ~DAC33_WIDTH;
 725         switch (substream->runtime->format) {
 726         case SNDRV_PCM_FORMAT_S16_LE:
 727                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 728                 fifoctrl_a |= DAC33_WIDTH;
 729                 break;
 730         default:
 731                 dev_err(codec->dev, "unsupported format %d\n",
 732                         substream->runtime->format);
 733                 return -EINVAL;
 734         }
 735
 736         mutex_lock(&dac33->mutex);
 737         dac33_soft_power(codec, 0);
 738         dac33_soft_power(codec, 1);
 739
 740         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 741         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 742
 743         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 744         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 745
 746         /* calib time: 128 is a nice number ;) */
 747         dac33_write(codec, DAC33_CALIB_TIME, 128);
 748
 749         /* adjustment treshold & step */
 750         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 751                                                  DAC33_ADJSTEP(1));
 752
 753         /* div=4 / gain=1 / div */
 754         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 755
 756         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 757         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 758         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 759
 760         dac33_oscwait(codec);
 761
 762         if (dac33->fifo_mode) {
 763                 /* Generic for all FIFO modes */
 764                 /* 50-51 : ASRC Control registers */
 765                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 766                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 767
 768                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 769                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 770
 771                 /* Set interrupts to high active */
 772                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 773         } else {
 774                 /* FIFO bypass mode */
 775                 /* 50-51 : ASRC Control registers */
 776                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 777                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 778         }
 779
 780         /* Interrupt behaviour configuration */
 781         switch (dac33->fifo_mode) {
 782         case DAC33_FIFO_MODE1:
 783                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 784                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 785                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 786                 break;
 787         case DAC33_FIFO_MODE7:
 788                 /* Disable all interrupts */
 789                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 790                 break;
 791         default:
 792                 /* in FIFO bypass mode, the interrupts are not used */
 793                 break;
 794         }
 795
 796         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 797
 798         switch (dac33->fifo_mode) {
 799         case DAC33_FIFO_MODE1:
 800                 /*
 801                  * For mode1:
 802                  * Disable the FIFO bypass (Enable the use of FIFO)
 803                  * Select nSample mode
 804                  * BCLK is only running when data is needed by DAC33
 805                  */
 806                 fifoctrl_a &= ~DAC33_FBYPAS;
 807                 fifoctrl_a &= ~DAC33_FAUTO;
 808                 if (dac33->keep_bclk)
 809                         aictrl_b |= DAC33_BCLKON;
 810                 else
 811                         aictrl_b &= ~DAC33_BCLKON;
 812                 break;
 813         case DAC33_FIFO_MODE7:
 814                 /*
 815                  * For mode1:
 816                  * Disable the FIFO bypass (Enable the use of FIFO)
 817                  * Select Threshold mode
 818                  * BCLK is only running when data is needed by DAC33
 819                  */
 820                 fifoctrl_a &= ~DAC33_FBYPAS;
 821                 fifoctrl_a |= DAC33_FAUTO;
 822                 if (dac33->keep_bclk)
 823                         aictrl_b |= DAC33_BCLKON;
 824                 else
 825                         aictrl_b &= ~DAC33_BCLKON;
 826                 break;
 827         default:
 828                 /*
 829                  * For FIFO bypass mode:
 830                  * Enable the FIFO bypass (Disable the FIFO use)
 831                  * Set the BCLK as continous
 832                  */
 833                 fifoctrl_a |= DAC33_FBYPAS;
 834                 aictrl_b |= DAC33_BCLKON;
 835                 break;
 836         }
 837
 838         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
 839         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
 840         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
 841
 842         /*
 843          * BCLK divide ratio
 844          * 0: 1.5
 845          * 1: 1
 846          * 2: 2
 847          * ...
 848          * 254: 254
 849          * 255: 255
 850          */
 851         if (dac33->fifo_mode)
 852                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
 853                                                         dac33->burst_bclkdiv);
 854         else
 855                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
 856
 857         switch (dac33->fifo_mode) {
 858         case DAC33_FIFO_MODE1:
 859                 dac33_write16(codec, DAC33_ATHR_MSB,
 860                               DAC33_THRREG(dac33->alarm_threshold));
 861                 break;
 862         case DAC33_FIFO_MODE7:
 863                 /*
 864                  * Configure the threshold levels, and leave 10 sample space
 865                  * at the bottom, and also at the top of the FIFO
 866                  */
 867                 dac33_write16(codec, DAC33_UTHR_MSB,
 868                         DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES - 10));
 869                 dac33_write16(codec, DAC33_LTHR_MSB,
 870                         DAC33_THRREG(10));
 871                 break;
 872         default:
 873                 break;
 874         }
 875
 876         mutex_unlock(&dac33->mutex);
 877
 878         return 0;
 879 }
 880
 881 static void dac33_calculate_times(struct snd_pcm_substream *substream)
 882 {
 883         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 884         struct snd_soc_device *socdev = rtd->socdev;
 885         struct snd_soc_codec *codec = socdev->card->codec;
 886         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 887         unsigned int nsample_limit;
 888
 889         /* Number of samples (16bit, stereo) in one period */
 890         dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
 891
 892         /* Number of samples (16bit, stereo) in ALSA buffer */
 893         dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
 894         /* Subtract one period from the total */
 895         dac33->nsample_max -= dac33->nsample_min;
 896
 897         /* Number of samples for LATENCY_TIME_MS / 2 */
 898         dac33->alarm_threshold = substream->runtime->rate /
 899                                  (1000 / (LATENCY_TIME_MS / 2));
 900
 901         /* Find and fix up the lowest nsmaple limit */
 902         nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
 903
 904         if (dac33->nsample_min < nsample_limit)
 905                 dac33->nsample_min = nsample_limit;
 906
 907         if (dac33->nsample < dac33->nsample_min)
 908                 dac33->nsample = dac33->nsample_min;
 909
 910         /*
 911          * Find and fix up the highest nsmaple limit
 912          * In order to not overflow the DAC33 buffer substract the
 913          * alarm_threshold value from the size of the DAC33 buffer
 914          */
 915         nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
 916
 917         if (dac33->nsample_max > nsample_limit)
 918                 dac33->nsample_max = nsample_limit;
 919
 920         if (dac33->nsample > dac33->nsample_max)
 921                 dac33->nsample = dac33->nsample_max;
 922 }
 923
 924 static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
 925                              struct snd_soc_dai *dai)
 926 {
 927         dac33_calculate_times(substream);
 928         dac33_prepare_chip(substream);
 929
 930         return 0;
 931 }
 932
 933 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 934                              struct snd_soc_dai *dai)
 935 {
 936         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 937         struct snd_soc_device *socdev = rtd->socdev;
 938         struct snd_soc_codec *codec = socdev->card->codec;
 939         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 940         int ret = 0;
 941
 942         switch (cmd) {
 943         case SNDRV_PCM_TRIGGER_START:
 944         case SNDRV_PCM_TRIGGER_RESUME:
 945         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 946                 if (dac33->fifo_mode) {
 947                         dac33->state = DAC33_PREFILL;
 948                         queue_work(dac33->dac33_wq, &dac33->work);
 949                 }
 950                 break;
 951         case SNDRV_PCM_TRIGGER_STOP:
 952         case SNDRV_PCM_TRIGGER_SUSPEND:
 953         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 954                 if (dac33->fifo_mode) {
 955                         dac33->state = DAC33_FLUSH;
 956                         queue_work(dac33->dac33_wq, &dac33->work);
 957                 }
 958                 break;
 959         default:
 960                 ret = -EINVAL;
 961         }
 962
 963         return ret;
 964 }
 965
 966 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 967                 int clk_id, unsigned int freq, int dir)
 968 {
 969         struct snd_soc_codec *codec = codec_dai->codec;
 970         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 971         u8 ioc_reg, asrcb_reg;
 972
 973         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 974         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
 975         switch (clk_id) {
 976         case TLV320DAC33_MCLK:
 977                 ioc_reg |= DAC33_REFSEL;
 978                 asrcb_reg |= DAC33_SRCREFSEL;
 979                 break;
 980         case TLV320DAC33_SLEEPCLK:
 981                 ioc_reg &= ~DAC33_REFSEL;
 982                 asrcb_reg &= ~DAC33_SRCREFSEL;
 983                 break;
 984         default:
 985                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
 986                 break;
 987         }
 988         dac33->refclk = freq;
 989
 990         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
 991         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
 992
 993         return 0;
 994 }
 995
 996 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
 997                              unsigned int fmt)
 998 {
 999         struct snd_soc_codec *codec = codec_dai->codec;
1000         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1001         u8 aictrl_a, aictrl_b;
1002
1003         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1004         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1005         /* set master/slave audio interface */
1006         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1007         case SND_SOC_DAIFMT_CBM_CFM:
1008                 /* Codec Master */
1009                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1010                 break;
1011         case SND_SOC_DAIFMT_CBS_CFS:
1012                 /* Codec Slave */
1013                 if (dac33->fifo_mode) {
1014                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1015                         return -EINVAL;
1016                 } else
1017                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1018                 break;
1019         default:
1020                 return -EINVAL;
1021         }
1022
1023         aictrl_a &= ~DAC33_AFMT_MASK;
1024         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1025         case SND_SOC_DAIFMT_I2S:
1026                 aictrl_a |= DAC33_AFMT_I2S;
1027                 break;
1028         case SND_SOC_DAIFMT_DSP_A:
1029                 aictrl_a |= DAC33_AFMT_DSP;
1030                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1031                 aictrl_b |= DAC33_DATA_DELAY(0);
1032                 break;
1033         case SND_SOC_DAIFMT_RIGHT_J:
1034                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1035                 break;
1036         case SND_SOC_DAIFMT_LEFT_J:
1037                 aictrl_a |= DAC33_AFMT_LEFT_J;
1038                 break;
1039         default:
1040                 dev_err(codec->dev, "Unsupported format (%u)\n",
1041                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1042                 return -EINVAL;
1043         }
1044
1045         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1046         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1047
1048         return 0;
1049 }
1050
1051 static void dac33_init_chip(struct snd_soc_codec *codec)
1052 {
1053         /* 44-46: DAC Control Registers */
1054         /* A : DAC sample rate Fsref/1.5 */
1055         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
1056         /* B : DAC src=normal, not muted */
1057         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1058                                              DAC33_DACSRCL_LEFT);
1059         /* C : (defaults) */
1060         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1061
1062         /* 64-65 : L&R DAC power control
1063          Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1064         dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1065         dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1066
1067         /* 73 : volume soft stepping control,
1068          clock source = internal osc (?) */
1069         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1070
1071         /* 66 : LOP/LOM Modes */
1072         dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1073
1074         /* 68 : LOM inverted from LOP */
1075         dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1076
1077         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1078 }
1079
1080 static int dac33_soc_probe(struct platform_device *pdev)
1081 {
1082         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1083         struct snd_soc_codec *codec;
1084         struct tlv320dac33_priv *dac33;
1085         int ret = 0;
1086
1087         BUG_ON(!tlv320dac33_codec);
1088
1089         codec = tlv320dac33_codec;
1090         socdev->card->codec = codec;
1091         dac33 = snd_soc_codec_get_drvdata(codec);
1092
1093         /* Power up the codec */
1094         dac33_hard_power(codec, 1);
1095         /* Set default configuration */
1096         dac33_init_chip(codec);
1097
1098         /* register pcms */
1099         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1100         if (ret < 0) {
1101                 dev_err(codec->dev, "failed to create pcms\n");
1102                 goto pcm_err;
1103         }
1104
1105         snd_soc_add_controls(codec, dac33_snd_controls,
1106                              ARRAY_SIZE(dac33_snd_controls));
1107         /* Only add the nSample controls, if we have valid IRQ number */
1108         if (dac33->irq >= 0)
1109                 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1110                                      ARRAY_SIZE(dac33_nsample_snd_controls));
1111
1112         dac33_add_widgets(codec);
1113
1114         /* power on device */
1115         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1116
1117         /* Bias level configuration has enabled regulator an extra time */
1118         regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1119
1120         return 0;
1121
1122 pcm_err:
1123         dac33_hard_power(codec, 0);
1124         return ret;
1125 }
1126
1127 static int dac33_soc_remove(struct platform_device *pdev)
1128 {
1129         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1130         struct snd_soc_codec *codec = socdev->card->codec;
1131
1132         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1133
1134         snd_soc_free_pcms(socdev);
1135         snd_soc_dapm_free(socdev);
1136
1137         return 0;
1138 }
1139
1140 static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1141 {
1142         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1143         struct snd_soc_codec *codec = socdev->card->codec;
1144
1145         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1146
1147         return 0;
1148 }
1149
1150 static int dac33_soc_resume(struct platform_device *pdev)
1151 {
1152         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1153         struct snd_soc_codec *codec = socdev->card->codec;
1154
1155         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1156         dac33_set_bias_level(codec, codec->suspend_bias_level);
1157
1158         return 0;
1159 }
1160
1161 struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1162         .probe = dac33_soc_probe,
1163         .remove = dac33_soc_remove,
1164         .suspend = dac33_soc_suspend,
1165         .resume = dac33_soc_resume,
1166 };
1167 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1168
1169 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1170                          SNDRV_PCM_RATE_48000)
1171 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1172
1173 static struct snd_soc_dai_ops dac33_dai_ops = {
1174         .hw_params      = dac33_hw_params,
1175         .prepare        = dac33_pcm_prepare,
1176         .trigger        = dac33_pcm_trigger,
1177         .set_sysclk     = dac33_set_dai_sysclk,
1178         .set_fmt        = dac33_set_dai_fmt,
1179 };
1180
1181 struct snd_soc_dai dac33_dai = {
1182         .name = "tlv320dac33",
1183         .playback = {
1184                 .stream_name = "Playback",
1185                 .channels_min = 2,
1186                 .channels_max = 2,
1187                 .rates = DAC33_RATES,
1188                 .formats = DAC33_FORMATS,},
1189         .ops = &dac33_dai_ops,
1190 };
1191 EXPORT_SYMBOL_GPL(dac33_dai);
1192
1193 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1194                                      const struct i2c_device_id *id)
1195 {
1196         struct tlv320dac33_platform_data *pdata;
1197         struct tlv320dac33_priv *dac33;
1198         struct snd_soc_codec *codec;
1199         int ret, i;
1200
1201         if (client->dev.platform_data == NULL) {
1202                 dev_err(&client->dev, "Platform data not set\n");
1203                 return -ENODEV;
1204         }
1205         pdata = client->dev.platform_data;
1206
1207         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1208         if (dac33 == NULL)
1209                 return -ENOMEM;
1210
1211         codec = &dac33->codec;
1212         snd_soc_codec_set_drvdata(codec, dac33);
1213         codec->control_data = client;
1214
1215         mutex_init(&codec->mutex);
1216         mutex_init(&dac33->mutex);
1217         INIT_LIST_HEAD(&codec->dapm_widgets);
1218         INIT_LIST_HEAD(&codec->dapm_paths);
1219
1220         codec->name = "tlv320dac33";
1221         codec->owner = THIS_MODULE;
1222         codec->read = dac33_read_reg_cache;
1223         codec->write = dac33_write_locked;
1224         codec->hw_write = (hw_write_t) i2c_master_send;
1225         codec->bias_level = SND_SOC_BIAS_OFF;
1226         codec->set_bias_level = dac33_set_bias_level;
1227         codec->dai = &dac33_dai;
1228         codec->num_dai = 1;
1229         codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1230         codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1231                                    GFP_KERNEL);
1232         if (codec->reg_cache == NULL) {
1233                 ret = -ENOMEM;
1234                 goto error_reg;
1235         }
1236
1237         i2c_set_clientdata(client, dac33);
1238
1239         dac33->power_gpio = pdata->power_gpio;
1240         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1241         dac33->keep_bclk = pdata->keep_bclk;
1242         dac33->irq = client->irq;
1243         dac33->nsample = NSAMPLE_MAX;
1244         /* Disable FIFO use by default */
1245         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1246
1247         tlv320dac33_codec = codec;
1248
1249         codec->dev = &client->dev;
1250         dac33_dai.dev = codec->dev;
1251
1252         /* Check if the reset GPIO number is valid and request it */
1253         if (dac33->power_gpio >= 0) {
1254                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1255                 if (ret < 0) {
1256                         dev_err(codec->dev,
1257                                 "Failed to request reset GPIO (%d)\n",
1258                                 dac33->power_gpio);
1259                         snd_soc_unregister_dai(&dac33_dai);
1260                         snd_soc_unregister_codec(codec);
1261                         goto error_gpio;
1262                 }
1263                 gpio_direction_output(dac33->power_gpio, 0);
1264         } else {
1265                 dac33->chip_power = 1;
1266         }
1267
1268         /* Check if the IRQ number is valid and request it */
1269         if (dac33->irq >= 0) {
1270                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1271                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1272                                   codec->name, codec);
1273                 if (ret < 0) {
1274                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1275                                                 dac33->irq, ret);
1276                         dac33->irq = -1;
1277                 }
1278                 if (dac33->irq != -1) {
1279                         /* Setup work queue */
1280                         dac33->dac33_wq =
1281                                 create_singlethread_workqueue("tlv320dac33");
1282                         if (dac33->dac33_wq == NULL) {
1283                                 free_irq(dac33->irq, &dac33->codec);
1284                                 ret = -ENOMEM;
1285                                 goto error_wq;
1286                         }
1287
1288                         INIT_WORK(&dac33->work, dac33_work);
1289                 }
1290         }
1291
1292         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1293                 dac33->supplies[i].supply = dac33_supply_names[i];
1294
1295         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1296                                  dac33->supplies);
1297
1298         if (ret != 0) {
1299                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1300                 goto err_get;
1301         }
1302
1303         ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1304                                     dac33->supplies);
1305         if (ret != 0) {
1306                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1307                 goto err_enable;
1308         }
1309
1310         ret = snd_soc_register_codec(codec);
1311         if (ret != 0) {
1312                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1313                 goto error_codec;
1314         }
1315
1316         ret = snd_soc_register_dai(&dac33_dai);
1317         if (ret != 0) {
1318                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1319                 snd_soc_unregister_codec(codec);
1320                 goto error_codec;
1321         }
1322
1323         /* Shut down the codec for now */
1324         dac33_hard_power(codec, 0);
1325
1326         return ret;
1327
1328 error_codec:
1329         regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1330 err_enable:
1331         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1332 err_get:
1333         if (dac33->irq >= 0) {
1334                 free_irq(dac33->irq, &dac33->codec);
1335                 destroy_workqueue(dac33->dac33_wq);
1336         }
1337 error_wq:
1338         if (dac33->power_gpio >= 0)
1339                 gpio_free(dac33->power_gpio);
1340 error_gpio:
1341         kfree(codec->reg_cache);
1342 error_reg:
1343         tlv320dac33_codec = NULL;
1344         kfree(dac33);
1345
1346         return ret;
1347 }
1348
1349 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1350 {
1351         struct tlv320dac33_priv *dac33;
1352
1353         dac33 = i2c_get_clientdata(client);
1354         dac33_hard_power(&dac33->codec, 0);
1355
1356         if (dac33->power_gpio >= 0)
1357                 gpio_free(dac33->power_gpio);
1358         if (dac33->irq >= 0)
1359                 free_irq(dac33->irq, &dac33->codec);
1360
1361         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1362
1363         destroy_workqueue(dac33->dac33_wq);
1364         snd_soc_unregister_dai(&dac33_dai);
1365         snd_soc_unregister_codec(&dac33->codec);
1366         kfree(dac33->codec.reg_cache);
1367         kfree(dac33);
1368         tlv320dac33_codec = NULL;
1369
1370         return 0;
1371 }
1372
1373 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1374         {
1375                 .name = "tlv320dac33",
1376                 .driver_data = 0,
1377         },
1378         { },
1379 };
1380
1381 static struct i2c_driver tlv320dac33_i2c_driver = {
1382         .driver = {
1383                 .name = "tlv320dac33",
1384                 .owner = THIS_MODULE,
1385         },
1386         .probe          = dac33_i2c_probe,
1387         .remove         = __devexit_p(dac33_i2c_remove),
1388         .id_table       = tlv320dac33_i2c_id,
1389 };
1390
1391 static int __init dac33_module_init(void)
1392 {
1393         int r;
1394         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1395         if (r < 0) {
1396                 printk(KERN_ERR "DAC33: driver registration failed\n");
1397                 return r;
1398         }
1399         return 0;
1400 }
1401 module_init(dac33_module_init);
1402
1403 static void __exit dac33_module_exit(void)
1404 {
1405         i2c_del_driver(&tlv320dac33_i2c_driver);
1406 }
1407 module_exit(dac33_module_exit);
1408
1409
1410 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1411 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1412 MODULE_LICENSE("GPL");