2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
27 #include <linux/interrupt.h>
29 #define DRV_NAME "jme"
30 #define DRV_VERSION "1.0.8.2-jmmod"
31 #define PFX DRV_NAME ": "
33 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
37 * Message related definitions
39 #define JME_DEF_MSG_ENABLE \
47 #define pr_err(fmt, arg...) \
48 printk(KERN_ERR fmt, ##arg)
51 #define netdev_err(netdev, fmt, arg...) \
56 #define tx_dbg(priv, fmt, args...) \
57 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
59 #define tx_dbg(priv, fmt, args...) \
62 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
66 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
67 #define jme_msg(msglvl, type, priv, fmt, args...) \
68 if (netif_msg_##type(priv)) \
69 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
71 #define msg_probe(priv, fmt, args...) \
72 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
74 #define msg_link(priv, fmt, args...) \
75 jme_msg(KERN_INFO, link, priv, fmt, ## args)
77 #define msg_intr(priv, fmt, args...) \
78 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
80 #define msg_rx_err(priv, fmt, args...) \
81 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
83 #define msg_rx_status(priv, fmt, args...) \
84 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
86 #define msg_tx_err(priv, fmt, args...) \
87 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
89 #define msg_tx_done(priv, fmt, args...) \
90 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
92 #define msg_tx_queued(priv, fmt, args...) \
93 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
95 #define msg_hw(priv, fmt, args...) \
96 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
99 #define netif_info(priv, type, dev, fmt, args...) \
100 msg_ ## type(priv, fmt, ## args)
103 #define netif_err(priv, type, dev, fmt, args...) \
104 msg_ ## type(priv, fmt, ## args)
109 #define NETIF_F_TSO6 0
111 #ifndef NETIF_F_IPV6_CSUM
112 #define NETIF_F_IPV6_CSUM 0
115 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
119 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
120 #define __USE_NDO_FIX_FEATURES__
123 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,1,0)
124 #define __UNIFY_VLAN_RX_PATH__
125 #define __USE_NDO_SET_RX_MODE__
128 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
129 #define __USE_SKB_FRAG_API__
132 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)
133 #define __NEW_FIX_FEATURES_TYPE__
137 * Extra PCI Configuration space interface
139 #define PCI_DCSR_MRRS 0x59
140 #define PCI_DCSR_MRRS_MASK 0x70
142 enum pci_dcsr_mrrs_vals {
164 __u8 wn; /* Number of write actions */
165 __u8 rn; /* Number of read actions */
166 __u8 bitn; /* Number of bits per action */
167 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
168 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
170 /* Internal use only */
174 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
177 enum jme_spi_op_bits {
178 SPI_MODE_CPHA = 0x01,
179 SPI_MODE_CPOL = 0x02,
183 #define HALF_US 500 /* 500 ns */
185 #define PCI_PRIV_PE1 0xE4
187 enum pci_priv_pe1_bit_masks {
188 PE1_ASPMSUPRT = 0x00000003, /*
191 * (R/W Port of 5C[11:10])
193 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
194 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
195 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
196 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
197 PE1_GPREG0 = 0x0000FF00, /*
200 * [7:6] phy_giga BG control
201 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
204 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
205 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
206 PE1_REVID = 0xFF000000, /* RO: Rev ID */
209 enum pci_priv_pe1_values {
210 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
211 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
212 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
213 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
217 * Dynamic(adaptive)/Static PCC values
219 enum dynamic_pcc_values {
236 unsigned long last_bytes;
237 unsigned long last_pkts;
238 unsigned long intr_cnt;
240 unsigned char attempt;
243 #define PCC_INTERVAL_US 100000
244 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
245 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
246 #define PCC_P2_THRESHOLD 800
247 #define PCC_INTR_THRESHOLD 800
248 #define PCC_TX_TO 1000
254 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
256 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
257 #define TX_DESC_SIZE 16
259 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
319 enum jme_txdesc_flags_bits {
330 #define TXDESC_MSS_SHIFT 2
331 enum jme_txwbdesc_flags_bits {
334 TXWBFLAG_TMOUT = 0x20,
335 TXWBFLAG_TRYOUT = 0x10,
338 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
343 #define RX_DESC_SIZE 16
345 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
346 #define RX_BUF_DMA_ALIGN 8
347 #define RX_PREPAD_SIZE 10
348 #define ETH_CRC_LEN 2
349 #define RX_VLANHDR_LEN 2
350 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
397 enum jme_rxdesc_flags_bits {
403 enum jme_rxwbdesc_flags_bits {
404 RXWBFLAG_OWN = 0x8000,
405 RXWBFLAG_INT = 0x4000,
406 RXWBFLAG_MF = 0x2000,
407 RXWBFLAG_64BIT = 0x2000,
408 RXWBFLAG_TCPON = 0x1000,
409 RXWBFLAG_UDPON = 0x0800,
410 RXWBFLAG_IPCS = 0x0400,
411 RXWBFLAG_TCPCS = 0x0200,
412 RXWBFLAG_UDPCS = 0x0100,
413 RXWBFLAG_TAGON = 0x0080,
414 RXWBFLAG_IPV4 = 0x0040,
415 RXWBFLAG_IPV6 = 0x0020,
416 RXWBFLAG_PAUSE = 0x0010,
417 RXWBFLAG_MAGIC = 0x0008,
418 RXWBFLAG_WAKEUP = 0x0004,
419 RXWBFLAG_DEST = 0x0003,
420 RXWBFLAG_DEST_UNI = 0x0001,
421 RXWBFLAG_DEST_MUL = 0x0002,
422 RXWBFLAG_DEST_BRO = 0x0003,
425 enum jme_rxwbdesc_desccnt_mask {
426 RXWBDCNT_WBCPL = 0x80,
427 RXWBDCNT_DCNT = 0x7F,
430 enum jme_rxwbdesc_errstat_bits {
431 RXWBERR_LIMIT = 0x80,
432 RXWBERR_MIIER = 0x40,
433 RXWBERR_NIBON = 0x20,
434 RXWBERR_COLON = 0x10,
435 RXWBERR_ABORT = 0x08,
436 RXWBERR_SHORT = 0x04,
437 RXWBERR_OVERUN = 0x02,
438 RXWBERR_CRCERR = 0x01,
439 RXWBERR_ALLERR = 0xFF,
443 * Buffer information corresponding to ring descriptors.
445 struct jme_buffer_info {
450 unsigned long start_xmit;
454 * The structure holding buffer information and ring descriptors all together.
457 void *alloc; /* pointer to allocated memory */
458 void *desc; /* pointer to ring memory */
459 dma_addr_t dmaalloc; /* phys address of ring alloc */
460 dma_addr_t dma; /* phys address for ring dma */
462 /* Buffer information corresponding to each descriptor */
463 struct jme_buffer_info *bufinf;
466 atomic_t next_to_clean;
470 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
473 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
474 #define PCI_VENDOR_ID_JMICRON 0x197B
477 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
478 #define PCI_VDEVICE(vendor, device) \
479 PCI_VENDOR_ID_##vendor, (device), \
480 PCI_ANY_ID, PCI_ANY_ID, 0, 0
483 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
484 #define NET_STAT(priv) priv->stats
485 #define NETDEV_GET_STATS(netdev, fun_ptr) \
486 netdev->get_stats = fun_ptr
487 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
489 * CentOS 5.2 have *_hdr helpers back-ported
491 #ifdef RHEL_RELEASE_CODE
492 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
493 #define __DEFINE_IPHDR_HELPERS__
496 #define __DEFINE_IPHDR_HELPERS__
499 #define NET_STAT(priv) (priv->dev->stats)
500 #define NETDEV_GET_STATS(netdev, fun_ptr)
501 #define DECLARE_NET_DEVICE_STATS
504 #ifdef __DEFINE_IPHDR_HELPERS__
505 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
510 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
512 return skb->nh.ipv6h;
515 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
521 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
522 #define DECLARE_NAPI_STRUCT
523 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
524 dev->poll = pollfn; \
526 #define JME_NAPI_HOLDER(holder) struct net_device *holder
527 #define JME_NAPI_WEIGHT(w) int *w
528 #define JME_NAPI_WEIGHT_VAL(w) *w
529 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
530 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
531 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
532 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
533 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
534 #define JME_RX_SCHEDULE_PREP(priv) \
535 netif_rx_schedule_prep(priv->dev)
536 #define JME_RX_SCHEDULE(priv) \
537 __netif_rx_schedule(priv->dev);
539 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
540 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
541 netif_napi_add(dev, napis, pollfn, q);
542 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
543 #define JME_NAPI_WEIGHT(w) int w
544 #define JME_NAPI_WEIGHT_VAL(w) w
545 #define JME_NAPI_WEIGHT_SET(w, r)
546 #define DECLARE_NETDEV
547 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
548 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
549 #define JME_NAPI_DISABLE(priv) \
550 if (!napi_disable_pending(&priv->napi)) \
551 napi_disable(&priv->napi);
552 #define JME_RX_SCHEDULE_PREP(priv) \
553 napi_schedule_prep(&priv->napi)
554 #define JME_RX_SCHEDULE(priv) \
555 __napi_schedule(&priv->napi);
558 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
559 #define JME_NEW_PM_API
562 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)
563 static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
570 * Jmac Adapter Private data
573 struct pci_dev *pdev;
574 struct net_device *dev;
576 struct mii_if_info mii_if;
577 struct jme_ring rxring[RX_RING_NR];
578 struct jme_ring txring[TX_RING_NR];
580 spinlock_t macaddr_lock;
581 spinlock_t rxmcs_lock;
582 struct tasklet_struct rxempty_task;
583 struct tasklet_struct rxclean_task;
584 struct tasklet_struct txclean_task;
585 struct tasklet_struct linkch_task;
586 struct tasklet_struct pcc_task;
598 u32 tx_wake_threshold;
602 unsigned int fpgaver;
608 struct ethtool_cmd old_ecmd;
609 unsigned int old_mtu;
610 #ifndef __UNIFY_VLAN_RX_PATH__
611 struct vlan_group *vlgrp;
613 struct dynpcc_info dpi;
615 atomic_t link_changing;
616 atomic_t tx_cleaning;
617 atomic_t rx_cleaning;
619 int (*jme_rx)(struct sk_buff *skb);
620 #ifndef __UNIFY_VLAN_RX_PATH__
621 int (*jme_vlan_rx)(struct sk_buff *skb,
622 struct vlan_group *grp,
623 unsigned short vlan_tag);
626 DECLARE_NET_DEVICE_STATS
629 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
630 static struct net_device_stats *
631 jme_get_stats(struct net_device *netdev)
633 struct jme_adapter *jme = netdev_priv(netdev);
638 enum jme_flags_bits {
641 #ifndef __USE_NDO_FIX_FEATURES__
646 JME_FLAG_SHUTDOWN = 6,
649 #define TX_TIMEOUT (5 * HZ)
650 #define JME_REG_LEN 0x500
651 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
653 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
654 static inline struct jme_adapter*
655 jme_napi_priv(struct net_device *holder)
657 struct jme_adapter *jme;
658 jme = netdev_priv(holder);
662 static inline struct jme_adapter*
663 jme_napi_priv(struct napi_struct *napi)
665 struct jme_adapter *jme;
666 jme = container_of(napi, struct jme_adapter, napi);
674 enum jme_iomap_offsets {
681 enum jme_iomap_lens {
688 enum jme_iomap_regs {
689 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
690 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
691 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
692 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
693 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
694 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
695 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
696 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
698 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
699 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
700 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
701 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
702 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
703 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
704 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
705 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
706 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
707 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
708 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
709 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
711 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
712 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
713 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
716 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
717 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
718 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
719 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
720 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
723 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
724 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
725 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
726 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
727 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
728 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
729 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
730 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
731 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
732 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
733 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
734 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
735 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
736 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
737 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
738 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
742 * TX Control/Status Bits
745 TXCS_QUEUE7S = 0x00008000,
746 TXCS_QUEUE6S = 0x00004000,
747 TXCS_QUEUE5S = 0x00002000,
748 TXCS_QUEUE4S = 0x00001000,
749 TXCS_QUEUE3S = 0x00000800,
750 TXCS_QUEUE2S = 0x00000400,
751 TXCS_QUEUE1S = 0x00000200,
752 TXCS_QUEUE0S = 0x00000100,
753 TXCS_FIFOTH = 0x000000C0,
754 TXCS_DMASIZE = 0x00000030,
755 TXCS_BURST = 0x00000004,
756 TXCS_ENABLE = 0x00000001,
759 enum jme_txcs_value {
760 TXCS_FIFOTH_16QW = 0x000000C0,
761 TXCS_FIFOTH_12QW = 0x00000080,
762 TXCS_FIFOTH_8QW = 0x00000040,
763 TXCS_FIFOTH_4QW = 0x00000000,
765 TXCS_DMASIZE_64B = 0x00000000,
766 TXCS_DMASIZE_128B = 0x00000010,
767 TXCS_DMASIZE_256B = 0x00000020,
768 TXCS_DMASIZE_512B = 0x00000030,
770 TXCS_SELECT_QUEUE0 = 0x00000000,
771 TXCS_SELECT_QUEUE1 = 0x00010000,
772 TXCS_SELECT_QUEUE2 = 0x00020000,
773 TXCS_SELECT_QUEUE3 = 0x00030000,
774 TXCS_SELECT_QUEUE4 = 0x00040000,
775 TXCS_SELECT_QUEUE5 = 0x00050000,
776 TXCS_SELECT_QUEUE6 = 0x00060000,
777 TXCS_SELECT_QUEUE7 = 0x00070000,
779 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
783 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
786 * TX MAC Control/Status Bits
788 enum jme_txmcs_bit_masks {
789 TXMCS_IFG2 = 0xC0000000,
790 TXMCS_IFG1 = 0x30000000,
791 TXMCS_TTHOLD = 0x00000300,
792 TXMCS_FBURST = 0x00000080,
793 TXMCS_CARRIEREXT = 0x00000040,
794 TXMCS_DEFER = 0x00000020,
795 TXMCS_BACKOFF = 0x00000010,
796 TXMCS_CARRIERSENSE = 0x00000008,
797 TXMCS_COLLISION = 0x00000004,
798 TXMCS_CRC = 0x00000002,
799 TXMCS_PADDING = 0x00000001,
802 enum jme_txmcs_values {
803 TXMCS_IFG2_6_4 = 0x00000000,
804 TXMCS_IFG2_8_5 = 0x40000000,
805 TXMCS_IFG2_10_6 = 0x80000000,
806 TXMCS_IFG2_12_7 = 0xC0000000,
808 TXMCS_IFG1_8_4 = 0x00000000,
809 TXMCS_IFG1_12_6 = 0x10000000,
810 TXMCS_IFG1_16_8 = 0x20000000,
811 TXMCS_IFG1_20_10 = 0x30000000,
813 TXMCS_TTHOLD_1_8 = 0x00000000,
814 TXMCS_TTHOLD_1_4 = 0x00000100,
815 TXMCS_TTHOLD_1_2 = 0x00000200,
816 TXMCS_TTHOLD_FULL = 0x00000300,
818 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
826 enum jme_txpfc_bits_masks {
827 TXPFC_VLAN_TAG = 0xFFFF0000,
828 TXPFC_VLAN_EN = 0x00008000,
829 TXPFC_PF_EN = 0x00000001,
832 enum jme_txtrhd_bits_masks {
833 TXTRHD_TXPEN = 0x80000000,
834 TXTRHD_TXP = 0x7FFFFF00,
835 TXTRHD_TXREN = 0x00000080,
836 TXTRHD_TXRL = 0x0000007F,
839 enum jme_txtrhd_shifts {
840 TXTRHD_TXP_SHIFT = 8,
841 TXTRHD_TXRL_SHIFT = 0,
844 enum jme_txtrhd_values {
845 TXTRHD_FULLDUPLEX = 0x00000000,
846 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
847 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
849 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
853 * RX Control/Status Bits
855 enum jme_rxcs_bit_masks {
856 /* FIFO full threshold for transmitting Tx Pause Packet */
857 RXCS_FIFOTHTP = 0x30000000,
858 /* FIFO threshold for processing next packet */
859 RXCS_FIFOTHNP = 0x0C000000,
860 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
861 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
862 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
863 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
864 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
865 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
866 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
867 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
868 RXCS_QST = 0x00000004, /* Receive queue start */
869 RXCS_SUSPEND = 0x00000002,
870 RXCS_ENABLE = 0x00000001,
873 enum jme_rxcs_values {
874 RXCS_FIFOTHTP_16T = 0x00000000,
875 RXCS_FIFOTHTP_32T = 0x10000000,
876 RXCS_FIFOTHTP_64T = 0x20000000,
877 RXCS_FIFOTHTP_128T = 0x30000000,
879 RXCS_FIFOTHNP_16QW = 0x00000000,
880 RXCS_FIFOTHNP_32QW = 0x04000000,
881 RXCS_FIFOTHNP_64QW = 0x08000000,
882 RXCS_FIFOTHNP_128QW = 0x0C000000,
884 RXCS_DMAREQSZ_16B = 0x00000000,
885 RXCS_DMAREQSZ_32B = 0x01000000,
886 RXCS_DMAREQSZ_64B = 0x02000000,
887 RXCS_DMAREQSZ_128B = 0x03000000,
889 RXCS_QUEUESEL_Q0 = 0x00000000,
890 RXCS_QUEUESEL_Q1 = 0x00010000,
891 RXCS_QUEUESEL_Q2 = 0x00020000,
892 RXCS_QUEUESEL_Q3 = 0x00030000,
894 RXCS_RETRYGAP_256ns = 0x00000000,
895 RXCS_RETRYGAP_512ns = 0x00001000,
896 RXCS_RETRYGAP_1024ns = 0x00002000,
897 RXCS_RETRYGAP_2048ns = 0x00003000,
898 RXCS_RETRYGAP_4096ns = 0x00004000,
899 RXCS_RETRYGAP_8192ns = 0x00005000,
900 RXCS_RETRYGAP_16384ns = 0x00006000,
901 RXCS_RETRYGAP_32768ns = 0x00007000,
903 RXCS_RETRYCNT_0 = 0x00000000,
904 RXCS_RETRYCNT_4 = 0x00000100,
905 RXCS_RETRYCNT_8 = 0x00000200,
906 RXCS_RETRYCNT_12 = 0x00000300,
907 RXCS_RETRYCNT_16 = 0x00000400,
908 RXCS_RETRYCNT_20 = 0x00000500,
909 RXCS_RETRYCNT_24 = 0x00000600,
910 RXCS_RETRYCNT_28 = 0x00000700,
911 RXCS_RETRYCNT_32 = 0x00000800,
912 RXCS_RETRYCNT_36 = 0x00000900,
913 RXCS_RETRYCNT_40 = 0x00000A00,
914 RXCS_RETRYCNT_44 = 0x00000B00,
915 RXCS_RETRYCNT_48 = 0x00000C00,
916 RXCS_RETRYCNT_52 = 0x00000D00,
917 RXCS_RETRYCNT_56 = 0x00000E00,
918 RXCS_RETRYCNT_60 = 0x00000F00,
920 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
923 RXCS_RETRYGAP_256ns |
927 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
930 * RX MAC Control/Status Bits
932 enum jme_rxmcs_bits {
933 RXMCS_ALLFRAME = 0x00000800,
934 RXMCS_BRDFRAME = 0x00000400,
935 RXMCS_MULFRAME = 0x00000200,
936 RXMCS_UNIFRAME = 0x00000100,
937 RXMCS_ALLMULFRAME = 0x00000080,
938 RXMCS_MULFILTERED = 0x00000040,
939 RXMCS_RXCOLLDEC = 0x00000020,
940 RXMCS_FLOWCTRL = 0x00000008,
941 RXMCS_VTAGRM = 0x00000004,
942 RXMCS_PREPAD = 0x00000002,
943 RXMCS_CHECKSUM = 0x00000001,
945 RXMCS_DEFAULT = RXMCS_VTAGRM |
951 /* Extern PHY common register 2 */
953 #define PHY_GAD_TEST_MODE_1 0x00002000
954 #define PHY_GAD_TEST_MODE_MSK 0x0000E000
955 #define JM_PHY_SPEC_REG_READ 0x00004000
956 #define JM_PHY_SPEC_REG_WRITE 0x00008000
957 #define PHY_CALIBRATION_DELAY 20
958 #define JM_PHY_SPEC_ADDR_REG 0x1E
959 #define JM_PHY_SPEC_DATA_REG 0x1F
961 #define JM_PHY_EXT_COMM_0_REG 0x30
962 #define JM_PHY_EXT_COMM_1_REG 0x31
963 #define JM_PHY_EXT_COMM_2_REG 0x32
964 #define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
965 #define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
966 #define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
967 #define PCI_PRIV_SHARE_NICCTRL 0xF5
968 #define JME_FLAG_PHYEA_ENABLE 0x2
971 * Wakeup Frame setup interface registers
973 #define WAKEUP_FRAME_NR 8
974 #define WAKEUP_FRAME_MASK_DWNR 4
976 enum jme_wfoi_bit_masks {
977 WFOI_MASK_SEL = 0x00000070,
978 WFOI_CRC_SEL = 0x00000008,
979 WFOI_FRAME_SEL = 0x00000007,
982 enum jme_wfoi_shifts {
987 * SMI Related definitions
989 enum jme_smi_bit_mask {
990 SMI_DATA_MASK = 0xFFFF0000,
991 SMI_REG_ADDR_MASK = 0x0000F800,
992 SMI_PHY_ADDR_MASK = 0x000007C0,
993 SMI_OP_WRITE = 0x00000020,
994 /* Set to 1, after req done it'll be cleared to 0 */
995 SMI_OP_REQ = 0x00000010,
996 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
997 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
998 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
999 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
1002 enum jme_smi_bit_shift {
1003 SMI_DATA_SHIFT = 16,
1004 SMI_REG_ADDR_SHIFT = 11,
1005 SMI_PHY_ADDR_SHIFT = 6,
1008 static inline u32 smi_reg_addr(int x)
1010 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
1013 static inline u32 smi_phy_addr(int x)
1015 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
1018 #define JME_PHY_TIMEOUT 100 /* 100 msec */
1019 #define JME_PHY_REG_NR 32
1022 * Global Host Control
1024 enum jme_ghc_bit_mask {
1025 GHC_SWRST = 0x40000000,
1026 GHC_TO_CLK_SRC = 0x00C00000,
1027 GHC_TXMAC_CLK_SRC = 0x00300000,
1028 GHC_DPX = 0x00000040,
1029 GHC_SPEED = 0x00000030,
1030 GHC_LINK_POLL = 0x00000001,
1033 enum jme_ghc_speed_val {
1034 GHC_SPEED_10M = 0x00000010,
1035 GHC_SPEED_100M = 0x00000020,
1036 GHC_SPEED_1000M = 0x00000030,
1039 enum jme_ghc_to_clk {
1040 GHC_TO_CLK_OFF = 0x00000000,
1041 GHC_TO_CLK_GPHY = 0x00400000,
1042 GHC_TO_CLK_PCIE = 0x00800000,
1043 GHC_TO_CLK_INVALID = 0x00C00000,
1046 enum jme_ghc_txmac_clk {
1047 GHC_TXMAC_CLK_OFF = 0x00000000,
1048 GHC_TXMAC_CLK_GPHY = 0x00100000,
1049 GHC_TXMAC_CLK_PCIE = 0x00200000,
1050 GHC_TXMAC_CLK_INVALID = 0x00300000,
1054 * Power management control and status register
1056 enum jme_pmcs_bit_masks {
1057 PMCS_STMASK = 0xFFFF0000,
1058 PMCS_WF7DET = 0x80000000,
1059 PMCS_WF6DET = 0x40000000,
1060 PMCS_WF5DET = 0x20000000,
1061 PMCS_WF4DET = 0x10000000,
1062 PMCS_WF3DET = 0x08000000,
1063 PMCS_WF2DET = 0x04000000,
1064 PMCS_WF1DET = 0x02000000,
1065 PMCS_WF0DET = 0x01000000,
1066 PMCS_LFDET = 0x00040000,
1067 PMCS_LRDET = 0x00020000,
1068 PMCS_MFDET = 0x00010000,
1069 PMCS_ENMASK = 0x0000FFFF,
1070 PMCS_WF7EN = 0x00008000,
1071 PMCS_WF6EN = 0x00004000,
1072 PMCS_WF5EN = 0x00002000,
1073 PMCS_WF4EN = 0x00001000,
1074 PMCS_WF3EN = 0x00000800,
1075 PMCS_WF2EN = 0x00000400,
1076 PMCS_WF1EN = 0x00000200,
1077 PMCS_WF0EN = 0x00000100,
1078 PMCS_LFEN = 0x00000004,
1079 PMCS_LREN = 0x00000002,
1080 PMCS_MFEN = 0x00000001,
1084 * New PHY Power Control Register
1086 enum jme_phy_pwr_bit_masks {
1087 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1088 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1089 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1090 PHY_PWR_CLKSEL = 0x08000000, /*
1091 * XTL_OUT Clock select
1092 * (an internal free-running clock)
1093 * 0: xtl_out = phy_giga.A_XTL25_O
1094 * 1: xtl_out = phy_giga.PD_OSC
1099 * Giga PHY Status Registers
1101 enum jme_phy_link_bit_mask {
1102 PHY_LINK_SPEED_MASK = 0x0000C000,
1103 PHY_LINK_DUPLEX = 0x00002000,
1104 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
1105 PHY_LINK_UP = 0x00000400,
1106 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
1107 PHY_LINK_MDI_STAT = 0x00000040,
1110 enum jme_phy_link_speed_val {
1111 PHY_LINK_SPEED_10M = 0x00000000,
1112 PHY_LINK_SPEED_100M = 0x00004000,
1113 PHY_LINK_SPEED_1000M = 0x00008000,
1116 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
1119 * SMB Control and Status
1121 enum jme_smbcsr_bit_mask {
1122 SMBCSR_CNACK = 0x00020000,
1123 SMBCSR_RELOAD = 0x00010000,
1124 SMBCSR_EEPROMD = 0x00000020,
1125 SMBCSR_INITDONE = 0x00000010,
1126 SMBCSR_BUSY = 0x0000000F,
1129 enum jme_smbintf_bit_mask {
1130 SMBINTF_HWDATR = 0xFF000000,
1131 SMBINTF_HWDATW = 0x00FF0000,
1132 SMBINTF_HWADDR = 0x0000FF00,
1133 SMBINTF_HWRWN = 0x00000020,
1134 SMBINTF_HWCMD = 0x00000010,
1135 SMBINTF_FASTM = 0x00000008,
1136 SMBINTF_GPIOSCL = 0x00000004,
1137 SMBINTF_GPIOSDA = 0x00000002,
1138 SMBINTF_GPIOEN = 0x00000001,
1141 enum jme_smbintf_vals {
1142 SMBINTF_HWRWN_READ = 0x00000020,
1143 SMBINTF_HWRWN_WRITE = 0x00000000,
1146 enum jme_smbintf_shifts {
1147 SMBINTF_HWDATR_SHIFT = 24,
1148 SMBINTF_HWDATW_SHIFT = 16,
1149 SMBINTF_HWADDR_SHIFT = 8,
1152 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1153 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1154 #define JME_SMB_LEN 256
1155 #define JME_EEPROM_MAGIC 0x250
1158 * Timer Control/Status Register
1160 enum jme_tmcsr_bit_masks {
1161 TMCSR_SWIT = 0x80000000,
1162 TMCSR_EN = 0x01000000,
1163 TMCSR_CNT = 0x00FFFFFF,
1167 * General Purpose REG-0
1169 enum jme_gpreg0_masks {
1170 GPREG0_DISSH = 0xFF000000,
1171 GPREG0_PCIRLMT = 0x00300000,
1172 GPREG0_PCCNOMUTCLR = 0x00040000,
1173 GPREG0_LNKINTPOLL = 0x00001000,
1174 GPREG0_PCCTMR = 0x00000300,
1175 GPREG0_PHYADDR = 0x0000001F,
1178 enum jme_gpreg0_vals {
1179 GPREG0_DISSH_DW7 = 0x80000000,
1180 GPREG0_DISSH_DW6 = 0x40000000,
1181 GPREG0_DISSH_DW5 = 0x20000000,
1182 GPREG0_DISSH_DW4 = 0x10000000,
1183 GPREG0_DISSH_DW3 = 0x08000000,
1184 GPREG0_DISSH_DW2 = 0x04000000,
1185 GPREG0_DISSH_DW1 = 0x02000000,
1186 GPREG0_DISSH_DW0 = 0x01000000,
1187 GPREG0_DISSH_ALL = 0xFF000000,
1189 GPREG0_PCIRLMT_8 = 0x00000000,
1190 GPREG0_PCIRLMT_6 = 0x00100000,
1191 GPREG0_PCIRLMT_5 = 0x00200000,
1192 GPREG0_PCIRLMT_4 = 0x00300000,
1194 GPREG0_PCCTMR_16ns = 0x00000000,
1195 GPREG0_PCCTMR_256ns = 0x00000100,
1196 GPREG0_PCCTMR_1us = 0x00000200,
1197 GPREG0_PCCTMR_1ms = 0x00000300,
1199 GPREG0_PHYADDR_1 = 0x00000001,
1201 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1207 * General Purpose REG-1
1209 enum jme_gpreg1_bit_masks {
1210 GPREG1_RXCLKOFF = 0x04000000,
1211 GPREG1_PCREQN = 0x00020000,
1212 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1213 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1214 GPREG1_INTRDELAYUNIT = 0x00000018,
1215 GPREG1_INTRDELAYENABLE = 0x00000007,
1218 enum jme_gpreg1_vals {
1219 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1220 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1221 GPREG1_INTDLYUNIT_1US = 0x00000010,
1222 GPREG1_INTDLYUNIT_16US = 0x00000018,
1224 GPREG1_INTDLYEN_1U = 0x00000001,
1225 GPREG1_INTDLYEN_2U = 0x00000002,
1226 GPREG1_INTDLYEN_3U = 0x00000003,
1227 GPREG1_INTDLYEN_4U = 0x00000004,
1228 GPREG1_INTDLYEN_5U = 0x00000005,
1229 GPREG1_INTDLYEN_6U = 0x00000006,
1230 GPREG1_INTDLYEN_7U = 0x00000007,
1232 GPREG1_DEFAULT = GPREG1_PCREQN,
1236 * Interrupt Status Bits
1238 enum jme_interrupt_bits {
1239 INTR_SWINTR = 0x80000000,
1240 INTR_TMINTR = 0x40000000,
1241 INTR_LINKCH = 0x20000000,
1242 INTR_PAUSERCV = 0x10000000,
1243 INTR_MAGICRCV = 0x08000000,
1244 INTR_WAKERCV = 0x04000000,
1245 INTR_PCCRX0TO = 0x02000000,
1246 INTR_PCCRX1TO = 0x01000000,
1247 INTR_PCCRX2TO = 0x00800000,
1248 INTR_PCCRX3TO = 0x00400000,
1249 INTR_PCCTXTO = 0x00200000,
1250 INTR_PCCRX0 = 0x00100000,
1251 INTR_PCCRX1 = 0x00080000,
1252 INTR_PCCRX2 = 0x00040000,
1253 INTR_PCCRX3 = 0x00020000,
1254 INTR_PCCTX = 0x00010000,
1255 INTR_RX3EMP = 0x00008000,
1256 INTR_RX2EMP = 0x00004000,
1257 INTR_RX1EMP = 0x00002000,
1258 INTR_RX0EMP = 0x00001000,
1259 INTR_RX3 = 0x00000800,
1260 INTR_RX2 = 0x00000400,
1261 INTR_RX1 = 0x00000200,
1262 INTR_RX0 = 0x00000100,
1263 INTR_TX7 = 0x00000080,
1264 INTR_TX6 = 0x00000040,
1265 INTR_TX5 = 0x00000020,
1266 INTR_TX4 = 0x00000010,
1267 INTR_TX3 = 0x00000008,
1268 INTR_TX2 = 0x00000004,
1269 INTR_TX1 = 0x00000002,
1270 INTR_TX0 = 0x00000001,
1273 static const u32 INTR_ENABLE = INTR_SWINTR |
1283 * PCC Control Registers
1285 enum jme_pccrx_masks {
1286 PCCRXTO_MASK = 0xFFFF0000,
1287 PCCRX_MASK = 0x0000FF00,
1290 enum jme_pcctx_masks {
1291 PCCTXTO_MASK = 0xFFFF0000,
1292 PCCTX_MASK = 0x0000FF00,
1293 PCCTX_QS_MASK = 0x000000FF,
1296 enum jme_pccrx_shifts {
1301 enum jme_pcctx_shifts {
1306 enum jme_pcctx_bits {
1307 PCCTXQ0_EN = 0x00000001,
1308 PCCTXQ1_EN = 0x00000002,
1309 PCCTXQ2_EN = 0x00000004,
1310 PCCTXQ3_EN = 0x00000008,
1311 PCCTXQ4_EN = 0x00000010,
1312 PCCTXQ5_EN = 0x00000020,
1313 PCCTXQ6_EN = 0x00000040,
1314 PCCTXQ7_EN = 0x00000080,
1318 * Chip Mode Register
1320 enum jme_chipmode_bit_masks {
1321 CM_FPGAVER_MASK = 0xFFFF0000,
1322 CM_CHIPREV_MASK = 0x0000FF00,
1323 CM_CHIPMODE_MASK = 0x0000000F,
1326 enum jme_chipmode_shifts {
1327 CM_FPGAVER_SHIFT = 16,
1328 CM_CHIPREV_SHIFT = 8,
1332 * Aggressive Power Mode Control
1334 enum jme_apmc_bits {
1335 JME_APMC_PCIE_SD_EN = 0x40000000,
1336 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1337 JME_APMC_EPIEN = 0x04000000,
1338 JME_APMC_EPIEN_CTRL = 0x03000000,
1341 enum jme_apmc_values {
1342 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1343 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1346 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1349 static char *MAC_REG_NAME[] = {
1350 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1351 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1352 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1353 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1354 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1355 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1358 static char *PE_REG_NAME[] = {
1359 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1360 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1361 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1362 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1363 "JME_SMBCSR", "JME_SMBINTF"};
1365 static char *MISC_REG_NAME[] = {
1366 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1367 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1368 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1369 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1370 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1371 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1372 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1373 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1376 static inline void reg_dbg(const struct jme_adapter *jme,
1377 const char *msg, u32 val, u32 reg)
1379 const char *regname;
1380 switch (reg & 0xF00) {
1382 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1385 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1388 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1391 regname = PE_REG_NAME[0];
1393 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1397 static inline void reg_dbg(const struct jme_adapter *jme,
1398 const char *msg, u32 val, u32 reg) {}
1402 * Read/Write MMaped I/O Registers
1404 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1406 return readl(jme->regs + reg);
1409 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1411 reg_dbg(jme, "REG WRITE", val, reg);
1412 writel(val, jme->regs + reg);
1413 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1416 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1419 * Read after write should cause flush
1421 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1422 writel(val, jme->regs + reg);
1423 readl(jme->regs + reg);
1424 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1430 enum jme_phy_reg17_bit_masks {
1431 PREG17_SPEED = 0xC000,
1432 PREG17_DUPLEX = 0x2000,
1433 PREG17_SPDRSV = 0x0800,
1434 PREG17_LNKUP = 0x0400,
1435 PREG17_MDI = 0x0040,
1438 enum jme_phy_reg17_vals {
1439 PREG17_SPEED_10M = 0x0000,
1440 PREG17_SPEED_100M = 0x4000,
1441 PREG17_SPEED_1000M = 0x8000,
1444 #define BMSR_ANCOMP 0x0020
1449 static inline int is_buggy250(unsigned short device, u8 chiprev)
1451 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1454 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1456 return chip_main_rev >= 5;
1460 * Function prototypes
1462 static int jme_set_settings(struct net_device *netdev,
1463 struct ethtool_cmd *ecmd);
1464 static void jme_set_unicastaddr(struct net_device *netdev);
1465 static void jme_set_multi(struct net_device *netdev);