2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
89 struct jme_adapter *jme = netdev_priv(netdev);
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
110 jme_reset_phy_processor(struct jme_adapter *jme)
114 jme_mdio_write(jme->dev,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125 val = jme_mdio_read(jme->dev,
129 jme_mdio_write(jme->dev,
131 MII_BMCR, val | BMCR_RESET);
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 jwrite32(jme, JME_WFODP, crc);
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
158 jwrite32(jme, JME_WFODP, mask[i]);
164 jme_reset_mac_processor(struct jme_adapter *jme)
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
204 jme_clear_pm(struct jme_adapter *jme)
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
212 jme_reload_eeprom(struct jme_adapter *jme)
217 val = jread32(jme, JME_SMBCSR);
219 if (val & SMBCSR_EEPROMD) {
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
242 jme_load_macaddr(struct net_device *netdev)
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
295 jme_start_irq(struct jme_adapter *jme)
297 register struct dynpcc_info *dpi = &(jme->dpi);
299 jme_set_rx_pcc(jme, PCC_P1);
301 dpi->attempt = PCC_P1;
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
317 jme_stop_irq(struct jme_adapter *jme)
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326 jme_enable_shadow(struct jme_adapter *jme)
330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
334 jme_disable_shadow(struct jme_adapter *jme)
336 jwrite32(jme, JME_SHBA_LO, 0x0);
340 jme_linkstat_from_phy(struct jme_adapter *jme)
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346 if (bmsr & BMSR_ANCOMP)
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
353 jme_set_phyfifoa(struct jme_adapter *jme)
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
359 jme_set_phyfifob(struct jme_adapter *jme)
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
365 jme_check_link(struct net_device *netdev, int testonly)
367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
375 phylink = jme_linkstat_from_phy(jme);
377 phylink = jread32(jme, JME_PHY_LINK);
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
385 phylink = PHY_LINK_UP;
387 bmcr = jme_mdio_read(jme->dev,
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
401 strcat(linkmsg, "Forced: ");
404 * Keep polling for speed/duplex resolve complete
406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
412 phylink = jme_linkstat_from_phy(jme);
414 phylink = jread32(jme, JME_PHY_LINK);
418 "Waiting speed resolve timeout.\n");
420 strcat(linkmsg, "ANed: ");
423 if (jme->phylink == phylink) {
430 jme->phylink = phylink;
432 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
433 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
435 switch (phylink & PHY_LINK_SPEED_MASK) {
436 case PHY_LINK_SPEED_10M:
437 ghc |= GHC_SPEED_10M |
438 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
439 strcat(linkmsg, "10 Mbps, ");
441 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M |
443 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
444 strcat(linkmsg, "100 Mbps, ");
446 case PHY_LINK_SPEED_1000M:
447 ghc |= GHC_SPEED_1000M |
448 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
449 strcat(linkmsg, "1000 Mbps, ");
455 if (phylink & PHY_LINK_DUPLEX) {
456 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
459 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
463 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
464 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
466 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
469 gpreg1 = GPREG1_DEFAULT;
470 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
471 if (!(phylink & PHY_LINK_DUPLEX))
472 gpreg1 |= GPREG1_HALFMODEPATCH;
473 switch (phylink & PHY_LINK_SPEED_MASK) {
474 case PHY_LINK_SPEED_10M:
475 jme_set_phyfifoa(jme);
476 gpreg1 |= GPREG1_RSSPATCH;
478 case PHY_LINK_SPEED_100M:
479 jme_set_phyfifob(jme);
480 gpreg1 |= GPREG1_RSSPATCH;
482 case PHY_LINK_SPEED_1000M:
483 jme_set_phyfifoa(jme);
490 jwrite32(jme, JME_GPREG1, gpreg1);
491 jwrite32(jme, JME_GHC, ghc);
494 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
497 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
500 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev);
506 msg_link(jme, "Link is down.\n");
508 netif_carrier_off(netdev);
516 jme_setup_tx_resources(struct jme_adapter *jme)
518 struct jme_ring *txring = &(jme->txring[0]);
520 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
521 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
525 if (!txring->alloc) {
527 txring->dmaalloc = 0;
535 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
537 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
538 txring->next_to_use = 0;
539 atomic_set(&txring->next_to_clean, 0);
540 atomic_set(&txring->nr_free, jme->tx_ring_size);
543 * Initialize Transmit Descriptors
545 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
546 memset(txring->bufinf, 0,
547 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
553 jme_free_tx_resources(struct jme_adapter *jme)
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi = txring->bufinf;
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
563 dev_kfree_skb(txbi->skb);
569 txbi->start_xmit = 0;
572 dma_free_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
577 txring->alloc = NULL;
579 txring->dmaalloc = 0;
582 txring->next_to_use = 0;
583 atomic_set(&txring->next_to_clean, 0);
584 atomic_set(&txring->nr_free, 0);
589 jme_enable_tx_engine(struct jme_adapter *jme)
594 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
598 * Setup TX Queue 0 DMA Bass Address
600 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
601 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
602 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 * Setup TX Descptor Count
607 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
613 jwrite32(jme, JME_TXCS, jme->reg_txcs |
620 jme_restart_tx_engine(struct jme_adapter *jme)
625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
631 jme_disable_tx_engine(struct jme_adapter *jme)
639 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
642 val = jread32(jme, JME_TXCS);
643 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
645 val = jread32(jme, JME_TXCS);
650 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
654 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
656 struct jme_ring *rxring = jme->rxring;
657 register struct rxdesc *rxdesc = rxring->desc;
658 struct jme_buffer_info *rxbi = rxring->bufinf;
664 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
665 rxdesc->desc1.bufaddrl = cpu_to_le32(
666 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
667 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
668 if (jme->dev->features & NETIF_F_HIGHDMA)
669 rxdesc->desc1.flags = RXFLAG_64BIT;
671 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
675 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
677 struct jme_ring *rxring = &(jme->rxring[0]);
678 struct jme_buffer_info *rxbi = rxring->bufinf + i;
681 skb = netdev_alloc_skb(jme->dev,
682 jme->dev->mtu + RX_EXTRA_LEN);
685 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
690 rxbi->len = skb_tailroom(skb);
691 rxbi->mapping = pci_map_page(jme->pdev,
692 virt_to_page(skb->data),
693 offset_in_page(skb->data),
701 jme_free_rx_buf(struct jme_adapter *jme, int i)
703 struct jme_ring *rxring = &(jme->rxring[0]);
704 struct jme_buffer_info *rxbi = rxring->bufinf;
708 pci_unmap_page(jme->pdev,
712 dev_kfree_skb(rxbi->skb);
720 jme_free_rx_resources(struct jme_adapter *jme)
723 struct jme_ring *rxring = &(jme->rxring[0]);
726 for (i = 0 ; i < jme->rx_ring_size ; ++i)
727 jme_free_rx_buf(jme, i);
729 dma_free_coherent(&(jme->pdev->dev),
730 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
733 rxring->alloc = NULL;
735 rxring->dmaalloc = 0;
738 rxring->next_to_use = 0;
739 atomic_set(&rxring->next_to_clean, 0);
743 jme_setup_rx_resources(struct jme_adapter *jme)
746 struct jme_ring *rxring = &(jme->rxring[0]);
748 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
749 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
752 if (!rxring->alloc) {
754 rxring->dmaalloc = 0;
762 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
764 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
765 rxring->next_to_use = 0;
766 atomic_set(&rxring->next_to_clean, 0);
769 * Initiallize Receive Descriptors
771 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
772 if (unlikely(jme_make_new_rx_buf(jme, i))) {
773 jme_free_rx_resources(jme);
777 jme_set_clean_rxdesc(jme, i);
784 jme_enable_rx_engine(struct jme_adapter *jme)
789 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
794 * Setup RX DMA Bass Address
796 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
797 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
798 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
801 * Setup RX Descriptor Count
803 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
806 * Setup Unicast Filter
808 jme_set_multi(jme->dev);
814 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
821 jme_restart_rx_engine(struct jme_adapter *jme)
826 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
833 jme_disable_rx_engine(struct jme_adapter *jme)
841 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
844 val = jread32(jme, JME_RXCS);
845 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
847 val = jread32(jme, JME_RXCS);
852 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
857 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
859 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
862 if (unlikely(!(flags & RXWBFLAG_MF) &&
863 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
864 msg_rx_err(jme, "TCP Checksum error.\n");
868 if (unlikely(!(flags & RXWBFLAG_MF) &&
869 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
870 msg_rx_err(jme, "UDP Checksum error.\n");
874 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
875 msg_rx_err(jme, "IPv4 Checksum error.\n");
886 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
888 struct jme_ring *rxring = &(jme->rxring[0]);
889 struct rxdesc *rxdesc = rxring->desc;
890 struct jme_buffer_info *rxbi = rxring->bufinf;
898 pci_dma_sync_single_for_cpu(jme->pdev,
903 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
904 pci_dma_sync_single_for_device(jme->pdev,
909 ++(NET_STAT(jme).rx_dropped);
911 framesize = le16_to_cpu(rxdesc->descwb.framesize)
914 skb_reserve(skb, RX_PREPAD_SIZE);
915 skb_put(skb, framesize);
916 skb->protocol = eth_type_trans(skb, jme->dev);
918 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
919 skb->ip_summed = CHECKSUM_UNNECESSARY;
921 skb->ip_summed = CHECKSUM_NONE;
923 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
925 jme->jme_vlan_rx(skb, jme->vlgrp,
926 le16_to_cpu(rxdesc->descwb.vlan));
927 NET_STAT(jme).rx_bytes += 4;
933 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
934 cpu_to_le16(RXWBFLAG_DEST_MUL))
935 ++(NET_STAT(jme).multicast);
937 NET_STAT(jme).rx_bytes += framesize;
938 ++(NET_STAT(jme).rx_packets);
941 jme_set_clean_rxdesc(jme, idx);
946 jme_process_receive(struct jme_adapter *jme, int limit)
948 struct jme_ring *rxring = &(jme->rxring[0]);
949 struct rxdesc *rxdesc = rxring->desc;
950 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
952 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
955 if (unlikely(atomic_read(&jme->link_changing) != 1))
958 if (unlikely(!netif_carrier_ok(jme->dev)))
961 i = atomic_read(&rxring->next_to_clean);
962 while (limit-- > 0) {
963 rxdesc = rxring->desc;
966 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
967 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
970 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
972 if (unlikely(desccnt > 1 ||
973 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
975 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
976 ++(NET_STAT(jme).rx_crc_errors);
977 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
978 ++(NET_STAT(jme).rx_fifo_errors);
980 ++(NET_STAT(jme).rx_errors);
983 limit -= desccnt - 1;
985 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
986 jme_set_clean_rxdesc(jme, j);
987 j = (j + 1) & (mask);
991 jme_alloc_and_feed_skb(jme, i);
994 i = (i + desccnt) & (mask);
998 atomic_set(&rxring->next_to_clean, i);
1001 atomic_inc(&jme->rx_cleaning);
1003 return limit > 0 ? limit : 0;
1008 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1010 if (likely(atmp == dpi->cur)) {
1015 if (dpi->attempt == atmp) {
1018 dpi->attempt = atmp;
1025 jme_dynamic_pcc(struct jme_adapter *jme)
1027 register struct dynpcc_info *dpi = &(jme->dpi);
1029 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1030 jme_attempt_pcc(dpi, PCC_P3);
1031 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1032 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1033 jme_attempt_pcc(dpi, PCC_P2);
1035 jme_attempt_pcc(dpi, PCC_P1);
1037 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1038 if (dpi->attempt < dpi->cur)
1039 tasklet_schedule(&jme->rxclean_task);
1040 jme_set_rx_pcc(jme, dpi->attempt);
1041 dpi->cur = dpi->attempt;
1047 jme_start_pcc_timer(struct jme_adapter *jme)
1049 struct dynpcc_info *dpi = &(jme->dpi);
1050 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1051 dpi->last_pkts = NET_STAT(jme).rx_packets;
1053 jwrite32(jme, JME_TMCSR,
1054 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1058 jme_stop_pcc_timer(struct jme_adapter *jme)
1060 jwrite32(jme, JME_TMCSR, 0);
1064 jme_shutdown_nic(struct jme_adapter *jme)
1068 phylink = jme_linkstat_from_phy(jme);
1070 if (!(phylink & PHY_LINK_UP)) {
1072 * Disable all interrupt before issue timer
1075 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1080 jme_pcc_tasklet(unsigned long arg)
1082 struct jme_adapter *jme = (struct jme_adapter *)arg;
1083 struct net_device *netdev = jme->dev;
1085 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1086 jme_shutdown_nic(jme);
1090 if (unlikely(!netif_carrier_ok(netdev) ||
1091 (atomic_read(&jme->link_changing) != 1)
1093 jme_stop_pcc_timer(jme);
1097 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1098 jme_dynamic_pcc(jme);
1100 jme_start_pcc_timer(jme);
1104 jme_polling_mode(struct jme_adapter *jme)
1106 jme_set_rx_pcc(jme, PCC_OFF);
1110 jme_interrupt_mode(struct jme_adapter *jme)
1112 jme_set_rx_pcc(jme, PCC_P1);
1116 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1119 apmc = jread32(jme, JME_APMC);
1120 return apmc & JME_APMC_PSEUDO_HP_EN;
1124 jme_start_shutdown_timer(struct jme_adapter *jme)
1128 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1129 apmc &= ~JME_APMC_EPIEN_CTRL;
1131 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1134 jwrite32f(jme, JME_APMC, apmc);
1136 jwrite32f(jme, JME_TIMER2, 0);
1137 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1138 jwrite32(jme, JME_TMCSR,
1139 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1143 jme_stop_shutdown_timer(struct jme_adapter *jme)
1147 jwrite32f(jme, JME_TMCSR, 0);
1148 jwrite32f(jme, JME_TIMER2, 0);
1149 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1151 apmc = jread32(jme, JME_APMC);
1152 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1153 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1155 jwrite32f(jme, JME_APMC, apmc);
1159 jme_link_change_tasklet(unsigned long arg)
1161 struct jme_adapter *jme = (struct jme_adapter *)arg;
1162 struct net_device *netdev = jme->dev;
1165 while (!atomic_dec_and_test(&jme->link_changing)) {
1166 atomic_inc(&jme->link_changing);
1167 msg_intr(jme, "Get link change lock failed.\n");
1168 while (atomic_read(&jme->link_changing) != 1)
1169 msg_intr(jme, "Waiting link change lock.\n");
1172 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1175 jme->old_mtu = netdev->mtu;
1176 netif_stop_queue(netdev);
1177 if (jme_pseudo_hotplug_enabled(jme))
1178 jme_stop_shutdown_timer(jme);
1180 jme_stop_pcc_timer(jme);
1181 tasklet_disable(&jme->txclean_task);
1182 tasklet_disable(&jme->rxclean_task);
1183 tasklet_disable(&jme->rxempty_task);
1185 if (netif_carrier_ok(netdev)) {
1186 jme_reset_ghc_speed(jme);
1187 jme_disable_rx_engine(jme);
1188 jme_disable_tx_engine(jme);
1189 jme_reset_mac_processor(jme);
1190 jme_free_rx_resources(jme);
1191 jme_free_tx_resources(jme);
1193 if (test_bit(JME_FLAG_POLL, &jme->flags))
1194 jme_polling_mode(jme);
1196 netif_carrier_off(netdev);
1199 jme_check_link(netdev, 0);
1200 if (netif_carrier_ok(netdev)) {
1201 rc = jme_setup_rx_resources(jme);
1203 jeprintk(jme->pdev, "Allocating resources for RX error"
1204 ", Device STOPPED!\n");
1205 goto out_enable_tasklet;
1208 rc = jme_setup_tx_resources(jme);
1210 jeprintk(jme->pdev, "Allocating resources for TX error"
1211 ", Device STOPPED!\n");
1212 goto err_out_free_rx_resources;
1215 jme_enable_rx_engine(jme);
1216 jme_enable_tx_engine(jme);
1218 netif_start_queue(netdev);
1220 if (test_bit(JME_FLAG_POLL, &jme->flags))
1221 jme_interrupt_mode(jme);
1223 jme_start_pcc_timer(jme);
1224 } else if (jme_pseudo_hotplug_enabled(jme)) {
1225 jme_start_shutdown_timer(jme);
1228 goto out_enable_tasklet;
1230 err_out_free_rx_resources:
1231 jme_free_rx_resources(jme);
1233 tasklet_enable(&jme->txclean_task);
1234 tasklet_hi_enable(&jme->rxclean_task);
1235 tasklet_hi_enable(&jme->rxempty_task);
1237 atomic_inc(&jme->link_changing);
1241 jme_rx_clean_tasklet(unsigned long arg)
1243 struct jme_adapter *jme = (struct jme_adapter *)arg;
1244 struct dynpcc_info *dpi = &(jme->dpi);
1246 jme_process_receive(jme, jme->rx_ring_size);
1252 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1254 struct jme_adapter *jme = jme_napi_priv(holder);
1258 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1260 while (atomic_read(&jme->rx_empty) > 0) {
1261 atomic_dec(&jme->rx_empty);
1262 ++(NET_STAT(jme).rx_dropped);
1263 jme_restart_rx_engine(jme);
1265 atomic_inc(&jme->rx_empty);
1268 JME_RX_COMPLETE(netdev, holder);
1269 jme_interrupt_mode(jme);
1272 JME_NAPI_WEIGHT_SET(budget, rest);
1273 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1277 jme_rx_empty_tasklet(unsigned long arg)
1279 struct jme_adapter *jme = (struct jme_adapter *)arg;
1281 if (unlikely(atomic_read(&jme->link_changing) != 1))
1284 if (unlikely(!netif_carrier_ok(jme->dev)))
1287 msg_rx_status(jme, "RX Queue Full!\n");
1289 jme_rx_clean_tasklet(arg);
1291 while (atomic_read(&jme->rx_empty) > 0) {
1292 atomic_dec(&jme->rx_empty);
1293 ++(NET_STAT(jme).rx_dropped);
1294 jme_restart_rx_engine(jme);
1296 atomic_inc(&jme->rx_empty);
1300 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1302 struct jme_ring *txring = jme->txring;
1305 if (unlikely(netif_queue_stopped(jme->dev) &&
1306 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1307 msg_tx_done(jme, "TX Queue Waked.\n");
1308 netif_wake_queue(jme->dev);
1314 jme_tx_clean_tasklet(unsigned long arg)
1316 struct jme_adapter *jme = (struct jme_adapter *)arg;
1317 struct jme_ring *txring = &(jme->txring[0]);
1318 struct txdesc *txdesc = txring->desc;
1319 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1320 int i, j, cnt = 0, max, err, mask;
1322 tx_dbg(jme, "Into txclean.\n");
1324 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1327 if (unlikely(atomic_read(&jme->link_changing) != 1))
1330 if (unlikely(!netif_carrier_ok(jme->dev)))
1333 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1334 mask = jme->tx_ring_mask;
1336 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1340 if (likely(ctxbi->skb &&
1341 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1343 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1344 i, ctxbi->nr_desc, jiffies);
1346 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1348 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1349 ttxbi = txbi + ((i + j) & (mask));
1350 txdesc[(i + j) & (mask)].dw[0] = 0;
1352 pci_unmap_page(jme->pdev,
1361 dev_kfree_skb(ctxbi->skb);
1363 cnt += ctxbi->nr_desc;
1365 if (unlikely(err)) {
1366 ++(NET_STAT(jme).tx_carrier_errors);
1368 ++(NET_STAT(jme).tx_packets);
1369 NET_STAT(jme).tx_bytes += ctxbi->len;
1374 ctxbi->start_xmit = 0;
1380 i = (i + ctxbi->nr_desc) & mask;
1385 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1386 atomic_set(&txring->next_to_clean, i);
1387 atomic_add(cnt, &txring->nr_free);
1389 jme_wake_queue_if_stopped(jme);
1392 atomic_inc(&jme->tx_cleaning);
1396 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1401 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1403 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1405 * Link change event is critical
1406 * all other events are ignored
1408 jwrite32(jme, JME_IEVE, intrstat);
1409 tasklet_schedule(&jme->linkch_task);
1413 if (intrstat & INTR_TMINTR) {
1414 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1415 tasklet_schedule(&jme->pcc_task);
1418 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1419 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1420 tasklet_schedule(&jme->txclean_task);
1423 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1424 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1430 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1431 if (intrstat & INTR_RX0EMP)
1432 atomic_inc(&jme->rx_empty);
1434 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1435 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1436 jme_polling_mode(jme);
1437 JME_RX_SCHEDULE(jme);
1441 if (intrstat & INTR_RX0EMP) {
1442 atomic_inc(&jme->rx_empty);
1443 tasklet_hi_schedule(&jme->rxempty_task);
1444 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1445 tasklet_hi_schedule(&jme->rxclean_task);
1451 * Re-enable interrupt
1453 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1456 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1458 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1461 jme_intr(int irq, void *dev_id)
1464 struct net_device *netdev = dev_id;
1465 struct jme_adapter *jme = netdev_priv(netdev);
1468 intrstat = jread32(jme, JME_IEVE);
1471 * Check if it's really an interrupt for us
1473 if (unlikely((intrstat & INTR_ENABLE) == 0))
1477 * Check if the device still exist
1479 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1482 jme_intr_msi(jme, intrstat);
1487 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1489 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1492 jme_msi(int irq, void *dev_id)
1495 struct net_device *netdev = dev_id;
1496 struct jme_adapter *jme = netdev_priv(netdev);
1499 pci_dma_sync_single_for_cpu(jme->pdev,
1501 sizeof(u32) * SHADOW_REG_NR,
1502 PCI_DMA_FROMDEVICE);
1503 intrstat = jme->shadow_regs[SHADOW_IEVE];
1504 jme->shadow_regs[SHADOW_IEVE] = 0;
1506 jme_intr_msi(jme, intrstat);
1512 jme_reset_link(struct jme_adapter *jme)
1514 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1518 jme_restart_an(struct jme_adapter *jme)
1522 spin_lock_bh(&jme->phy_lock);
1523 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1524 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1525 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1526 spin_unlock_bh(&jme->phy_lock);
1530 jme_request_irq(struct jme_adapter *jme)
1533 struct net_device *netdev = jme->dev;
1534 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1535 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1536 int irq_flags = SA_SHIRQ;
1538 irq_handler_t handler = jme_intr;
1539 int irq_flags = IRQF_SHARED;
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1552 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
1561 netdev->irq = jme->pdev->irq;
1568 jme_free_irq(struct jme_adapter *jme)
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
1574 jme->dev->irq = jme->pdev->irq;
1579 jme_open(struct net_device *netdev)
1581 struct jme_adapter *jme = netdev_priv(netdev);
1585 JME_NAPI_ENABLE(jme);
1587 tasklet_enable(&jme->txclean_task);
1588 tasklet_hi_enable(&jme->rxclean_task);
1589 tasklet_hi_enable(&jme->rxempty_task);
1591 rc = jme_request_irq(jme);
1595 jme_enable_shadow(jme);
1598 if (test_bit(JME_FLAG_SSET, &jme->flags))
1599 jme_set_settings(netdev, &jme->old_ecmd);
1601 jme_reset_phy_processor(jme);
1603 jme_reset_link(jme);
1608 netif_stop_queue(netdev);
1609 netif_carrier_off(netdev);
1615 jme_set_100m_half(struct jme_adapter *jme)
1619 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1620 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1621 BMCR_SPEED1000 | BMCR_FULLDPLX);
1622 tmp |= BMCR_SPEED100;
1625 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1628 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1630 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1633 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1635 jme_wait_link(struct jme_adapter *jme)
1637 u32 phylink, to = JME_WAIT_LINK_TIME;
1640 phylink = jme_linkstat_from_phy(jme);
1641 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1643 phylink = jme_linkstat_from_phy(jme);
1649 jme_phy_off(struct jme_adapter *jme)
1651 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1655 jme_close(struct net_device *netdev)
1657 struct jme_adapter *jme = netdev_priv(netdev);
1659 netif_stop_queue(netdev);
1660 netif_carrier_off(netdev);
1663 jme_disable_shadow(jme);
1666 JME_NAPI_DISABLE(jme);
1668 tasklet_kill(&jme->linkch_task);
1669 tasklet_kill(&jme->txclean_task);
1670 tasklet_kill(&jme->rxclean_task);
1671 tasklet_kill(&jme->rxempty_task);
1673 jme_reset_ghc_speed(jme);
1674 jme_disable_rx_engine(jme);
1675 jme_disable_tx_engine(jme);
1676 jme_reset_mac_processor(jme);
1677 jme_free_rx_resources(jme);
1678 jme_free_tx_resources(jme);
1686 jme_alloc_txdesc(struct jme_adapter *jme,
1687 struct sk_buff *skb)
1689 struct jme_ring *txring = jme->txring;
1690 int idx, nr_alloc, mask = jme->tx_ring_mask;
1692 idx = txring->next_to_use;
1693 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1695 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1698 atomic_sub(nr_alloc, &txring->nr_free);
1700 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1706 jme_fill_tx_map(struct pci_dev *pdev,
1707 struct txdesc *txdesc,
1708 struct jme_buffer_info *txbi,
1716 dmaaddr = pci_map_page(pdev,
1722 pci_dma_sync_single_for_device(pdev,
1729 txdesc->desc2.flags = TXFLAG_OWN;
1730 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1731 txdesc->desc2.datalen = cpu_to_le16(len);
1732 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1733 txdesc->desc2.bufaddrl = cpu_to_le32(
1734 (__u64)dmaaddr & 0xFFFFFFFFUL);
1736 txbi->mapping = dmaaddr;
1741 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1743 struct jme_ring *txring = jme->txring;
1744 struct txdesc *txdesc = txring->desc, *ctxdesc;
1745 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1746 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1747 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1748 int mask = jme->tx_ring_mask;
1749 struct skb_frag_struct *frag;
1752 for (i = 0 ; i < nr_frags ; ++i) {
1753 frag = &skb_shinfo(skb)->frags[i];
1754 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1755 ctxbi = txbi + ((idx + i + 2) & (mask));
1757 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1758 frag->page_offset, frag->size, hidma);
1761 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1762 ctxdesc = txdesc + ((idx + 1) & (mask));
1763 ctxbi = txbi + ((idx + 1) & (mask));
1764 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1765 offset_in_page(skb->data), len, hidma);
1770 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1773 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)
1774 skb_shinfo(skb)->tso_size
1776 skb_shinfo(skb)->gso_size
1778 && skb_header_cloned(skb) &&
1779 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1788 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1790 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,16)
1791 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1793 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1796 *flags |= TXFLAG_LSEN;
1798 if (skb->protocol == htons(ETH_P_IP)) {
1799 struct iphdr *iph = ip_hdr(skb);
1802 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1807 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1809 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1822 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1824 #ifdef CHECKSUM_PARTIAL
1825 if (skb->ip_summed == CHECKSUM_PARTIAL)
1827 if (skb->ip_summed == CHECKSUM_HW)
1832 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1833 if (skb->protocol == htons(ETH_P_IP))
1834 ip_proto = ip_hdr(skb)->protocol;
1835 else if (skb->protocol == htons(ETH_P_IPV6))
1836 ip_proto = ipv6_hdr(skb)->nexthdr;
1840 switch (skb->protocol) {
1841 case htons(ETH_P_IP):
1842 ip_proto = ip_hdr(skb)->protocol;
1844 case htons(ETH_P_IPV6):
1845 ip_proto = ipv6_hdr(skb)->nexthdr;
1855 *flags |= TXFLAG_TCPCS;
1858 *flags |= TXFLAG_UDPCS;
1861 msg_tx_err(jme, "Error upper layer protocol.\n");
1868 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1870 if (vlan_tx_tag_present(skb)) {
1871 *flags |= TXFLAG_TAGON;
1872 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1877 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1879 struct jme_ring *txring = jme->txring;
1880 struct txdesc *txdesc;
1881 struct jme_buffer_info *txbi;
1884 txdesc = (struct txdesc *)txring->desc + idx;
1885 txbi = txring->bufinf + idx;
1891 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1893 * Set OWN bit at final.
1894 * When kernel transmit faster than NIC.
1895 * And NIC trying to send this descriptor before we tell
1896 * it to start sending this TX queue.
1897 * Other fields are already filled correctly.
1900 flags = TXFLAG_OWN | TXFLAG_INT;
1902 * Set checksum flags while not tso
1904 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1905 jme_tx_csum(jme, skb, &flags);
1906 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1907 jme_map_tx_skb(jme, skb, idx);
1908 txdesc->desc1.flags = flags;
1910 * Set tx buffer info after telling NIC to send
1911 * For better tx_clean timing
1914 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1916 txbi->len = skb->len;
1917 txbi->start_xmit = jiffies;
1918 if (!txbi->start_xmit)
1919 txbi->start_xmit = (0UL-1);
1925 jme_stop_queue_if_full(struct jme_adapter *jme)
1927 struct jme_ring *txring = jme->txring;
1928 struct jme_buffer_info *txbi = txring->bufinf;
1929 int idx = atomic_read(&txring->next_to_clean);
1934 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1935 netif_stop_queue(jme->dev);
1936 msg_tx_queued(jme, "TX Queue Paused.\n");
1938 if (atomic_read(&txring->nr_free)
1939 >= (jme->tx_wake_threshold)) {
1940 netif_wake_queue(jme->dev);
1941 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1945 if (unlikely(txbi->start_xmit &&
1946 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1948 netif_stop_queue(jme->dev);
1949 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1954 * This function is already protected by netif_tx_lock()
1958 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1960 struct jme_adapter *jme = netdev_priv(netdev);
1963 if (unlikely(jme_expand_header(jme, skb))) {
1964 ++(NET_STAT(jme).tx_dropped);
1965 return NETDEV_TX_OK;
1968 idx = jme_alloc_txdesc(jme, skb);
1970 if (unlikely(idx < 0)) {
1971 netif_stop_queue(netdev);
1972 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1974 return NETDEV_TX_BUSY;
1977 jme_fill_tx_desc(jme, skb, idx);
1979 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1980 TXCS_SELECT_QUEUE0 |
1983 netdev->trans_start = jiffies;
1985 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1986 skb_shinfo(skb)->nr_frags + 2,
1988 jme_stop_queue_if_full(jme);
1990 return NETDEV_TX_OK;
1994 jme_set_macaddr(struct net_device *netdev, void *p)
1996 struct jme_adapter *jme = netdev_priv(netdev);
1997 struct sockaddr *addr = p;
2000 if (netif_running(netdev))
2003 spin_lock_bh(&jme->macaddr_lock);
2004 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2006 val = (addr->sa_data[3] & 0xff) << 24 |
2007 (addr->sa_data[2] & 0xff) << 16 |
2008 (addr->sa_data[1] & 0xff) << 8 |
2009 (addr->sa_data[0] & 0xff);
2010 jwrite32(jme, JME_RXUMA_LO, val);
2011 val = (addr->sa_data[5] & 0xff) << 8 |
2012 (addr->sa_data[4] & 0xff);
2013 jwrite32(jme, JME_RXUMA_HI, val);
2014 spin_unlock_bh(&jme->macaddr_lock);
2020 jme_set_multi(struct net_device *netdev)
2022 struct jme_adapter *jme = netdev_priv(netdev);
2023 u32 mc_hash[2] = {};
2026 spin_lock_bh(&jme->rxmcs_lock);
2028 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2030 if (netdev->flags & IFF_PROMISC) {
2031 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2032 } else if (netdev->flags & IFF_ALLMULTI) {
2033 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2034 } else if (netdev->flags & IFF_MULTICAST) {
2035 struct dev_mc_list *mclist;
2038 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2039 for (i = 0, mclist = netdev->mc_list;
2040 mclist && i < netdev->mc_count;
2041 ++i, mclist = mclist->next) {
2043 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2044 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2047 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2048 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2052 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2054 spin_unlock_bh(&jme->rxmcs_lock);
2058 jme_change_mtu(struct net_device *netdev, int new_mtu)
2060 struct jme_adapter *jme = netdev_priv(netdev);
2062 if (new_mtu == jme->old_mtu)
2065 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2066 ((new_mtu) < IPV6_MIN_MTU))
2069 if (new_mtu > 4000) {
2070 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2071 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2072 jme_restart_rx_engine(jme);
2074 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2075 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2076 jme_restart_rx_engine(jme);
2079 if (new_mtu > 1900) {
2080 netdev->features &= ~(NETIF_F_HW_CSUM |
2087 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2088 netdev->features |= NETIF_F_HW_CSUM;
2089 if (test_bit(JME_FLAG_TSO, &jme->flags))
2090 netdev->features |= NETIF_F_TSO
2097 netdev->mtu = new_mtu;
2098 jme_reset_link(jme);
2104 jme_tx_timeout(struct net_device *netdev)
2106 struct jme_adapter *jme = netdev_priv(netdev);
2109 jme_reset_phy_processor(jme);
2110 if (test_bit(JME_FLAG_SSET, &jme->flags))
2111 jme_set_settings(netdev, &jme->old_ecmd);
2114 * Force to Reset the link again
2116 jme_reset_link(jme);
2120 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2122 struct jme_adapter *jme = netdev_priv(netdev);
2128 jme_get_drvinfo(struct net_device *netdev,
2129 struct ethtool_drvinfo *info)
2131 struct jme_adapter *jme = netdev_priv(netdev);
2133 strcpy(info->driver, DRV_NAME);
2134 strcpy(info->version, DRV_VERSION);
2135 strcpy(info->bus_info, pci_name(jme->pdev));
2139 jme_get_regs_len(struct net_device *netdev)
2145 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2149 for (i = 0 ; i < len ; i += 4)
2150 p[i >> 2] = jread32(jme, reg + i);
2154 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2157 u16 *p16 = (u16 *)p;
2159 for (i = 0 ; i < reg_nr ; ++i)
2160 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2164 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2166 struct jme_adapter *jme = netdev_priv(netdev);
2167 u32 *p32 = (u32 *)p;
2169 memset(p, 0xFF, JME_REG_LEN);
2172 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2175 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2178 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2181 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2184 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2188 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2190 struct jme_adapter *jme = netdev_priv(netdev);
2192 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2193 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2195 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2196 ecmd->use_adaptive_rx_coalesce = false;
2197 ecmd->rx_coalesce_usecs = 0;
2198 ecmd->rx_max_coalesced_frames = 0;
2202 ecmd->use_adaptive_rx_coalesce = true;
2204 switch (jme->dpi.cur) {
2206 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2207 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2210 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2211 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2214 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2215 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2225 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2227 struct jme_adapter *jme = netdev_priv(netdev);
2228 struct dynpcc_info *dpi = &(jme->dpi);
2230 if (netif_running(netdev))
2233 if (ecmd->use_adaptive_rx_coalesce
2234 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2235 clear_bit(JME_FLAG_POLL, &jme->flags);
2236 jme->jme_rx = netif_rx;
2237 jme->jme_vlan_rx = vlan_hwaccel_rx;
2239 dpi->attempt = PCC_P1;
2241 jme_set_rx_pcc(jme, PCC_P1);
2242 jme_interrupt_mode(jme);
2243 } else if (!(ecmd->use_adaptive_rx_coalesce)
2244 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2245 set_bit(JME_FLAG_POLL, &jme->flags);
2246 jme->jme_rx = netif_receive_skb;
2247 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2248 jme_interrupt_mode(jme);
2255 jme_get_pauseparam(struct net_device *netdev,
2256 struct ethtool_pauseparam *ecmd)
2258 struct jme_adapter *jme = netdev_priv(netdev);
2261 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2262 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2264 spin_lock_bh(&jme->phy_lock);
2265 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2266 spin_unlock_bh(&jme->phy_lock);
2269 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2273 jme_set_pauseparam(struct net_device *netdev,
2274 struct ethtool_pauseparam *ecmd)
2276 struct jme_adapter *jme = netdev_priv(netdev);
2279 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2280 (ecmd->tx_pause != 0)) {
2283 jme->reg_txpfc |= TXPFC_PF_EN;
2285 jme->reg_txpfc &= ~TXPFC_PF_EN;
2287 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2290 spin_lock_bh(&jme->rxmcs_lock);
2291 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2292 (ecmd->rx_pause != 0)) {
2295 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2297 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2299 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2301 spin_unlock_bh(&jme->rxmcs_lock);
2303 spin_lock_bh(&jme->phy_lock);
2304 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2305 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2306 (ecmd->autoneg != 0)) {
2309 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2311 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2313 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2314 MII_ADVERTISE, val);
2316 spin_unlock_bh(&jme->phy_lock);
2322 jme_get_wol(struct net_device *netdev,
2323 struct ethtool_wolinfo *wol)
2325 struct jme_adapter *jme = netdev_priv(netdev);
2327 wol->supported = WAKE_MAGIC | WAKE_PHY;
2331 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2332 wol->wolopts |= WAKE_PHY;
2334 if (jme->reg_pmcs & PMCS_MFEN)
2335 wol->wolopts |= WAKE_MAGIC;
2340 jme_set_wol(struct net_device *netdev,
2341 struct ethtool_wolinfo *wol)
2343 struct jme_adapter *jme = netdev_priv(netdev);
2345 if (wol->wolopts & (WAKE_MAGICSECURE |
2354 if (wol->wolopts & WAKE_PHY)
2355 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2357 if (wol->wolopts & WAKE_MAGIC)
2358 jme->reg_pmcs |= PMCS_MFEN;
2360 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2366 jme_get_settings(struct net_device *netdev,
2367 struct ethtool_cmd *ecmd)
2369 struct jme_adapter *jme = netdev_priv(netdev);
2372 spin_lock_bh(&jme->phy_lock);
2373 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2374 spin_unlock_bh(&jme->phy_lock);
2379 jme_set_settings(struct net_device *netdev,
2380 struct ethtool_cmd *ecmd)
2382 struct jme_adapter *jme = netdev_priv(netdev);
2385 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2388 if (jme->mii_if.force_media &&
2389 ecmd->autoneg != AUTONEG_ENABLE &&
2390 (jme->mii_if.full_duplex != ecmd->duplex))
2393 spin_lock_bh(&jme->phy_lock);
2394 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2395 spin_unlock_bh(&jme->phy_lock);
2398 jme_reset_link(jme);
2401 set_bit(JME_FLAG_SSET, &jme->flags);
2402 jme->old_ecmd = *ecmd;
2409 jme_get_link(struct net_device *netdev)
2411 struct jme_adapter *jme = netdev_priv(netdev);
2412 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2416 jme_get_msglevel(struct net_device *netdev)
2418 struct jme_adapter *jme = netdev_priv(netdev);
2419 return jme->msg_enable;
2423 jme_set_msglevel(struct net_device *netdev, u32 value)
2425 struct jme_adapter *jme = netdev_priv(netdev);
2426 jme->msg_enable = value;
2430 jme_get_rx_csum(struct net_device *netdev)
2432 struct jme_adapter *jme = netdev_priv(netdev);
2433 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2437 jme_set_rx_csum(struct net_device *netdev, u32 on)
2439 struct jme_adapter *jme = netdev_priv(netdev);
2441 spin_lock_bh(&jme->rxmcs_lock);
2443 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2445 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2446 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2447 spin_unlock_bh(&jme->rxmcs_lock);
2453 jme_set_tx_csum(struct net_device *netdev, u32 on)
2455 struct jme_adapter *jme = netdev_priv(netdev);
2458 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2459 if (netdev->mtu <= 1900)
2460 netdev->features |= NETIF_F_HW_CSUM;
2462 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2463 netdev->features &= ~NETIF_F_HW_CSUM;
2470 jme_set_tso(struct net_device *netdev, u32 on)
2472 struct jme_adapter *jme = netdev_priv(netdev);
2475 set_bit(JME_FLAG_TSO, &jme->flags);
2476 if (netdev->mtu <= 1900)
2477 netdev->features |= NETIF_F_TSO
2483 clear_bit(JME_FLAG_TSO, &jme->flags);
2484 netdev->features &= ~(NETIF_F_TSO
2495 jme_nway_reset(struct net_device *netdev)
2497 struct jme_adapter *jme = netdev_priv(netdev);
2498 jme_restart_an(jme);
2503 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2508 val = jread32(jme, JME_SMBCSR);
2509 to = JME_SMB_BUSY_TIMEOUT;
2510 while ((val & SMBCSR_BUSY) && --to) {
2512 val = jread32(jme, JME_SMBCSR);
2515 msg_hw(jme, "SMB Bus Busy.\n");
2519 jwrite32(jme, JME_SMBINTF,
2520 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2521 SMBINTF_HWRWN_READ |
2524 val = jread32(jme, JME_SMBINTF);
2525 to = JME_SMB_BUSY_TIMEOUT;
2526 while ((val & SMBINTF_HWCMD) && --to) {
2528 val = jread32(jme, JME_SMBINTF);
2531 msg_hw(jme, "SMB Bus Busy.\n");
2535 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2539 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2544 val = jread32(jme, JME_SMBCSR);
2545 to = JME_SMB_BUSY_TIMEOUT;
2546 while ((val & SMBCSR_BUSY) && --to) {
2548 val = jread32(jme, JME_SMBCSR);
2551 msg_hw(jme, "SMB Bus Busy.\n");
2555 jwrite32(jme, JME_SMBINTF,
2556 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2557 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2558 SMBINTF_HWRWN_WRITE |
2561 val = jread32(jme, JME_SMBINTF);
2562 to = JME_SMB_BUSY_TIMEOUT;
2563 while ((val & SMBINTF_HWCMD) && --to) {
2565 val = jread32(jme, JME_SMBINTF);
2568 msg_hw(jme, "SMB Bus Busy.\n");
2576 jme_get_eeprom_len(struct net_device *netdev)
2578 struct jme_adapter *jme = netdev_priv(netdev);
2580 val = jread32(jme, JME_SMBCSR);
2581 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2585 jme_get_eeprom(struct net_device *netdev,
2586 struct ethtool_eeprom *eeprom, u8 *data)
2588 struct jme_adapter *jme = netdev_priv(netdev);
2589 int i, offset = eeprom->offset, len = eeprom->len;
2592 * ethtool will check the boundary for us
2594 eeprom->magic = JME_EEPROM_MAGIC;
2595 for (i = 0 ; i < len ; ++i)
2596 data[i] = jme_smb_read(jme, i + offset);
2602 jme_set_eeprom(struct net_device *netdev,
2603 struct ethtool_eeprom *eeprom, u8 *data)
2605 struct jme_adapter *jme = netdev_priv(netdev);
2606 int i, offset = eeprom->offset, len = eeprom->len;
2608 if (eeprom->magic != JME_EEPROM_MAGIC)
2612 * ethtool will check the boundary for us
2614 for (i = 0 ; i < len ; ++i)
2615 jme_smb_write(jme, i + offset, data[i]);
2620 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2621 static struct ethtool_ops jme_ethtool_ops = {
2623 static const struct ethtool_ops jme_ethtool_ops = {
2625 .get_drvinfo = jme_get_drvinfo,
2626 .get_regs_len = jme_get_regs_len,
2627 .get_regs = jme_get_regs,
2628 .get_coalesce = jme_get_coalesce,
2629 .set_coalesce = jme_set_coalesce,
2630 .get_pauseparam = jme_get_pauseparam,
2631 .set_pauseparam = jme_set_pauseparam,
2632 .get_wol = jme_get_wol,
2633 .set_wol = jme_set_wol,
2634 .get_settings = jme_get_settings,
2635 .set_settings = jme_set_settings,
2636 .get_link = jme_get_link,
2637 .get_msglevel = jme_get_msglevel,
2638 .set_msglevel = jme_set_msglevel,
2639 .get_rx_csum = jme_get_rx_csum,
2640 .set_rx_csum = jme_set_rx_csum,
2641 .set_tx_csum = jme_set_tx_csum,
2642 .set_tso = jme_set_tso,
2643 .set_sg = ethtool_op_set_sg,
2644 .nway_reset = jme_nway_reset,
2645 .get_eeprom_len = jme_get_eeprom_len,
2646 .get_eeprom = jme_get_eeprom,
2647 .set_eeprom = jme_set_eeprom,
2651 jme_pci_dma64(struct pci_dev *pdev)
2653 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2654 !pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2655 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2658 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2659 !pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2660 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2663 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2664 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2671 jme_phy_init(struct jme_adapter *jme)
2675 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2676 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2680 jme_check_hw_ver(struct jme_adapter *jme)
2684 chipmode = jread32(jme, JME_CHIPMODE);
2686 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2687 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2690 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2691 static const struct net_device_ops jme_netdev_ops = {
2692 .ndo_open = jme_open,
2693 .ndo_stop = jme_close,
2694 .ndo_validate_addr = eth_validate_addr,
2695 .ndo_start_xmit = jme_start_xmit,
2696 .ndo_set_mac_address = jme_set_macaddr,
2697 .ndo_set_multicast_list = jme_set_multi,
2698 .ndo_change_mtu = jme_change_mtu,
2699 .ndo_tx_timeout = jme_tx_timeout,
2700 .ndo_vlan_rx_register = jme_vlan_rx_register,
2704 static int __devinit
2705 jme_init_one(struct pci_dev *pdev,
2706 const struct pci_device_id *ent)
2708 int rc = 0, using_dac, i;
2709 struct net_device *netdev;
2710 struct jme_adapter *jme;
2715 * set up PCI device basics
2717 rc = pci_enable_device(pdev);
2719 jeprintk(pdev, "Cannot enable PCI device.\n");
2723 using_dac = jme_pci_dma64(pdev);
2724 if (using_dac < 0) {
2725 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2727 goto err_out_disable_pdev;
2730 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2731 jeprintk(pdev, "No PCI resource region found.\n");
2733 goto err_out_disable_pdev;
2736 rc = pci_request_regions(pdev, DRV_NAME);
2738 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2739 goto err_out_disable_pdev;
2742 pci_set_master(pdev);
2745 * alloc and init net device
2747 netdev = alloc_etherdev(sizeof(*jme));
2749 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2751 goto err_out_release_regions;
2753 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2754 netdev->netdev_ops = &jme_netdev_ops;
2756 netdev->open = jme_open;
2757 netdev->stop = jme_close;
2758 netdev->hard_start_xmit = jme_start_xmit;
2759 netdev->set_mac_address = jme_set_macaddr;
2760 netdev->set_multicast_list = jme_set_multi;
2761 netdev->change_mtu = jme_change_mtu;
2762 netdev->tx_timeout = jme_tx_timeout;
2763 netdev->vlan_rx_register = jme_vlan_rx_register;
2764 NETDEV_GET_STATS(netdev, &jme_get_stats);
2766 netdev->ethtool_ops = &jme_ethtool_ops;
2767 netdev->watchdog_timeo = TX_TIMEOUT;
2768 netdev->features = NETIF_F_HW_CSUM |
2774 NETIF_F_HW_VLAN_TX |
2777 netdev->features |= NETIF_F_HIGHDMA;
2779 SET_NETDEV_DEV(netdev, &pdev->dev);
2780 pci_set_drvdata(pdev, netdev);
2785 jme = netdev_priv(netdev);
2788 jme->jme_rx = netif_rx;
2789 jme->jme_vlan_rx = vlan_hwaccel_rx;
2790 jme->old_mtu = netdev->mtu = 1500;
2792 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2793 jme->tx_ring_size = 1 << 9;
2794 jme->tx_wake_threshold = 1 << 8;
2795 jme->rx_ring_size = 1 << 8;
2797 jme->tx_ring_size = 1 << 10;
2798 jme->tx_wake_threshold = 1 << 9;
2799 jme->rx_ring_size = 1 << 9;
2801 jme->tx_ring_mask = jme->tx_ring_size - 1;
2802 jme->rx_ring_mask = jme->rx_ring_size - 1;
2803 jme->msg_enable = JME_DEF_MSG_ENABLE;
2804 jme->regs = ioremap(pci_resource_start(pdev, 0),
2805 pci_resource_len(pdev, 0));
2807 jeprintk(pdev, "Mapping PCI resource region error.\n");
2809 goto err_out_free_netdev;
2811 jme->shadow_regs = pci_alloc_consistent(pdev,
2812 sizeof(u32) * SHADOW_REG_NR,
2813 &(jme->shadow_dma));
2814 if (!(jme->shadow_regs)) {
2815 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2821 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2822 jwrite32(jme, JME_APMC, apmc);
2823 } else if (force_pseudohp) {
2824 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2825 jwrite32(jme, JME_APMC, apmc);
2828 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2830 spin_lock_init(&jme->phy_lock);
2831 spin_lock_init(&jme->macaddr_lock);
2832 spin_lock_init(&jme->rxmcs_lock);
2834 atomic_set(&jme->link_changing, 1);
2835 atomic_set(&jme->rx_cleaning, 1);
2836 atomic_set(&jme->tx_cleaning, 1);
2837 atomic_set(&jme->rx_empty, 1);
2839 tasklet_init(&jme->pcc_task,
2841 (unsigned long) jme);
2842 tasklet_init(&jme->linkch_task,
2843 &jme_link_change_tasklet,
2844 (unsigned long) jme);
2845 tasklet_init(&jme->txclean_task,
2846 &jme_tx_clean_tasklet,
2847 (unsigned long) jme);
2848 tasklet_init(&jme->rxclean_task,
2849 &jme_rx_clean_tasklet,
2850 (unsigned long) jme);
2851 tasklet_init(&jme->rxempty_task,
2852 &jme_rx_empty_tasklet,
2853 (unsigned long) jme);
2854 tasklet_disable_nosync(&jme->txclean_task);
2855 tasklet_disable_nosync(&jme->rxclean_task);
2856 tasklet_disable_nosync(&jme->rxempty_task);
2857 jme->dpi.cur = PCC_P1;
2860 jme->reg_rxcs = RXCS_DEFAULT;
2861 jme->reg_rxmcs = RXMCS_DEFAULT;
2863 jme->reg_pmcs = PMCS_MFEN;
2864 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2865 set_bit(JME_FLAG_TSO, &jme->flags);
2868 * Get Max Read Req Size from PCI Config Space
2870 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2871 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2872 switch (jme->mrrs) {
2874 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2877 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2880 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2885 * Must check before reset_mac_processor
2887 jme_check_hw_ver(jme);
2888 jme->mii_if.dev = netdev;
2890 jme->mii_if.phy_id = 0;
2891 for (i = 1 ; i < 32 ; ++i) {
2892 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2893 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2894 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2895 jme->mii_if.phy_id = i;
2900 if (!jme->mii_if.phy_id) {
2902 jeprintk(pdev, "Can not find phy_id.\n");
2903 goto err_out_free_shadow;
2906 jme->reg_ghc |= GHC_LINK_POLL;
2908 jme->mii_if.phy_id = 1;
2910 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2911 jme->mii_if.supports_gmii = true;
2913 jme->mii_if.supports_gmii = false;
2914 jme->mii_if.mdio_read = jme_mdio_read;
2915 jme->mii_if.mdio_write = jme_mdio_write;
2918 jme_set_phyfifoa(jme);
2919 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2925 * Reset MAC processor and reload EEPROM for MAC Address
2927 jme_reset_mac_processor(jme);
2928 rc = jme_reload_eeprom(jme);
2931 "Reload eeprom for reading MAC Address error.\n");
2932 goto err_out_free_shadow;
2934 jme_load_macaddr(netdev);
2937 * Tell stack that we are not ready to work until open()
2939 netif_carrier_off(netdev);
2940 netif_stop_queue(netdev);
2945 rc = register_netdev(netdev);
2947 jeprintk(pdev, "Cannot register net device.\n");
2948 goto err_out_free_shadow;
2951 msg_probe(jme, "%s%s ver:%x rev:%x macaddr:%pM\n",
2952 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2953 "JMC250 Gigabit Ethernet" :
2954 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2955 "JMC260 Fast Ethernet" : "Unknown",
2956 (jme->fpgaver != 0) ? " (FPGA)" : "",
2957 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2958 jme->rev, netdev->dev_addr);
2962 err_out_free_shadow:
2963 pci_free_consistent(pdev,
2964 sizeof(u32) * SHADOW_REG_NR,
2969 err_out_free_netdev:
2970 pci_set_drvdata(pdev, NULL);
2971 free_netdev(netdev);
2972 err_out_release_regions:
2973 pci_release_regions(pdev);
2974 err_out_disable_pdev:
2975 pci_disable_device(pdev);
2980 static void __devexit
2981 jme_remove_one(struct pci_dev *pdev)
2983 struct net_device *netdev = pci_get_drvdata(pdev);
2984 struct jme_adapter *jme = netdev_priv(netdev);
2986 unregister_netdev(netdev);
2987 pci_free_consistent(pdev,
2988 sizeof(u32) * SHADOW_REG_NR,
2992 pci_set_drvdata(pdev, NULL);
2993 free_netdev(netdev);
2994 pci_release_regions(pdev);
2995 pci_disable_device(pdev);
3001 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3003 struct net_device *netdev = pci_get_drvdata(pdev);
3004 struct jme_adapter *jme = netdev_priv(netdev);
3006 atomic_dec(&jme->link_changing);
3008 netif_device_detach(netdev);
3009 netif_stop_queue(netdev);
3012 tasklet_disable(&jme->txclean_task);
3013 tasklet_disable(&jme->rxclean_task);
3014 tasklet_disable(&jme->rxempty_task);
3016 jme_disable_shadow(jme);
3018 if (netif_carrier_ok(netdev)) {
3019 if (test_bit(JME_FLAG_POLL, &jme->flags))
3020 jme_polling_mode(jme);
3022 jme_stop_pcc_timer(jme);
3023 jme_reset_ghc_speed(jme);
3024 jme_disable_rx_engine(jme);
3025 jme_disable_tx_engine(jme);
3026 jme_reset_mac_processor(jme);
3027 jme_free_rx_resources(jme);
3028 jme_free_tx_resources(jme);
3029 netif_carrier_off(netdev);
3033 tasklet_enable(&jme->txclean_task);
3034 tasklet_hi_enable(&jme->rxclean_task);
3035 tasklet_hi_enable(&jme->rxempty_task);
3037 pci_save_state(pdev);
3038 if (jme->reg_pmcs) {
3039 jme_set_100m_half(jme);
3041 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3044 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3046 pci_enable_wake(pdev, PCI_D3cold, true);
3050 pci_set_power_state(pdev, PCI_D3cold);
3056 jme_resume(struct pci_dev *pdev)
3058 struct net_device *netdev = pci_get_drvdata(pdev);
3059 struct jme_adapter *jme = netdev_priv(netdev);
3062 pci_restore_state(pdev);
3064 if (test_bit(JME_FLAG_SSET, &jme->flags))
3065 jme_set_settings(netdev, &jme->old_ecmd);
3067 jme_reset_phy_processor(jme);
3069 jme_enable_shadow(jme);
3071 netif_device_attach(netdev);
3073 atomic_inc(&jme->link_changing);
3075 jme_reset_link(jme);
3081 static struct pci_device_id jme_pci_tbl[] = {
3082 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3083 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3087 static struct pci_driver jme_driver = {
3089 .id_table = jme_pci_tbl,
3090 .probe = jme_init_one,
3091 .remove = __devexit_p(jme_remove_one),
3093 .suspend = jme_suspend,
3094 .resume = jme_resume,
3095 #endif /* CONFIG_PM */
3099 jme_init_module(void)
3101 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3102 "driver version %s\n", DRV_VERSION);
3103 return pci_register_driver(&jme_driver);
3107 jme_cleanup_module(void)
3109 pci_unregister_driver(&jme_driver);
3112 module_init(jme_init_module);
3113 module_exit(jme_cleanup_module);
3115 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3116 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3117 MODULE_LICENSE("GPL");
3118 MODULE_VERSION(DRV_VERSION);
3119 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);