2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
63 jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
66 pci_enable_wake(jme->pdev, PCI_D1, enable);
67 pci_enable_wake(jme->pdev, PCI_D2, enable);
68 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
69 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71 pci_pme_active(jme->pdev, enable);
76 jme_mdio_read(struct net_device *netdev, int phy, int reg)
78 struct jme_adapter *jme = netdev_priv(netdev);
79 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
82 jwrite32(jme, JME_SMI, SMI_OP_REQ |
87 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
89 val = jread32(jme, JME_SMI);
90 if ((val & SMI_OP_REQ) == 0)
95 pr_err("phy(%d) read timeout : %d\n", phy, reg);
102 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
106 jme_mdio_write(struct net_device *netdev,
107 int phy, int reg, int val)
109 struct jme_adapter *jme = netdev_priv(netdev);
112 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
113 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
114 smi_phy_addr(phy) | smi_reg_addr(reg));
117 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
119 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
124 pr_err("phy(%d) write timeout : %d\n", phy, reg);
128 jme_reset_phy_processor(struct jme_adapter *jme)
132 jme_mdio_write(jme->dev,
134 MII_ADVERTISE, ADVERTISE_ALL |
135 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
137 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
138 jme_mdio_write(jme->dev,
141 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
143 val = jme_mdio_read(jme->dev,
147 jme_mdio_write(jme->dev,
149 MII_BMCR, val | BMCR_RESET);
153 jme_setup_wakeup_frame(struct jme_adapter *jme,
154 const u32 *mask, u32 crc, int fnr)
161 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
163 jwrite32(jme, JME_WFODP, crc);
169 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
170 jwrite32(jme, JME_WFOI,
171 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
172 (fnr & WFOI_FRAME_SEL));
174 jwrite32(jme, JME_WFODP, mask[i]);
180 jme_mac_rxclk_off(struct jme_adapter *jme)
182 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
183 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
187 jme_mac_rxclk_on(struct jme_adapter *jme)
189 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
190 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
194 jme_mac_txclk_off(struct jme_adapter *jme)
196 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
197 jwrite32f(jme, JME_GHC, jme->reg_ghc);
201 jme_mac_txclk_on(struct jme_adapter *jme)
203 u32 speed = jme->reg_ghc & GHC_SPEED;
204 if (speed == GHC_SPEED_1000M)
205 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
207 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
208 jwrite32f(jme, JME_GHC, jme->reg_ghc);
212 jme_reset_ghc_speed(struct jme_adapter *jme)
214 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
215 jwrite32f(jme, JME_GHC, jme->reg_ghc);
219 jme_reset_250A2_workaround(struct jme_adapter *jme)
221 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
223 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
227 jme_assert_ghc_reset(struct jme_adapter *jme)
229 jme->reg_ghc |= GHC_SWRST;
230 jwrite32f(jme, JME_GHC, jme->reg_ghc);
234 jme_clear_ghc_reset(struct jme_adapter *jme)
236 jme->reg_ghc &= ~GHC_SWRST;
237 jwrite32f(jme, JME_GHC, jme->reg_ghc);
241 jme_reset_mac_processor(struct jme_adapter *jme)
243 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
244 u32 crc = 0xCDCDCDCD;
248 jme_reset_ghc_speed(jme);
249 jme_reset_250A2_workaround(jme);
251 jme_mac_rxclk_on(jme);
252 jme_mac_txclk_on(jme);
254 jme_assert_ghc_reset(jme);
256 jme_mac_rxclk_off(jme);
257 jme_mac_txclk_off(jme);
259 jme_clear_ghc_reset(jme);
261 jme_mac_rxclk_on(jme);
262 jme_mac_txclk_on(jme);
264 jme_mac_rxclk_off(jme);
265 jme_mac_txclk_off(jme);
267 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
268 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
269 jwrite32(jme, JME_RXQDC, 0x00000000);
270 jwrite32(jme, JME_RXNDA, 0x00000000);
271 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
272 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
273 jwrite32(jme, JME_TXQDC, 0x00000000);
274 jwrite32(jme, JME_TXNDA, 0x00000000);
276 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
277 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
278 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
279 jme_setup_wakeup_frame(jme, mask, crc, i);
281 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
283 gpreg0 = GPREG0_DEFAULT;
284 jwrite32(jme, JME_GPREG0, gpreg0);
288 jme_clear_pm(struct jme_adapter *jme)
290 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
294 jme_reload_eeprom(struct jme_adapter *jme)
299 val = jread32(jme, JME_SMBCSR);
301 if (val & SMBCSR_EEPROMD) {
303 jwrite32(jme, JME_SMBCSR, val);
304 val |= SMBCSR_RELOAD;
305 jwrite32(jme, JME_SMBCSR, val);
308 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
310 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
315 pr_err("eeprom reload timeout\n");
324 jme_load_macaddr(struct net_device *netdev)
326 struct jme_adapter *jme = netdev_priv(netdev);
327 unsigned char macaddr[6];
330 spin_lock_bh(&jme->macaddr_lock);
331 val = jread32(jme, JME_RXUMA_LO);
332 macaddr[0] = (val >> 0) & 0xFF;
333 macaddr[1] = (val >> 8) & 0xFF;
334 macaddr[2] = (val >> 16) & 0xFF;
335 macaddr[3] = (val >> 24) & 0xFF;
336 val = jread32(jme, JME_RXUMA_HI);
337 macaddr[4] = (val >> 0) & 0xFF;
338 macaddr[5] = (val >> 8) & 0xFF;
339 memcpy(netdev->dev_addr, macaddr, 6);
340 spin_unlock_bh(&jme->macaddr_lock);
344 jme_set_rx_pcc(struct jme_adapter *jme, int p)
348 jwrite32(jme, JME_PCCRX0,
349 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
350 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 jwrite32(jme, JME_PCCRX0,
354 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
355 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 jwrite32(jme, JME_PCCRX0,
359 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
360 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 jwrite32(jme, JME_PCCRX0,
364 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
365 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
372 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
373 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
377 jme_start_irq(struct jme_adapter *jme)
379 register struct dynpcc_info *dpi = &(jme->dpi);
381 jme_set_rx_pcc(jme, PCC_P1);
383 dpi->attempt = PCC_P1;
386 jwrite32(jme, JME_PCCTX,
387 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
388 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
395 jwrite32(jme, JME_IENS, INTR_ENABLE);
399 jme_stop_irq(struct jme_adapter *jme)
404 jwrite32f(jme, JME_IENC, INTR_ENABLE);
408 jme_linkstat_from_phy(struct jme_adapter *jme)
412 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
413 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
414 if (bmsr & BMSR_ANCOMP)
415 phylink |= PHY_LINK_AUTONEG_COMPLETE;
421 jme_set_phyfifo_5level(struct jme_adapter *jme)
423 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
427 jme_set_phyfifo_8level(struct jme_adapter *jme)
429 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
433 jme_check_link(struct net_device *netdev, int testonly)
435 struct jme_adapter *jme = netdev_priv(netdev);
436 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
443 phylink = jme_linkstat_from_phy(jme);
445 phylink = jread32(jme, JME_PHY_LINK);
447 if (phylink & PHY_LINK_UP) {
448 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
450 * If we did not enable AN
451 * Speed/Duplex Info should be obtained from SMI
453 phylink = PHY_LINK_UP;
455 bmcr = jme_mdio_read(jme->dev,
459 phylink |= ((bmcr & BMCR_SPEED1000) &&
460 (bmcr & BMCR_SPEED100) == 0) ?
461 PHY_LINK_SPEED_1000M :
462 (bmcr & BMCR_SPEED100) ?
463 PHY_LINK_SPEED_100M :
466 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 strcat(linkmsg, "Forced: ");
472 * Keep polling for speed/duplex resolve complete
474 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
480 phylink = jme_linkstat_from_phy(jme);
482 phylink = jread32(jme, JME_PHY_LINK);
485 pr_err("Waiting speed resolve timeout\n");
487 strcat(linkmsg, "ANed: ");
490 if (jme->phylink == phylink) {
497 jme->phylink = phylink;
500 * The speed/duplex setting of jme->reg_ghc already cleared
501 * by jme_reset_mac_processor()
503 switch (phylink & PHY_LINK_SPEED_MASK) {
504 case PHY_LINK_SPEED_10M:
505 jme->reg_ghc |= GHC_SPEED_10M;
506 strcat(linkmsg, "10 Mbps, ");
508 case PHY_LINK_SPEED_100M:
509 jme->reg_ghc |= GHC_SPEED_100M;
510 strcat(linkmsg, "100 Mbps, ");
512 case PHY_LINK_SPEED_1000M:
513 jme->reg_ghc |= GHC_SPEED_1000M;
514 strcat(linkmsg, "1000 Mbps, ");
520 if (phylink & PHY_LINK_DUPLEX) {
521 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
522 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
523 jme->reg_ghc |= GHC_DPX;
525 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
529 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
532 jwrite32(jme, JME_GHC, jme->reg_ghc);
534 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
535 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
537 if (!(phylink & PHY_LINK_DUPLEX))
538 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
539 switch (phylink & PHY_LINK_SPEED_MASK) {
540 case PHY_LINK_SPEED_10M:
541 jme_set_phyfifo_8level(jme);
542 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
544 case PHY_LINK_SPEED_100M:
545 jme_set_phyfifo_5level(jme);
546 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
548 case PHY_LINK_SPEED_1000M:
549 jme_set_phyfifo_8level(jme);
555 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
557 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
564 netif_carrier_on(netdev);
569 netif_info(jme, link, jme->dev, "Link is down\n");
571 netif_carrier_off(netdev);
579 jme_setup_tx_resources(struct jme_adapter *jme)
581 struct jme_ring *txring = &(jme->txring[0]);
583 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
584 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
594 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
596 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
597 txring->next_to_use = 0;
598 atomic_set(&txring->next_to_clean, 0);
599 atomic_set(&txring->nr_free, jme->tx_ring_size);
601 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
602 jme->tx_ring_size, GFP_ATOMIC);
603 if (unlikely(!(txring->bufinf)))
604 goto err_free_txring;
607 * Initialize Transmit Descriptors
609 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
610 memset(txring->bufinf, 0,
611 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
616 dma_free_coherent(&(jme->pdev->dev),
617 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
623 txring->dmaalloc = 0;
625 txring->bufinf = NULL;
631 jme_free_tx_resources(struct jme_adapter *jme)
634 struct jme_ring *txring = &(jme->txring[0]);
635 struct jme_buffer_info *txbi;
638 if (txring->bufinf) {
639 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
640 txbi = txring->bufinf + i;
642 dev_kfree_skb(txbi->skb);
648 txbi->start_xmit = 0;
650 kfree(txring->bufinf);
653 dma_free_coherent(&(jme->pdev->dev),
654 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
658 txring->alloc = NULL;
660 txring->dmaalloc = 0;
662 txring->bufinf = NULL;
664 txring->next_to_use = 0;
665 atomic_set(&txring->next_to_clean, 0);
666 atomic_set(&txring->nr_free, 0);
670 jme_enable_tx_engine(struct jme_adapter *jme)
675 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
679 * Setup TX Queue 0 DMA Bass Address
681 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
682 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
683 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
686 * Setup TX Descptor Count
688 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
694 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
699 * Start clock for TX MAC Processor
701 jme_mac_txclk_on(jme);
705 jme_restart_tx_engine(struct jme_adapter *jme)
710 jwrite32(jme, JME_TXCS, jme->reg_txcs |
716 jme_disable_tx_engine(struct jme_adapter *jme)
724 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
727 val = jread32(jme, JME_TXCS);
728 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
730 val = jread32(jme, JME_TXCS);
735 pr_err("Disable TX engine timeout\n");
738 * Stop clock for TX MAC Processor
740 jme_mac_txclk_off(jme);
744 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
746 struct jme_ring *rxring = &(jme->rxring[0]);
747 register struct rxdesc *rxdesc = rxring->desc;
748 struct jme_buffer_info *rxbi = rxring->bufinf;
754 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
755 rxdesc->desc1.bufaddrl = cpu_to_le32(
756 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
757 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
758 if (jme->dev->features & NETIF_F_HIGHDMA)
759 rxdesc->desc1.flags = RXFLAG_64BIT;
761 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
765 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
767 struct jme_ring *rxring = &(jme->rxring[0]);
768 struct jme_buffer_info *rxbi = rxring->bufinf + i;
771 skb = netdev_alloc_skb(jme->dev,
772 jme->dev->mtu + RX_EXTRA_LEN);
775 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
780 rxbi->len = skb_tailroom(skb);
781 rxbi->mapping = pci_map_page(jme->pdev,
782 virt_to_page(skb->data),
783 offset_in_page(skb->data),
791 jme_free_rx_buf(struct jme_adapter *jme, int i)
793 struct jme_ring *rxring = &(jme->rxring[0]);
794 struct jme_buffer_info *rxbi = rxring->bufinf;
798 pci_unmap_page(jme->pdev,
802 dev_kfree_skb(rxbi->skb);
810 jme_free_rx_resources(struct jme_adapter *jme)
813 struct jme_ring *rxring = &(jme->rxring[0]);
816 if (rxring->bufinf) {
817 for (i = 0 ; i < jme->rx_ring_size ; ++i)
818 jme_free_rx_buf(jme, i);
819 kfree(rxring->bufinf);
822 dma_free_coherent(&(jme->pdev->dev),
823 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
826 rxring->alloc = NULL;
828 rxring->dmaalloc = 0;
830 rxring->bufinf = NULL;
832 rxring->next_to_use = 0;
833 atomic_set(&rxring->next_to_clean, 0);
837 jme_setup_rx_resources(struct jme_adapter *jme)
840 struct jme_ring *rxring = &(jme->rxring[0]);
842 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
843 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
852 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
854 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
855 rxring->next_to_use = 0;
856 atomic_set(&rxring->next_to_clean, 0);
858 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
859 jme->rx_ring_size, GFP_ATOMIC);
860 if (unlikely(!(rxring->bufinf)))
861 goto err_free_rxring;
864 * Initiallize Receive Descriptors
866 memset(rxring->bufinf, 0,
867 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
868 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
869 if (unlikely(jme_make_new_rx_buf(jme, i))) {
870 jme_free_rx_resources(jme);
874 jme_set_clean_rxdesc(jme, i);
880 dma_free_coherent(&(jme->pdev->dev),
881 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
886 rxring->dmaalloc = 0;
888 rxring->bufinf = NULL;
894 jme_enable_rx_engine(struct jme_adapter *jme)
899 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
904 * Setup RX DMA Bass Address
906 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
907 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
908 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
911 * Setup RX Descriptor Count
913 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
916 * Setup Unicast Filter
918 jme_set_unicastaddr(jme->dev);
919 jme_set_multi(jme->dev);
925 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
931 * Start clock for RX MAC Processor
933 jme_mac_rxclk_on(jme);
937 jme_restart_rx_engine(struct jme_adapter *jme)
942 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
949 jme_disable_rx_engine(struct jme_adapter *jme)
957 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
960 val = jread32(jme, JME_RXCS);
961 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
963 val = jread32(jme, JME_RXCS);
968 pr_err("Disable RX engine timeout\n");
971 * Stop clock for RX MAC Processor
973 jme_mac_rxclk_off(jme);
977 jme_udpsum(struct sk_buff *skb)
981 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
983 if (skb->protocol != htons(ETH_P_IP))
985 skb_set_network_header(skb, ETH_HLEN);
986 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
987 (skb->len < (ETH_HLEN +
988 (ip_hdr(skb)->ihl << 2) +
989 sizeof(struct udphdr)))) {
990 skb_reset_network_header(skb);
993 skb_set_transport_header(skb,
994 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
995 csum = udp_hdr(skb)->check;
996 skb_reset_transport_header(skb);
997 skb_reset_network_header(skb);
1003 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1005 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1008 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1009 == RXWBFLAG_TCPON)) {
1010 if (flags & RXWBFLAG_IPV4)
1011 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1015 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1016 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1017 if (flags & RXWBFLAG_IPV4)
1018 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1022 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1023 == RXWBFLAG_IPV4)) {
1024 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1032 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1034 struct jme_ring *rxring = &(jme->rxring[0]);
1035 struct rxdesc *rxdesc = rxring->desc;
1036 struct jme_buffer_info *rxbi = rxring->bufinf;
1037 struct sk_buff *skb;
1044 pci_dma_sync_single_for_cpu(jme->pdev,
1047 PCI_DMA_FROMDEVICE);
1049 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1050 pci_dma_sync_single_for_device(jme->pdev,
1053 PCI_DMA_FROMDEVICE);
1055 ++(NET_STAT(jme).rx_dropped);
1057 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1060 skb_reserve(skb, RX_PREPAD_SIZE);
1061 skb_put(skb, framesize);
1062 skb->protocol = eth_type_trans(skb, jme->dev);
1064 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1065 skb->ip_summed = CHECKSUM_UNNECESSARY;
1067 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
1068 skb->ip_summed = CHECKSUM_NONE;
1070 skb_checksum_none_assert(skb);
1073 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1075 jme->jme_vlan_rx(skb, jme->vlgrp,
1076 le16_to_cpu(rxdesc->descwb.vlan));
1077 NET_STAT(jme).rx_bytes += 4;
1085 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1086 cpu_to_le16(RXWBFLAG_DEST_MUL))
1087 ++(NET_STAT(jme).multicast);
1089 NET_STAT(jme).rx_bytes += framesize;
1090 ++(NET_STAT(jme).rx_packets);
1093 jme_set_clean_rxdesc(jme, idx);
1098 jme_process_receive(struct jme_adapter *jme, int limit)
1100 struct jme_ring *rxring = &(jme->rxring[0]);
1101 struct rxdesc *rxdesc = rxring->desc;
1102 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1104 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1107 if (unlikely(atomic_read(&jme->link_changing) != 1))
1110 if (unlikely(!netif_carrier_ok(jme->dev)))
1113 i = atomic_read(&rxring->next_to_clean);
1115 rxdesc = rxring->desc;
1118 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1119 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1124 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1126 if (unlikely(desccnt > 1 ||
1127 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1129 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1130 ++(NET_STAT(jme).rx_crc_errors);
1131 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1132 ++(NET_STAT(jme).rx_fifo_errors);
1134 ++(NET_STAT(jme).rx_errors);
1137 limit -= desccnt - 1;
1139 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1140 jme_set_clean_rxdesc(jme, j);
1141 j = (j + 1) & (mask);
1145 jme_alloc_and_feed_skb(jme, i);
1148 i = (i + desccnt) & (mask);
1152 atomic_set(&rxring->next_to_clean, i);
1155 atomic_inc(&jme->rx_cleaning);
1157 return limit > 0 ? limit : 0;
1162 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1164 if (likely(atmp == dpi->cur)) {
1169 if (dpi->attempt == atmp) {
1172 dpi->attempt = atmp;
1179 jme_dynamic_pcc(struct jme_adapter *jme)
1181 register struct dynpcc_info *dpi = &(jme->dpi);
1183 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1184 jme_attempt_pcc(dpi, PCC_P3);
1185 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1186 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1187 jme_attempt_pcc(dpi, PCC_P2);
1189 jme_attempt_pcc(dpi, PCC_P1);
1191 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1192 if (dpi->attempt < dpi->cur)
1193 tasklet_schedule(&jme->rxclean_task);
1194 jme_set_rx_pcc(jme, dpi->attempt);
1195 dpi->cur = dpi->attempt;
1201 jme_start_pcc_timer(struct jme_adapter *jme)
1203 struct dynpcc_info *dpi = &(jme->dpi);
1204 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1205 dpi->last_pkts = NET_STAT(jme).rx_packets;
1207 jwrite32(jme, JME_TMCSR,
1208 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1212 jme_stop_pcc_timer(struct jme_adapter *jme)
1214 jwrite32(jme, JME_TMCSR, 0);
1218 jme_shutdown_nic(struct jme_adapter *jme)
1222 phylink = jme_linkstat_from_phy(jme);
1224 if (!(phylink & PHY_LINK_UP)) {
1226 * Disable all interrupt before issue timer
1229 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1234 jme_pcc_tasklet(unsigned long arg)
1236 struct jme_adapter *jme = (struct jme_adapter *)arg;
1237 struct net_device *netdev = jme->dev;
1239 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1240 jme_shutdown_nic(jme);
1244 if (unlikely(!netif_carrier_ok(netdev) ||
1245 (atomic_read(&jme->link_changing) != 1)
1247 jme_stop_pcc_timer(jme);
1251 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1252 jme_dynamic_pcc(jme);
1254 jme_start_pcc_timer(jme);
1258 jme_polling_mode(struct jme_adapter *jme)
1260 jme_set_rx_pcc(jme, PCC_OFF);
1264 jme_interrupt_mode(struct jme_adapter *jme)
1266 jme_set_rx_pcc(jme, PCC_P1);
1270 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1273 apmc = jread32(jme, JME_APMC);
1274 return apmc & JME_APMC_PSEUDO_HP_EN;
1278 jme_start_shutdown_timer(struct jme_adapter *jme)
1282 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1283 apmc &= ~JME_APMC_EPIEN_CTRL;
1285 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1288 jwrite32f(jme, JME_APMC, apmc);
1290 jwrite32f(jme, JME_TIMER2, 0);
1291 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1292 jwrite32(jme, JME_TMCSR,
1293 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1297 jme_stop_shutdown_timer(struct jme_adapter *jme)
1301 jwrite32f(jme, JME_TMCSR, 0);
1302 jwrite32f(jme, JME_TIMER2, 0);
1303 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1305 apmc = jread32(jme, JME_APMC);
1306 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1307 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1309 jwrite32f(jme, JME_APMC, apmc);
1313 jme_link_change_tasklet(unsigned long arg)
1315 struct jme_adapter *jme = (struct jme_adapter *)arg;
1316 struct net_device *netdev = jme->dev;
1319 while (!atomic_dec_and_test(&jme->link_changing)) {
1320 atomic_inc(&jme->link_changing);
1321 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1322 while (atomic_read(&jme->link_changing) != 1)
1323 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1326 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1329 jme->old_mtu = netdev->mtu;
1330 netif_stop_queue(netdev);
1331 if (jme_pseudo_hotplug_enabled(jme))
1332 jme_stop_shutdown_timer(jme);
1334 jme_stop_pcc_timer(jme);
1335 tasklet_disable(&jme->txclean_task);
1336 tasklet_disable(&jme->rxclean_task);
1337 tasklet_disable(&jme->rxempty_task);
1339 if (netif_carrier_ok(netdev)) {
1340 jme_disable_rx_engine(jme);
1341 jme_disable_tx_engine(jme);
1342 jme_reset_mac_processor(jme);
1343 jme_free_rx_resources(jme);
1344 jme_free_tx_resources(jme);
1346 if (test_bit(JME_FLAG_POLL, &jme->flags))
1347 jme_polling_mode(jme);
1349 netif_carrier_off(netdev);
1352 jme_check_link(netdev, 0);
1353 if (netif_carrier_ok(netdev)) {
1354 rc = jme_setup_rx_resources(jme);
1356 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1357 goto out_enable_tasklet;
1360 rc = jme_setup_tx_resources(jme);
1362 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1363 goto err_out_free_rx_resources;
1366 jme_enable_rx_engine(jme);
1367 jme_enable_tx_engine(jme);
1369 netif_start_queue(netdev);
1371 if (test_bit(JME_FLAG_POLL, &jme->flags))
1372 jme_interrupt_mode(jme);
1374 jme_start_pcc_timer(jme);
1375 } else if (jme_pseudo_hotplug_enabled(jme)) {
1376 jme_start_shutdown_timer(jme);
1379 goto out_enable_tasklet;
1381 err_out_free_rx_resources:
1382 jme_free_rx_resources(jme);
1384 tasklet_enable(&jme->txclean_task);
1385 tasklet_hi_enable(&jme->rxclean_task);
1386 tasklet_hi_enable(&jme->rxempty_task);
1388 atomic_inc(&jme->link_changing);
1392 jme_rx_clean_tasklet(unsigned long arg)
1394 struct jme_adapter *jme = (struct jme_adapter *)arg;
1395 struct dynpcc_info *dpi = &(jme->dpi);
1397 jme_process_receive(jme, jme->rx_ring_size);
1403 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1405 struct jme_adapter *jme = jme_napi_priv(holder);
1409 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1411 while (atomic_read(&jme->rx_empty) > 0) {
1412 atomic_dec(&jme->rx_empty);
1413 ++(NET_STAT(jme).rx_dropped);
1414 jme_restart_rx_engine(jme);
1416 atomic_inc(&jme->rx_empty);
1419 JME_RX_COMPLETE(netdev, holder);
1420 jme_interrupt_mode(jme);
1423 JME_NAPI_WEIGHT_SET(budget, rest);
1424 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1428 jme_rx_empty_tasklet(unsigned long arg)
1430 struct jme_adapter *jme = (struct jme_adapter *)arg;
1432 if (unlikely(atomic_read(&jme->link_changing) != 1))
1435 if (unlikely(!netif_carrier_ok(jme->dev)))
1438 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1440 jme_rx_clean_tasklet(arg);
1442 while (atomic_read(&jme->rx_empty) > 0) {
1443 atomic_dec(&jme->rx_empty);
1444 ++(NET_STAT(jme).rx_dropped);
1445 jme_restart_rx_engine(jme);
1447 atomic_inc(&jme->rx_empty);
1451 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1453 struct jme_ring *txring = &(jme->txring[0]);
1456 if (unlikely(netif_queue_stopped(jme->dev) &&
1457 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1458 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1459 netif_wake_queue(jme->dev);
1465 jme_tx_clean_tasklet(unsigned long arg)
1467 struct jme_adapter *jme = (struct jme_adapter *)arg;
1468 struct jme_ring *txring = &(jme->txring[0]);
1469 struct txdesc *txdesc = txring->desc;
1470 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1471 int i, j, cnt = 0, max, err, mask;
1473 tx_dbg(jme, "Into txclean\n");
1475 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1478 if (unlikely(atomic_read(&jme->link_changing) != 1))
1481 if (unlikely(!netif_carrier_ok(jme->dev)))
1484 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1485 mask = jme->tx_ring_mask;
1487 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1491 if (likely(ctxbi->skb &&
1492 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1494 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1495 i, ctxbi->nr_desc, jiffies);
1497 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1499 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1500 ttxbi = txbi + ((i + j) & (mask));
1501 txdesc[(i + j) & (mask)].dw[0] = 0;
1503 pci_unmap_page(jme->pdev,
1512 dev_kfree_skb(ctxbi->skb);
1514 cnt += ctxbi->nr_desc;
1516 if (unlikely(err)) {
1517 ++(NET_STAT(jme).tx_carrier_errors);
1519 ++(NET_STAT(jme).tx_packets);
1520 NET_STAT(jme).tx_bytes += ctxbi->len;
1525 ctxbi->start_xmit = 0;
1531 i = (i + ctxbi->nr_desc) & mask;
1536 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1537 atomic_set(&txring->next_to_clean, i);
1538 atomic_add(cnt, &txring->nr_free);
1540 jme_wake_queue_if_stopped(jme);
1543 atomic_inc(&jme->tx_cleaning);
1547 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1552 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1554 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1556 * Link change event is critical
1557 * all other events are ignored
1559 jwrite32(jme, JME_IEVE, intrstat);
1560 tasklet_schedule(&jme->linkch_task);
1564 if (intrstat & INTR_TMINTR) {
1565 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1566 tasklet_schedule(&jme->pcc_task);
1569 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1570 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1571 tasklet_schedule(&jme->txclean_task);
1574 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1575 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1581 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1582 if (intrstat & INTR_RX0EMP)
1583 atomic_inc(&jme->rx_empty);
1585 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1586 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1587 jme_polling_mode(jme);
1588 JME_RX_SCHEDULE(jme);
1592 if (intrstat & INTR_RX0EMP) {
1593 atomic_inc(&jme->rx_empty);
1594 tasklet_hi_schedule(&jme->rxempty_task);
1595 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1596 tasklet_hi_schedule(&jme->rxclean_task);
1602 * Re-enable interrupt
1604 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1607 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1609 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1612 jme_intr(int irq, void *dev_id)
1615 struct net_device *netdev = dev_id;
1616 struct jme_adapter *jme = netdev_priv(netdev);
1619 intrstat = jread32(jme, JME_IEVE);
1622 * Check if it's really an interrupt for us
1624 if (unlikely((intrstat & INTR_ENABLE) == 0))
1628 * Check if the device still exist
1630 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1633 jme_intr_msi(jme, intrstat);
1638 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1640 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1643 jme_msi(int irq, void *dev_id)
1646 struct net_device *netdev = dev_id;
1647 struct jme_adapter *jme = netdev_priv(netdev);
1650 intrstat = jread32(jme, JME_IEVE);
1652 jme_intr_msi(jme, intrstat);
1658 jme_reset_link(struct jme_adapter *jme)
1660 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1664 jme_restart_an(struct jme_adapter *jme)
1668 spin_lock_bh(&jme->phy_lock);
1669 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1670 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1671 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1672 spin_unlock_bh(&jme->phy_lock);
1676 jme_request_irq(struct jme_adapter *jme)
1679 struct net_device *netdev = jme->dev;
1680 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1681 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1682 int irq_flags = SA_SHIRQ;
1684 irq_handler_t handler = jme_intr;
1685 int irq_flags = IRQF_SHARED;
1688 if (!pci_enable_msi(jme->pdev)) {
1689 set_bit(JME_FLAG_MSI, &jme->flags);
1694 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1698 "Unable to request %s interrupt (return: %d)\n",
1699 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1702 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1703 pci_disable_msi(jme->pdev);
1704 clear_bit(JME_FLAG_MSI, &jme->flags);
1707 netdev->irq = jme->pdev->irq;
1714 jme_free_irq(struct jme_adapter *jme)
1716 free_irq(jme->pdev->irq, jme->dev);
1717 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1718 pci_disable_msi(jme->pdev);
1719 clear_bit(JME_FLAG_MSI, &jme->flags);
1720 jme->dev->irq = jme->pdev->irq;
1725 jme_new_phy_on(struct jme_adapter *jme)
1729 reg = jread32(jme, JME_PHY_PWR);
1730 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1731 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1732 jwrite32(jme, JME_PHY_PWR, reg);
1734 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1735 reg &= ~PE1_GPREG0_PBG;
1736 reg |= PE1_GPREG0_ENBG;
1737 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1741 jme_new_phy_off(struct jme_adapter *jme)
1745 reg = jread32(jme, JME_PHY_PWR);
1746 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1747 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1748 jwrite32(jme, JME_PHY_PWR, reg);
1750 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1751 reg &= ~PE1_GPREG0_PBG;
1752 reg |= PE1_GPREG0_PDD3COLD;
1753 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1757 jme_phy_on(struct jme_adapter *jme)
1761 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1762 bmcr &= ~BMCR_PDOWN;
1763 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1765 if (new_phy_power_ctrl(jme->chip_main_rev))
1766 jme_new_phy_on(jme);
1770 jme_phy_off(struct jme_adapter *jme)
1774 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1776 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1778 if (new_phy_power_ctrl(jme->chip_main_rev))
1779 jme_new_phy_off(jme);
1783 jme_open(struct net_device *netdev)
1785 struct jme_adapter *jme = netdev_priv(netdev);
1789 JME_NAPI_ENABLE(jme);
1791 tasklet_enable(&jme->linkch_task);
1792 tasklet_enable(&jme->txclean_task);
1793 tasklet_hi_enable(&jme->rxclean_task);
1794 tasklet_hi_enable(&jme->rxempty_task);
1796 rc = jme_request_irq(jme);
1803 if (test_bit(JME_FLAG_SSET, &jme->flags))
1804 jme_set_settings(netdev, &jme->old_ecmd);
1806 jme_reset_phy_processor(jme);
1808 jme_reset_link(jme);
1813 netif_stop_queue(netdev);
1814 netif_carrier_off(netdev);
1819 jme_set_100m_half(struct jme_adapter *jme)
1824 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1825 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1826 BMCR_SPEED1000 | BMCR_FULLDPLX);
1827 tmp |= BMCR_SPEED100;
1830 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1833 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1835 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1838 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1840 jme_wait_link(struct jme_adapter *jme)
1842 u32 phylink, to = JME_WAIT_LINK_TIME;
1845 phylink = jme_linkstat_from_phy(jme);
1846 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1848 phylink = jme_linkstat_from_phy(jme);
1853 jme_powersave_phy(struct jme_adapter *jme)
1855 if (jme->reg_pmcs) {
1856 jme_set_100m_half(jme);
1858 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1861 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1868 jme_close(struct net_device *netdev)
1870 struct jme_adapter *jme = netdev_priv(netdev);
1872 netif_stop_queue(netdev);
1873 netif_carrier_off(netdev);
1878 JME_NAPI_DISABLE(jme);
1880 tasklet_disable(&jme->linkch_task);
1881 tasklet_disable(&jme->txclean_task);
1882 tasklet_disable(&jme->rxclean_task);
1883 tasklet_disable(&jme->rxempty_task);
1885 jme_disable_rx_engine(jme);
1886 jme_disable_tx_engine(jme);
1887 jme_reset_mac_processor(jme);
1888 jme_free_rx_resources(jme);
1889 jme_free_tx_resources(jme);
1897 jme_alloc_txdesc(struct jme_adapter *jme,
1898 struct sk_buff *skb)
1900 struct jme_ring *txring = &(jme->txring[0]);
1901 int idx, nr_alloc, mask = jme->tx_ring_mask;
1903 idx = txring->next_to_use;
1904 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1906 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1909 atomic_sub(nr_alloc, &txring->nr_free);
1911 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1917 jme_fill_tx_map(struct pci_dev *pdev,
1918 struct txdesc *txdesc,
1919 struct jme_buffer_info *txbi,
1927 dmaaddr = pci_map_page(pdev,
1933 pci_dma_sync_single_for_device(pdev,
1940 txdesc->desc2.flags = TXFLAG_OWN;
1941 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1942 txdesc->desc2.datalen = cpu_to_le16(len);
1943 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1944 txdesc->desc2.bufaddrl = cpu_to_le32(
1945 (__u64)dmaaddr & 0xFFFFFFFFUL);
1947 txbi->mapping = dmaaddr;
1952 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1954 struct jme_ring *txring = &(jme->txring[0]);
1955 struct txdesc *txdesc = txring->desc, *ctxdesc;
1956 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1957 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1958 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1959 int mask = jme->tx_ring_mask;
1960 struct skb_frag_struct *frag;
1963 for (i = 0 ; i < nr_frags ; ++i) {
1964 frag = &skb_shinfo(skb)->frags[i];
1965 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1966 ctxbi = txbi + ((idx + i + 2) & (mask));
1968 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1969 frag->page_offset, frag->size, hidma);
1972 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1973 ctxdesc = txdesc + ((idx + 1) & (mask));
1974 ctxbi = txbi + ((idx + 1) & (mask));
1975 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1976 offset_in_page(skb->data), len, hidma);
1981 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1984 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1985 skb_shinfo(skb)->tso_size
1987 skb_shinfo(skb)->gso_size
1989 && skb_header_cloned(skb) &&
1990 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1999 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2001 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2002 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2004 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2007 *flags |= TXFLAG_LSEN;
2009 if (skb->protocol == htons(ETH_P_IP)) {
2010 struct iphdr *iph = ip_hdr(skb);
2013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2018 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2020 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2033 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2035 #ifdef CHECKSUM_PARTIAL
2036 if (skb->ip_summed == CHECKSUM_PARTIAL)
2038 if (skb->ip_summed == CHECKSUM_HW)
2043 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2044 if (skb->protocol == htons(ETH_P_IP))
2045 ip_proto = ip_hdr(skb)->protocol;
2046 else if (skb->protocol == htons(ETH_P_IPV6))
2047 ip_proto = ipv6_hdr(skb)->nexthdr;
2051 switch (skb->protocol) {
2052 case htons(ETH_P_IP):
2053 ip_proto = ip_hdr(skb)->protocol;
2055 case htons(ETH_P_IPV6):
2056 ip_proto = ipv6_hdr(skb)->nexthdr;
2066 *flags |= TXFLAG_TCPCS;
2069 *flags |= TXFLAG_UDPCS;
2072 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2079 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2081 if (vlan_tx_tag_present(skb)) {
2082 *flags |= TXFLAG_TAGON;
2083 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2088 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2090 struct jme_ring *txring = &(jme->txring[0]);
2091 struct txdesc *txdesc;
2092 struct jme_buffer_info *txbi;
2095 txdesc = (struct txdesc *)txring->desc + idx;
2096 txbi = txring->bufinf + idx;
2102 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2104 * Set OWN bit at final.
2105 * When kernel transmit faster than NIC.
2106 * And NIC trying to send this descriptor before we tell
2107 * it to start sending this TX queue.
2108 * Other fields are already filled correctly.
2111 flags = TXFLAG_OWN | TXFLAG_INT;
2113 * Set checksum flags while not tso
2115 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2116 jme_tx_csum(jme, skb, &flags);
2117 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2118 jme_map_tx_skb(jme, skb, idx);
2119 txdesc->desc1.flags = flags;
2121 * Set tx buffer info after telling NIC to send
2122 * For better tx_clean timing
2125 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2127 txbi->len = skb->len;
2128 txbi->start_xmit = jiffies;
2129 if (!txbi->start_xmit)
2130 txbi->start_xmit = (0UL-1);
2136 jme_stop_queue_if_full(struct jme_adapter *jme)
2138 struct jme_ring *txring = &(jme->txring[0]);
2139 struct jme_buffer_info *txbi = txring->bufinf;
2140 int idx = atomic_read(&txring->next_to_clean);
2145 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2146 netif_stop_queue(jme->dev);
2147 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2149 if (atomic_read(&txring->nr_free)
2150 >= (jme->tx_wake_threshold)) {
2151 netif_wake_queue(jme->dev);
2152 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2156 if (unlikely(txbi->start_xmit &&
2157 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2159 netif_stop_queue(jme->dev);
2160 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2165 * This function is already protected by netif_tx_lock()
2168 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2173 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2175 struct jme_adapter *jme = netdev_priv(netdev);
2178 if (unlikely(jme_expand_header(jme, skb))) {
2179 ++(NET_STAT(jme).tx_dropped);
2180 return NETDEV_TX_OK;
2183 idx = jme_alloc_txdesc(jme, skb);
2185 if (unlikely(idx < 0)) {
2186 netif_stop_queue(netdev);
2187 netif_err(jme, tx_err, jme->dev,
2188 "BUG! Tx ring full when queue awake!\n");
2190 return NETDEV_TX_BUSY;
2193 jme_fill_tx_desc(jme, skb, idx);
2195 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2196 TXCS_SELECT_QUEUE0 |
2199 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2200 netdev->trans_start = jiffies;
2203 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2204 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2205 jme_stop_queue_if_full(jme);
2207 return NETDEV_TX_OK;
2211 jme_set_unicastaddr(struct net_device *netdev)
2213 struct jme_adapter *jme = netdev_priv(netdev);
2216 val = (netdev->dev_addr[3] & 0xff) << 24 |
2217 (netdev->dev_addr[2] & 0xff) << 16 |
2218 (netdev->dev_addr[1] & 0xff) << 8 |
2219 (netdev->dev_addr[0] & 0xff);
2220 jwrite32(jme, JME_RXUMA_LO, val);
2221 val = (netdev->dev_addr[5] & 0xff) << 8 |
2222 (netdev->dev_addr[4] & 0xff);
2223 jwrite32(jme, JME_RXUMA_HI, val);
2227 jme_set_macaddr(struct net_device *netdev, void *p)
2229 struct jme_adapter *jme = netdev_priv(netdev);
2230 struct sockaddr *addr = p;
2232 if (netif_running(netdev))
2235 spin_lock_bh(&jme->macaddr_lock);
2236 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2237 jme_set_unicastaddr(netdev);
2238 spin_unlock_bh(&jme->macaddr_lock);
2244 jme_set_multi(struct net_device *netdev)
2246 struct jme_adapter *jme = netdev_priv(netdev);
2247 u32 mc_hash[2] = {};
2248 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2252 spin_lock_bh(&jme->rxmcs_lock);
2254 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2256 if (netdev->flags & IFF_PROMISC) {
2257 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2258 } else if (netdev->flags & IFF_ALLMULTI) {
2259 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2260 } else if (netdev->flags & IFF_MULTICAST) {
2261 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2262 struct dev_mc_list *mclist;
2264 struct netdev_hw_addr *ha;
2268 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2269 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2270 for (i = 0, mclist = netdev->mc_list;
2271 mclist && i < netdev->mc_count;
2272 ++i, mclist = mclist->next) {
2273 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2274 netdev_for_each_mc_addr(mclist, netdev) {
2276 netdev_for_each_mc_addr(ha, netdev) {
2278 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2279 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2281 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2283 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2286 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2287 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2291 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2293 spin_unlock_bh(&jme->rxmcs_lock);
2297 jme_change_mtu(struct net_device *netdev, int new_mtu)
2299 struct jme_adapter *jme = netdev_priv(netdev);
2301 if (new_mtu == jme->old_mtu)
2304 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2305 ((new_mtu) < IPV6_MIN_MTU))
2308 if (new_mtu > 4000) {
2309 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2310 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2311 jme_restart_rx_engine(jme);
2313 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2314 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2315 jme_restart_rx_engine(jme);
2318 if (new_mtu > 1900) {
2319 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2320 NETIF_F_TSO | NETIF_F_TSO6);
2322 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2323 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2324 if (test_bit(JME_FLAG_TSO, &jme->flags))
2325 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2328 netdev->mtu = new_mtu;
2329 jme_reset_link(jme);
2335 jme_tx_timeout(struct net_device *netdev)
2337 struct jme_adapter *jme = netdev_priv(netdev);
2340 jme_reset_phy_processor(jme);
2341 if (test_bit(JME_FLAG_SSET, &jme->flags))
2342 jme_set_settings(netdev, &jme->old_ecmd);
2345 * Force to Reset the link again
2347 jme_reset_link(jme);
2350 static inline void jme_pause_rx(struct jme_adapter *jme)
2352 atomic_dec(&jme->link_changing);
2354 jme_set_rx_pcc(jme, PCC_OFF);
2355 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2356 JME_NAPI_DISABLE(jme);
2358 tasklet_disable(&jme->rxclean_task);
2359 tasklet_disable(&jme->rxempty_task);
2363 static inline void jme_resume_rx(struct jme_adapter *jme)
2365 struct dynpcc_info *dpi = &(jme->dpi);
2367 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2368 JME_NAPI_ENABLE(jme);
2370 tasklet_hi_enable(&jme->rxclean_task);
2371 tasklet_hi_enable(&jme->rxempty_task);
2374 dpi->attempt = PCC_P1;
2376 jme_set_rx_pcc(jme, PCC_P1);
2378 atomic_inc(&jme->link_changing);
2382 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2384 struct jme_adapter *jme = netdev_priv(netdev);
2391 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2393 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2395 struct jme_adapter *jme = netdev_priv(netdev);
2399 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2400 jme->vlgrp->vlan_devices[vid] = NULL;
2402 vlan_group_set_device(jme->vlgrp, vid, NULL);
2410 jme_get_drvinfo(struct net_device *netdev,
2411 struct ethtool_drvinfo *info)
2413 struct jme_adapter *jme = netdev_priv(netdev);
2415 strcpy(info->driver, DRV_NAME);
2416 strcpy(info->version, DRV_VERSION);
2417 strcpy(info->bus_info, pci_name(jme->pdev));
2421 jme_get_regs_len(struct net_device *netdev)
2427 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2431 for (i = 0 ; i < len ; i += 4)
2432 p[i >> 2] = jread32(jme, reg + i);
2436 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2439 u16 *p16 = (u16 *)p;
2441 for (i = 0 ; i < reg_nr ; ++i)
2442 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2446 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2448 struct jme_adapter *jme = netdev_priv(netdev);
2449 u32 *p32 = (u32 *)p;
2451 memset(p, 0xFF, JME_REG_LEN);
2454 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2457 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2460 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2463 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2466 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2470 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2472 struct jme_adapter *jme = netdev_priv(netdev);
2474 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2475 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2477 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2478 ecmd->use_adaptive_rx_coalesce = false;
2479 ecmd->rx_coalesce_usecs = 0;
2480 ecmd->rx_max_coalesced_frames = 0;
2484 ecmd->use_adaptive_rx_coalesce = true;
2486 switch (jme->dpi.cur) {
2488 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2489 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2492 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2493 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2496 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2497 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2507 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2509 struct jme_adapter *jme = netdev_priv(netdev);
2510 struct dynpcc_info *dpi = &(jme->dpi);
2512 if (netif_running(netdev))
2515 if (ecmd->use_adaptive_rx_coalesce &&
2516 test_bit(JME_FLAG_POLL, &jme->flags)) {
2517 clear_bit(JME_FLAG_POLL, &jme->flags);
2518 jme->jme_rx = netif_rx;
2519 jme->jme_vlan_rx = vlan_hwaccel_rx;
2521 dpi->attempt = PCC_P1;
2523 jme_set_rx_pcc(jme, PCC_P1);
2524 jme_interrupt_mode(jme);
2525 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2526 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2527 set_bit(JME_FLAG_POLL, &jme->flags);
2528 jme->jme_rx = netif_receive_skb;
2529 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2530 jme_interrupt_mode(jme);
2537 jme_get_pauseparam(struct net_device *netdev,
2538 struct ethtool_pauseparam *ecmd)
2540 struct jme_adapter *jme = netdev_priv(netdev);
2543 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2544 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2546 spin_lock_bh(&jme->phy_lock);
2547 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2548 spin_unlock_bh(&jme->phy_lock);
2551 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2555 jme_set_pauseparam(struct net_device *netdev,
2556 struct ethtool_pauseparam *ecmd)
2558 struct jme_adapter *jme = netdev_priv(netdev);
2561 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2562 (ecmd->tx_pause != 0)) {
2565 jme->reg_txpfc |= TXPFC_PF_EN;
2567 jme->reg_txpfc &= ~TXPFC_PF_EN;
2569 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2572 spin_lock_bh(&jme->rxmcs_lock);
2573 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2574 (ecmd->rx_pause != 0)) {
2577 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2579 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2581 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2583 spin_unlock_bh(&jme->rxmcs_lock);
2585 spin_lock_bh(&jme->phy_lock);
2586 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2587 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2588 (ecmd->autoneg != 0)) {
2591 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2593 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2595 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2596 MII_ADVERTISE, val);
2598 spin_unlock_bh(&jme->phy_lock);
2604 jme_get_wol(struct net_device *netdev,
2605 struct ethtool_wolinfo *wol)
2607 struct jme_adapter *jme = netdev_priv(netdev);
2609 wol->supported = WAKE_MAGIC | WAKE_PHY;
2613 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2614 wol->wolopts |= WAKE_PHY;
2616 if (jme->reg_pmcs & PMCS_MFEN)
2617 wol->wolopts |= WAKE_MAGIC;
2622 jme_set_wol(struct net_device *netdev,
2623 struct ethtool_wolinfo *wol)
2625 struct jme_adapter *jme = netdev_priv(netdev);
2627 if (wol->wolopts & (WAKE_MAGICSECURE |
2636 if (wol->wolopts & WAKE_PHY)
2637 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2639 if (wol->wolopts & WAKE_MAGIC)
2640 jme->reg_pmcs |= PMCS_MFEN;
2642 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2644 #ifndef JME_NEW_PM_API
2645 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2647 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
2648 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2654 jme_get_settings(struct net_device *netdev,
2655 struct ethtool_cmd *ecmd)
2657 struct jme_adapter *jme = netdev_priv(netdev);
2660 spin_lock_bh(&jme->phy_lock);
2661 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2662 spin_unlock_bh(&jme->phy_lock);
2667 jme_set_settings(struct net_device *netdev,
2668 struct ethtool_cmd *ecmd)
2670 struct jme_adapter *jme = netdev_priv(netdev);
2673 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2677 * Check If user changed duplex only while force_media.
2678 * Hardware would not generate link change interrupt.
2680 if (jme->mii_if.force_media &&
2681 ecmd->autoneg != AUTONEG_ENABLE &&
2682 (jme->mii_if.full_duplex != ecmd->duplex))
2685 spin_lock_bh(&jme->phy_lock);
2686 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2687 spin_unlock_bh(&jme->phy_lock);
2691 jme_reset_link(jme);
2692 jme->old_ecmd = *ecmd;
2693 set_bit(JME_FLAG_SSET, &jme->flags);
2700 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2703 struct jme_adapter *jme = netdev_priv(netdev);
2704 struct mii_ioctl_data *mii_data = if_mii(rq);
2705 unsigned int duplex_chg;
2707 if (cmd == SIOCSMIIREG) {
2708 u16 val = mii_data->val_in;
2709 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2710 (val & BMCR_SPEED1000))
2714 spin_lock_bh(&jme->phy_lock);
2715 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2716 spin_unlock_bh(&jme->phy_lock);
2718 if (!rc && (cmd == SIOCSMIIREG)) {
2720 jme_reset_link(jme);
2721 jme_get_settings(netdev, &jme->old_ecmd);
2722 set_bit(JME_FLAG_SSET, &jme->flags);
2729 jme_get_link(struct net_device *netdev)
2731 struct jme_adapter *jme = netdev_priv(netdev);
2732 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2736 jme_get_msglevel(struct net_device *netdev)
2738 struct jme_adapter *jme = netdev_priv(netdev);
2739 return jme->msg_enable;
2743 jme_set_msglevel(struct net_device *netdev, u32 value)
2745 struct jme_adapter *jme = netdev_priv(netdev);
2746 jme->msg_enable = value;
2750 jme_get_rx_csum(struct net_device *netdev)
2752 struct jme_adapter *jme = netdev_priv(netdev);
2753 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2757 jme_set_rx_csum(struct net_device *netdev, u32 on)
2759 struct jme_adapter *jme = netdev_priv(netdev);
2761 spin_lock_bh(&jme->rxmcs_lock);
2763 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2765 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2766 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2767 spin_unlock_bh(&jme->rxmcs_lock);
2773 jme_set_tx_csum(struct net_device *netdev, u32 on)
2775 struct jme_adapter *jme = netdev_priv(netdev);
2778 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2779 if (netdev->mtu <= 1900)
2781 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2783 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2785 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2792 jme_set_tso(struct net_device *netdev, u32 on)
2794 struct jme_adapter *jme = netdev_priv(netdev);
2797 set_bit(JME_FLAG_TSO, &jme->flags);
2798 if (netdev->mtu <= 1900)
2799 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2801 clear_bit(JME_FLAG_TSO, &jme->flags);
2802 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2809 jme_nway_reset(struct net_device *netdev)
2811 struct jme_adapter *jme = netdev_priv(netdev);
2812 jme_restart_an(jme);
2817 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2822 val = jread32(jme, JME_SMBCSR);
2823 to = JME_SMB_BUSY_TIMEOUT;
2824 while ((val & SMBCSR_BUSY) && --to) {
2826 val = jread32(jme, JME_SMBCSR);
2829 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2833 jwrite32(jme, JME_SMBINTF,
2834 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2835 SMBINTF_HWRWN_READ |
2838 val = jread32(jme, JME_SMBINTF);
2839 to = JME_SMB_BUSY_TIMEOUT;
2840 while ((val & SMBINTF_HWCMD) && --to) {
2842 val = jread32(jme, JME_SMBINTF);
2845 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2849 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2853 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2858 val = jread32(jme, JME_SMBCSR);
2859 to = JME_SMB_BUSY_TIMEOUT;
2860 while ((val & SMBCSR_BUSY) && --to) {
2862 val = jread32(jme, JME_SMBCSR);
2865 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2869 jwrite32(jme, JME_SMBINTF,
2870 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2871 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2872 SMBINTF_HWRWN_WRITE |
2875 val = jread32(jme, JME_SMBINTF);
2876 to = JME_SMB_BUSY_TIMEOUT;
2877 while ((val & SMBINTF_HWCMD) && --to) {
2879 val = jread32(jme, JME_SMBINTF);
2882 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2890 jme_get_eeprom_len(struct net_device *netdev)
2892 struct jme_adapter *jme = netdev_priv(netdev);
2894 val = jread32(jme, JME_SMBCSR);
2895 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2899 jme_get_eeprom(struct net_device *netdev,
2900 struct ethtool_eeprom *eeprom, u8 *data)
2902 struct jme_adapter *jme = netdev_priv(netdev);
2903 int i, offset = eeprom->offset, len = eeprom->len;
2906 * ethtool will check the boundary for us
2908 eeprom->magic = JME_EEPROM_MAGIC;
2909 for (i = 0 ; i < len ; ++i)
2910 data[i] = jme_smb_read(jme, i + offset);
2916 jme_set_eeprom(struct net_device *netdev,
2917 struct ethtool_eeprom *eeprom, u8 *data)
2919 struct jme_adapter *jme = netdev_priv(netdev);
2920 int i, offset = eeprom->offset, len = eeprom->len;
2922 if (eeprom->magic != JME_EEPROM_MAGIC)
2926 * ethtool will check the boundary for us
2928 for (i = 0 ; i < len ; ++i)
2929 jme_smb_write(jme, i + offset, data[i]);
2934 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2935 static struct ethtool_ops jme_ethtool_ops = {
2937 static const struct ethtool_ops jme_ethtool_ops = {
2939 .get_drvinfo = jme_get_drvinfo,
2940 .get_regs_len = jme_get_regs_len,
2941 .get_regs = jme_get_regs,
2942 .get_coalesce = jme_get_coalesce,
2943 .set_coalesce = jme_set_coalesce,
2944 .get_pauseparam = jme_get_pauseparam,
2945 .set_pauseparam = jme_set_pauseparam,
2946 .get_wol = jme_get_wol,
2947 .set_wol = jme_set_wol,
2948 .get_settings = jme_get_settings,
2949 .set_settings = jme_set_settings,
2950 .get_link = jme_get_link,
2951 .get_msglevel = jme_get_msglevel,
2952 .set_msglevel = jme_set_msglevel,
2953 .get_rx_csum = jme_get_rx_csum,
2954 .set_rx_csum = jme_set_rx_csum,
2955 .set_tx_csum = jme_set_tx_csum,
2956 .set_tso = jme_set_tso,
2957 .set_sg = ethtool_op_set_sg,
2958 .nway_reset = jme_nway_reset,
2959 .get_eeprom_len = jme_get_eeprom_len,
2960 .get_eeprom = jme_get_eeprom,
2961 .set_eeprom = jme_set_eeprom,
2965 jme_pci_dma64(struct pci_dev *pdev)
2967 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2968 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2969 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2971 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2974 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2975 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2977 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2981 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2982 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2983 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2985 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2988 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2989 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2991 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2995 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2996 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2997 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2999 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3000 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3008 jme_phy_init(struct jme_adapter *jme)
3012 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3013 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3017 jme_check_hw_ver(struct jme_adapter *jme)
3021 chipmode = jread32(jme, JME_CHIPMODE);
3023 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3024 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3025 jme->chip_main_rev = jme->chiprev & 0xF;
3026 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3029 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3030 static const struct net_device_ops jme_netdev_ops = {
3031 .ndo_open = jme_open,
3032 .ndo_stop = jme_close,
3033 .ndo_validate_addr = eth_validate_addr,
3034 .ndo_do_ioctl = jme_ioctl,
3035 .ndo_start_xmit = jme_start_xmit,
3036 .ndo_set_mac_address = jme_set_macaddr,
3037 .ndo_set_multicast_list = jme_set_multi,
3038 .ndo_change_mtu = jme_change_mtu,
3039 .ndo_tx_timeout = jme_tx_timeout,
3040 .ndo_vlan_rx_register = jme_vlan_rx_register,
3044 static int __devinit
3045 jme_init_one(struct pci_dev *pdev,
3046 const struct pci_device_id *ent)
3048 int rc = 0, using_dac, i;
3049 struct net_device *netdev;
3050 struct jme_adapter *jme;
3055 * set up PCI device basics
3057 rc = pci_enable_device(pdev);
3059 pr_err("Cannot enable PCI device\n");
3063 using_dac = jme_pci_dma64(pdev);
3064 if (using_dac < 0) {
3065 pr_err("Cannot set PCI DMA Mask\n");
3067 goto err_out_disable_pdev;
3070 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3071 pr_err("No PCI resource region found\n");
3073 goto err_out_disable_pdev;
3076 rc = pci_request_regions(pdev, DRV_NAME);
3078 pr_err("Cannot obtain PCI resource region\n");
3079 goto err_out_disable_pdev;
3082 pci_set_master(pdev);
3085 * alloc and init net device
3087 netdev = alloc_etherdev(sizeof(*jme));
3089 pr_err("Cannot allocate netdev structure\n");
3091 goto err_out_release_regions;
3093 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3094 netdev->netdev_ops = &jme_netdev_ops;
3096 netdev->open = jme_open;
3097 netdev->stop = jme_close;
3098 netdev->do_ioctl = jme_ioctl;
3099 netdev->hard_start_xmit = jme_start_xmit;
3100 netdev->set_mac_address = jme_set_macaddr;
3101 netdev->set_multicast_list = jme_set_multi;
3102 netdev->change_mtu = jme_change_mtu;
3103 netdev->tx_timeout = jme_tx_timeout;
3104 netdev->vlan_rx_register = jme_vlan_rx_register;
3105 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3106 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3108 NETDEV_GET_STATS(netdev, &jme_get_stats);
3110 netdev->ethtool_ops = &jme_ethtool_ops;
3111 netdev->watchdog_timeo = TX_TIMEOUT;
3112 netdev->features = NETIF_F_IP_CSUM |
3117 NETIF_F_HW_VLAN_TX |
3120 netdev->features |= NETIF_F_HIGHDMA;
3122 SET_NETDEV_DEV(netdev, &pdev->dev);
3123 pci_set_drvdata(pdev, netdev);
3128 jme = netdev_priv(netdev);
3131 jme->jme_rx = netif_rx;
3132 jme->jme_vlan_rx = vlan_hwaccel_rx;
3133 jme->old_mtu = netdev->mtu = 1500;
3135 jme->tx_ring_size = 1 << 10;
3136 jme->tx_ring_mask = jme->tx_ring_size - 1;
3137 jme->tx_wake_threshold = 1 << 9;
3138 jme->rx_ring_size = 1 << 9;
3139 jme->rx_ring_mask = jme->rx_ring_size - 1;
3140 jme->msg_enable = JME_DEF_MSG_ENABLE;
3141 jme->regs = ioremap(pci_resource_start(pdev, 0),
3142 pci_resource_len(pdev, 0));
3144 pr_err("Mapping PCI resource region error\n");
3146 goto err_out_free_netdev;
3150 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3151 jwrite32(jme, JME_APMC, apmc);
3152 } else if (force_pseudohp) {
3153 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3154 jwrite32(jme, JME_APMC, apmc);
3157 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3159 spin_lock_init(&jme->phy_lock);
3160 spin_lock_init(&jme->macaddr_lock);
3161 spin_lock_init(&jme->rxmcs_lock);
3163 atomic_set(&jme->link_changing, 1);
3164 atomic_set(&jme->rx_cleaning, 1);
3165 atomic_set(&jme->tx_cleaning, 1);
3166 atomic_set(&jme->rx_empty, 1);
3168 tasklet_init(&jme->pcc_task,
3170 (unsigned long) jme);
3171 tasklet_init(&jme->linkch_task,
3172 jme_link_change_tasklet,
3173 (unsigned long) jme);
3174 tasklet_init(&jme->txclean_task,
3175 jme_tx_clean_tasklet,
3176 (unsigned long) jme);
3177 tasklet_init(&jme->rxclean_task,
3178 jme_rx_clean_tasklet,
3179 (unsigned long) jme);
3180 tasklet_init(&jme->rxempty_task,
3181 jme_rx_empty_tasklet,
3182 (unsigned long) jme);
3183 tasklet_disable_nosync(&jme->linkch_task);
3184 tasklet_disable_nosync(&jme->txclean_task);
3185 tasklet_disable_nosync(&jme->rxclean_task);
3186 tasklet_disable_nosync(&jme->rxempty_task);
3187 jme->dpi.cur = PCC_P1;
3190 jme->reg_rxcs = RXCS_DEFAULT;
3191 jme->reg_rxmcs = RXMCS_DEFAULT;
3193 jme->reg_pmcs = PMCS_MFEN;
3194 jme->reg_gpreg1 = GPREG1_DEFAULT;
3195 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3196 set_bit(JME_FLAG_TSO, &jme->flags);
3199 pci_set_power_state(jme->pdev, PCI_D0);
3200 #ifndef JME_NEW_PM_API
3201 jme_pci_wakeup_enable(jme, true);
3203 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3204 device_set_wakeup_enable(&jme->pdev->dev, true);
3208 * Get Max Read Req Size from PCI Config Space
3210 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3211 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3212 switch (jme->mrrs) {
3214 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3217 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3220 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3225 * Must check before reset_mac_processor
3227 jme_check_hw_ver(jme);
3228 jme->mii_if.dev = netdev;
3230 jme->mii_if.phy_id = 0;
3231 for (i = 1 ; i < 32 ; ++i) {
3232 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3233 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3234 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3235 jme->mii_if.phy_id = i;
3240 if (!jme->mii_if.phy_id) {
3242 pr_err("Can not find phy_id\n");
3246 jme->reg_ghc |= GHC_LINK_POLL;
3248 jme->mii_if.phy_id = 1;
3250 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3251 jme->mii_if.supports_gmii = true;
3253 jme->mii_if.supports_gmii = false;
3254 jme->mii_if.phy_id_mask = 0x1F;
3255 jme->mii_if.reg_num_mask = 0x1F;
3256 jme->mii_if.mdio_read = jme_mdio_read;
3257 jme->mii_if.mdio_write = jme_mdio_write;
3259 jme_set_phyfifo_5level(jme);
3260 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3261 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3263 jme->pcirev = pdev->revision;
3270 * Reset MAC processor and reload EEPROM for MAC Address
3272 jme_reset_mac_processor(jme);
3273 rc = jme_reload_eeprom(jme);
3275 pr_err("Reload eeprom for reading MAC Address error\n");
3278 jme_load_macaddr(netdev);
3281 * Tell stack that we are not ready to work until open()
3283 netif_carrier_off(netdev);
3285 rc = register_netdev(netdev);
3287 pr_err("Cannot register net device\n");
3291 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3292 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3293 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3294 "JMC250 Gigabit Ethernet" :
3295 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3296 "JMC260 Fast Ethernet" : "Unknown",
3297 (jme->fpgaver != 0) ? " (FPGA)" : "",
3298 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3300 netdev->dev_addr[0],
3301 netdev->dev_addr[1],
3302 netdev->dev_addr[2],
3303 netdev->dev_addr[3],
3304 netdev->dev_addr[4],
3305 netdev->dev_addr[5]);
3311 err_out_free_netdev:
3312 pci_set_drvdata(pdev, NULL);
3313 free_netdev(netdev);
3314 err_out_release_regions:
3315 pci_release_regions(pdev);
3316 err_out_disable_pdev:
3317 pci_disable_device(pdev);
3322 static void __devexit
3323 jme_remove_one(struct pci_dev *pdev)
3325 struct net_device *netdev = pci_get_drvdata(pdev);
3326 struct jme_adapter *jme = netdev_priv(netdev);
3328 unregister_netdev(netdev);
3330 pci_set_drvdata(pdev, NULL);
3331 free_netdev(netdev);
3332 pci_release_regions(pdev);
3333 pci_disable_device(pdev);
3338 jme_shutdown(struct pci_dev *pdev)
3340 struct net_device *netdev = pci_get_drvdata(pdev);
3341 struct jme_adapter *jme = netdev_priv(netdev);
3343 if (jme->reg_pmcs) {
3344 jme_powersave_phy(jme);
3345 jme_pci_wakeup_enable(jme, true);
3346 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3347 device_set_wakeup_enable(&jme->pdev->dev, true);
3354 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3359 #ifdef CONFIG_PM_SLEEP
3366 #ifdef JME_NEW_PM_API
3367 jme_suspend(struct device *dev)
3369 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3372 #ifdef JME_NEW_PM_API
3373 struct pci_dev *pdev = to_pci_dev(dev);
3375 struct net_device *netdev = pci_get_drvdata(pdev);
3376 struct jme_adapter *jme = netdev_priv(netdev);
3378 atomic_dec(&jme->link_changing);
3380 netif_device_detach(netdev);
3381 netif_stop_queue(netdev);
3384 tasklet_disable(&jme->txclean_task);
3385 tasklet_disable(&jme->rxclean_task);
3386 tasklet_disable(&jme->rxempty_task);
3388 if (netif_carrier_ok(netdev)) {
3389 if (test_bit(JME_FLAG_POLL, &jme->flags))
3390 jme_polling_mode(jme);
3392 jme_stop_pcc_timer(jme);
3393 jme_disable_rx_engine(jme);
3394 jme_disable_tx_engine(jme);
3395 jme_reset_mac_processor(jme);
3396 jme_free_rx_resources(jme);
3397 jme_free_tx_resources(jme);
3398 netif_carrier_off(netdev);
3402 tasklet_enable(&jme->txclean_task);
3403 tasklet_hi_enable(&jme->rxclean_task);
3404 tasklet_hi_enable(&jme->rxempty_task);
3406 jme_powersave_phy(jme);
3407 #ifndef JME_NEW_PM_API
3408 pci_save_state(pdev);
3409 jme_pci_wakeup_enable(jme, true);
3410 pci_set_power_state(pdev, PCI_D3hot);
3418 #ifdef JME_NEW_PM_API
3419 jme_resume(struct device *dev)
3421 jme_resume(struct pci_dev *pdev)
3424 #ifdef JME_NEW_PM_API
3425 struct pci_dev *pdev = to_pci_dev(dev);
3427 struct net_device *netdev = pci_get_drvdata(pdev);
3428 struct jme_adapter *jme = netdev_priv(netdev);
3431 #ifndef JME_NEW_PM_API
3432 pci_set_power_state(pdev, PCI_D0);
3433 pci_restore_state(pdev);
3437 if (test_bit(JME_FLAG_SSET, &jme->flags))
3438 jme_set_settings(netdev, &jme->old_ecmd);
3440 jme_reset_phy_processor(jme);
3443 netif_device_attach(netdev);
3445 atomic_inc(&jme->link_changing);
3447 jme_reset_link(jme);
3452 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
3453 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3454 #define JME_PM_OPS (&jme_pm_ops)
3459 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
3460 #define JME_PM_OPS NULL
3464 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3465 static struct pci_device_id jme_pci_tbl[] = {
3467 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3469 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3470 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3474 static struct pci_driver jme_driver = {
3476 .id_table = jme_pci_tbl,
3477 .probe = jme_init_one,
3478 .remove = __devexit_p(jme_remove_one),
3479 .shutdown = jme_shutdown,
3480 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,38)
3481 .suspend = jme_suspend,
3482 .resume = jme_resume
3484 .driver.pm = JME_PM_OPS,
3489 jme_init_module(void)
3491 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3492 return pci_register_driver(&jme_driver);
3496 jme_cleanup_module(void)
3498 pci_unregister_driver(&jme_driver);
3501 module_init(jme_init_module);
3502 module_exit(jme_cleanup_module);
3504 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3505 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3506 MODULE_LICENSE("GPL");
3507 MODULE_VERSION(DRV_VERSION);
3508 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);