2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
26 #include <video/sh_mobile_hdmi.h>
27 #include <video/sh_mobile_lcdc.h>
29 #include "sh_mobile_lcdcfb.h"
31 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
32 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
33 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
34 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
35 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
36 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
37 bits 19..16 of Internal CTS */
38 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
39 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
40 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
41 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
42 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
43 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
44 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
45 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
46 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
47 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
48 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
49 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
50 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
51 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
52 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
53 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
54 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
55 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
56 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
58 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
59 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
61 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
62 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
63 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
64 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
65 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
66 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
67 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
68 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
69 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
70 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
71 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
72 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
73 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
74 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
75 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
76 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
77 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
78 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
79 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
80 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
81 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
82 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
83 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
84 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
85 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
86 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
87 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
95 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
96 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
97 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
127 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
128 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
129 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
130 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
131 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
132 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
133 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
134 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
135 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
136 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
137 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
138 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
139 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
140 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
141 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
142 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
143 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
144 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
145 #define HDMI_SHA0 0xB9 /* sha0 */
146 #define HDMI_SHA1 0xBA /* sha1 */
147 #define HDMI_SHA2 0xBB /* sha2 */
148 #define HDMI_SHA3 0xBC /* sha3 */
149 #define HDMI_SHA4 0xBD /* sha4 */
150 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
151 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
152 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
153 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
154 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
155 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
156 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
157 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
158 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
159 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
160 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
161 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
162 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
163 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
164 #define HDMI_AN_SEED 0xCC /* An seed */
165 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
166 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
167 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
168 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
169 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
170 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
171 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
172 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
173 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
174 #define HDMI_PJ 0xD7 /* Pj */
175 #define HDMI_SHA_RD 0xD8 /* sha_rd */
176 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
177 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
178 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
179 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
180 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
181 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
182 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
183 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
184 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
185 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
186 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
187 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
188 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
189 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
190 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
191 #define HDMI_AN_23_16 0xEA /* An [23:16] */
192 #define HDMI_AN_31_24 0xEB /* An [31:24] */
193 #define HDMI_AN_39_32 0xEC /* An [39:32] */
194 #define HDMI_AN_47_40 0xED /* An [47:40] */
195 #define HDMI_AN_55_48 0xEE /* An [55:48] */
196 #define HDMI_AN_63_56 0xEF /* An [63:56] */
197 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
198 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
199 #define HDMI_TEST_MODE 0xFE /* Test mode */
202 HDMI_HOTPLUG_DISCONNECTED,
203 HDMI_HOTPLUG_CONNECTED,
204 HDMI_HOTPLUG_EDID_DONE,
209 enum hotplug_state hp_state; /* hot-plug status */
210 bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
211 struct clk *hdmi_clk;
213 struct fb_info *info;
214 struct mutex mutex; /* Protect the info pointer */
215 struct delayed_work edid_work;
216 struct fb_var_screeninfo var;
217 struct fb_monspecs monspec;
220 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
222 iowrite8(data, hdmi->base + reg);
225 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
227 return ioread8(hdmi->base + reg);
230 /* External video parameter settings */
231 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
233 struct fb_var_screeninfo *var = &hdmi->var;
234 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
237 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
239 hdelay = var->hsync_len + var->left_margin;
240 hblank = var->right_margin + hdelay;
243 * Vertical timing looks a bit different in Figure 18,
244 * but let's try the same first by setting offset = 0
246 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
248 vdelay = var->vsync_len + var->upper_margin;
249 vblank = var->lower_margin + vdelay;
250 voffset = min(var->upper_margin / 2, 6U);
253 * [3]: VSYNC polarity: Positive
254 * [2]: HSYNC polarity: Positive
255 * [1]: Interlace/Progressive: Progressive
256 * [0]: External video settings enable: used.
258 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
260 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
263 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
264 htotal, hblank, hdelay, var->hsync_len,
265 vtotal, vblank, vdelay, var->vsync_len, sync);
267 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
269 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
270 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
272 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
273 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
275 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
276 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
278 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
279 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
281 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
282 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
284 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
286 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
288 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
290 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
291 if (!hdmi->preprogrammed_mode)
292 hdmi_write(hdmi, sync | 1 | (voffset << 4),
293 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
297 * sh_hdmi_video_config()
299 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
302 * [7:4]: Audio sampling frequency: 48kHz
303 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
304 * [0]: Internal/External DE select: internal
306 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
309 * [7:6]: Video output format: RGB 4:4:4
310 * [5:4]: Input video data width: 8 bit
311 * [3:1]: EAV/SAV location: channel 1
312 * [0]: Video input color space: RGB
314 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
317 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
318 * left at 0 by default, this configures 24bpp and sets the Color Depth
319 * (CD) field in the General Control Packet
321 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
325 * sh_hdmi_audio_config()
327 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
330 * [7:4] L/R data swap control
331 * [3:0] appropriate N[19:16]
333 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
334 /* appropriate N[15:8] */
335 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
336 /* appropriate N[7:0] */
337 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
339 /* [7:4] 48 kHz SPDIF not used */
340 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
343 * [6:5] set required down sampling rate if required
344 * [4:3] set required audio source
346 hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1);
348 /* [3:0] set sending channel number for channel status */
349 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
352 * [5:2] set valid I2S source input pin
353 * [1:0] set input I2S source mode
355 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
357 /* [7:4] set valid DSD source input pin */
358 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
360 /* [7:0] set appropriate I2S input pin swap settings if required */
361 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
364 * [7] set validity bit for channel status
365 * [3:0] set original sample frequency for channel status
367 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
370 * [7] set value for channel status
371 * [6] set value for channel status
372 * [5] set copyright bit for channel status
373 * [4:2] set additional information for channel status
374 * [1:0] set clock accuracy for channel status
376 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
378 /* [7:0] set category code for channel status */
379 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
382 * [7:4] set source number for channel status
383 * [3:0] set word length for channel status
385 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
387 /* [7:4] set sample frequency for channel status */
388 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
392 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
394 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
396 if (hdmi->var.yres > 480) {
397 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
405 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
406 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
407 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
412 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
413 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
414 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
416 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
417 * LPF capacitance, LPF resistance[1]
419 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
420 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
421 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
423 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
424 * LPF capacitance, LPF resistance[1]
426 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
427 /* DRV_CONFIG, PE_CONFIG */
428 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
430 * [2:0] AMON_SEL (4 == LPF voltage)
431 * [4] PLLA_CONFIG[16]
432 * [5] PLLB_CONFIG[16]
434 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
436 /* for 480p8bit 27MHz */
437 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
438 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
439 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
440 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
441 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
442 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
443 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
444 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
445 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
450 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
452 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
457 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
459 /* Packet Type = 0x82 */
460 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
463 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
465 /* Length = 13 (0x0D) */
466 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
469 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
474 * B = Bar Data not valid
477 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
480 * [7:6] C = Colorimetry: no data
481 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
482 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
484 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
489 * Q = Default (depends on video format)
490 * SC = No Known non_uniform Scaling
492 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
495 * VIC = 1280 x 720p: ignored if external config is used
496 * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
498 if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
500 else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
504 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
506 /* PR = No Repetition */
507 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
509 /* Line Number of End of Top Bar (lower 8 bits) */
510 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
512 /* Line Number of End of Top Bar (upper 8 bits) */
513 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
515 /* Line Number of Start of Bottom Bar (lower 8 bits) */
516 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
518 /* Line Number of Start of Bottom Bar (upper 8 bits) */
519 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
521 /* Pixel Number of End of Left Bar (lower 8 bits) */
522 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
524 /* Pixel Number of End of Left Bar (upper 8 bits) */
525 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
527 /* Pixel Number of Start of Right Bar (lower 8 bits) */
528 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
530 /* Pixel Number of Start of Right Bar (upper 8 bits) */
531 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
535 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
537 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
539 /* Audio InfoFrame */
540 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
542 /* Packet Type = 0x84 */
543 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
545 /* Version Number = 0x01 */
546 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
548 /* 0 Length = 10 (0x0A) */
549 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
552 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
554 /* Audio Channel Count = Refer to Stream Header */
555 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
557 /* Refer to Stream Header */
558 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
560 /* Format depends on coding type (i.e. CT0...CT3) */
561 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
563 /* Speaker Channel Allocation = Front Right + Front Left */
564 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
566 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
567 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
570 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
571 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
572 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
573 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
574 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
578 * sh_hdmi_configure() - Initialise HDMI for output
580 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
582 /* Configure video format */
583 sh_hdmi_video_config(hdmi);
585 /* Configure audio format */
586 sh_hdmi_audio_config(hdmi);
589 sh_hdmi_phy_config(hdmi);
591 /* Auxiliary Video Information (AVI) InfoFrame */
592 sh_hdmi_avi_infoframe_setup(hdmi);
594 /* Audio InfoFrame */
595 sh_hdmi_audio_infoframe_setup(hdmi);
598 * Control packet auto send with VSYNC control: auto send
599 * General control, Gamut metadata, ISRC, and ACP packets
601 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
606 /* PS mode b->d, reset PLLA and PLLB */
607 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
611 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
614 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
616 struct fb_var_screeninfo tmpvar;
617 /* TODO: When we are ready to use EDID, use this to fill &hdmi->var */
618 struct fb_var_screeninfo *var = &tmpvar;
619 const struct fb_videomode *mode, *found = NULL;
624 dev_dbg(hdmi->dev, "Read back EDID code:");
625 for (i = 0; i < 128; i++) {
626 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
629 printk(KERN_CONT "\n");
630 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
632 printk(KERN_CONT " %02X", edid[i]);
637 printk(KERN_CONT "\n");
640 fb_edid_to_monspecs(edid, &hdmi->monspec);
642 /* First look for an exact match */
643 for (i = 0, mode = hdmi->monspec.modedb; i < hdmi->monspec.modedb_len;
645 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
646 mode->left_margin, mode->xres,
647 mode->right_margin, mode->hsync_len,
648 mode->upper_margin, mode->yres,
649 mode->lower_margin, mode->vsync_len,
650 PICOS2KHZ(mode->pixclock));
651 if (!found && hdmi->info) {
652 fb_videomode_to_var(var, mode);
653 found = fb_match_mode(var, &hdmi->info->modelist);
655 * If an exact match found, we're good to bail out, but
656 * continue to print out all modes
662 * The monitor might also work with a mode, that is smaller, than one of
663 * its modes, use the first (default) one for this
665 if (!found && hdmi->info && hdmi->monspec.modedb_len) {
666 struct fb_modelist *modelist;
667 unsigned int min_err = UINT_MAX, err;
668 const struct fb_videomode *mon_mode = hdmi->monspec.modedb;
670 list_for_each_entry(modelist, &hdmi->info->modelist, list) {
671 mode = &modelist->mode;
672 dev_dbg(hdmi->dev, "matching %ux%u to %ux%u\n", mode->xres, mode->yres,
673 mon_mode->xres, mon_mode->yres);
674 if (mode->xres <= mon_mode->xres && mode->yres <= mon_mode->yres) {
675 err = mon_mode->xres - mode->xres + mon_mode->yres - mode->yres;
688 /* Nothing suitable specified by the platform: use monitor's first mode */
689 if (!found && hdmi->monspec.modedb_len)
690 found = hdmi->monspec.modedb;
692 /* No valid timing info in EDID - last resort: use platform default mode */
693 if (!found && hdmi->info) {
694 struct fb_modelist *modelist = list_entry(hdmi->info->modelist.next,
695 struct fb_modelist, list);
696 found = &modelist->mode;
699 /* No cookie today */
703 dev_dbg(hdmi->dev, "best \"%s\" %ux%u@%ups\n", found->name,
704 found->xres, found->yres, found->pixclock);
706 if ((found->xres == 720 && found->yres == 480) ||
707 (found->xres == 1280 && found->yres == 720) ||
708 (found->xres == 1920 && found->yres == 1080))
709 hdmi->preprogrammed_mode = true;
711 hdmi->preprogrammed_mode = false;
713 fb_videomode_to_var(&hdmi->var, found);
714 sh_hdmi_external_video_param(hdmi);
719 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
721 struct sh_hdmi *hdmi = dev_id;
722 u8 status1, status2, mask1, mask2;
724 /* mode_b and PLLA and PLLB reset */
725 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
727 /* How long shall reset be held? */
730 /* mode_b and PLLA and PLLB reset release */
731 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
733 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
734 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
736 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
737 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
739 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
740 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
741 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
743 if (printk_ratelimit())
744 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
745 irq, status1, mask1, status2, mask2);
747 if (!((status1 & mask1) | (status2 & mask2))) {
749 } else if (status1 & 0xc0) {
752 /* Datasheet specifies 10ms... */
755 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
756 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
757 /* Check, if hot plug & MSENS pin status are both high */
758 if ((msens & 0xC0) == 0xC0) {
759 /* Display plug in */
760 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
762 /* Set EDID word address */
763 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
764 /* Set EDID segment pointer */
765 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
766 /* Enable EDID interrupt */
767 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
768 } else if (!(status1 & 0x80)) {
769 /* Display unplug, beware multiple interrupts */
770 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
771 schedule_delayed_work(&hdmi->edid_work, 0);
773 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
774 /* display_off will switch back to mode_a */
776 } else if (status1 & 2) {
777 /* EDID error interrupt: retry */
778 /* Set EDID word address */
779 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
780 /* Set EDID segment pointer */
781 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
782 } else if (status1 & 4) {
783 /* Disable EDID interrupt */
784 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
785 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
786 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
792 /* locking: called with info->lock held, or before register_framebuffer() */
793 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
796 * info is guaranteed to be valid, when we are called, because our
797 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
799 struct sh_hdmi *hdmi = arg;
800 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
801 struct sh_mobile_lcdc_chan *ch = info->par;
803 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
804 pdata->lcd_dev, info->state);
806 /* No need to lock */
810 * hp_state can be set to
811 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
812 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
813 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
815 switch (hdmi->hp_state) {
816 case HDMI_HOTPLUG_EDID_DONE:
817 /* PS mode d->e. All functions are active */
818 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
819 dev_dbg(hdmi->dev, "HDMI running\n");
821 case HDMI_HOTPLUG_DISCONNECTED:
822 info->state = FBINFO_STATE_SUSPENDED;
824 hdmi->var = ch->display_var;
828 /* locking: called with info->lock held */
829 static void sh_hdmi_display_off(void *arg)
831 struct sh_hdmi *hdmi = arg;
832 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
834 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
836 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
839 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
841 struct fb_info *info = hdmi->info;
842 struct sh_mobile_lcdc_chan *ch = info->par;
843 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
844 struct fb_videomode mode1, mode2;
846 fb_var_to_videomode(&mode1, old_var);
847 fb_var_to_videomode(&mode2, new_var);
849 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
850 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
852 if (fb_mode_is_equal(&mode1, &mode2))
855 dev_dbg(info->dev, "Switching %u -> %u lines\n",
856 mode1.yres, mode2.yres);
863 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
864 * @hdmi: driver context
865 * @pixclock: pixel clock period in picoseconds
866 * return: configured positive rate if successful
867 * 0 if couldn't set the rate, but managed to enable the clock
868 * negative error, if couldn't enable the clock
870 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
875 rate = PICOS2KHZ(pixclock) * 1000;
876 rate = clk_round_rate(hdmi->hdmi_clk, rate);
878 ret = clk_set_rate(hdmi->hdmi_clk, rate);
880 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
883 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
887 dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
890 ret = clk_enable(hdmi->hdmi_clk);
892 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
899 /* Hotplug interrupt occurred, read EDID */
900 static void sh_hdmi_edid_work_fn(struct work_struct *work)
902 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
903 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
904 struct sh_mobile_lcdc_chan *ch;
907 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
908 pdata->lcd_dev, hdmi->hp_state);
913 mutex_lock(&hdmi->mutex);
915 if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
916 /* A device has been plugged in */
917 pm_runtime_get_sync(hdmi->dev);
919 ret = sh_hdmi_read_edid(hdmi);
923 /* Reconfigure the clock */
924 clk_disable(hdmi->hdmi_clk);
925 ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
930 sh_hdmi_configure(hdmi);
931 /* Switched to another (d) power-save mode */
937 ch = hdmi->info->par;
939 acquire_console_sem();
942 if (!sh_hdmi_must_reconfigure(hdmi) &&
943 hdmi->info->state == FBINFO_STATE_RUNNING) {
945 * First activation with the default monitor - just turn
946 * on, if we run a resume here, the logo disappears
948 if (lock_fb_info(hdmi->info)) {
949 sh_hdmi_display_on(hdmi, hdmi->info);
950 unlock_fb_info(hdmi->info);
953 /* New monitor or have to wake up */
954 fb_set_suspend(hdmi->info, 0);
957 release_console_sem();
963 acquire_console_sem();
965 /* HDMI disconnect */
966 fb_set_suspend(hdmi->info, 1);
968 release_console_sem();
969 pm_runtime_put(hdmi->dev);
970 fb_destroy_modedb(hdmi->monspec.modedb);
975 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
976 mutex_unlock(&hdmi->mutex);
978 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
981 static int sh_hdmi_notify(struct notifier_block *nb,
982 unsigned long action, void *data);
984 static struct notifier_block sh_hdmi_notifier = {
985 .notifier_call = sh_hdmi_notify,
988 static int sh_hdmi_notify(struct notifier_block *nb,
989 unsigned long action, void *data)
991 struct fb_event *event = data;
992 struct fb_info *info = event->info;
993 struct sh_mobile_lcdc_chan *ch = info->par;
994 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
995 struct sh_hdmi *hdmi = board_cfg->board_data;
997 if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1001 case FB_EVENT_FB_REGISTERED:
1002 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1004 case FB_EVENT_FB_UNREGISTERED:
1006 * We are called from unregister_framebuffer() with the
1007 * info->lock held. This is bad for us, because we can race with
1008 * the scheduled work, which has to call fb_set_suspend(), which
1009 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1010 * cannot take and hold info->lock for the whole function
1011 * duration. Using an additional lock creates a classical AB-BA
1012 * lock up. Therefore, we have to release the info->lock
1013 * temporarily, synchronise with the work queue and re-acquire
1016 unlock_fb_info(hdmi->info);
1017 mutex_lock(&hdmi->mutex);
1019 mutex_unlock(&hdmi->mutex);
1020 lock_fb_info(hdmi->info);
1026 static int __init sh_hdmi_probe(struct platform_device *pdev)
1028 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1029 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 struct sh_mobile_lcdc_board_cfg *board_cfg;
1031 int irq = platform_get_irq(pdev, 0), ret;
1032 struct sh_hdmi *hdmi;
1035 if (!res || !pdata || irq < 0)
1038 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1040 dev_err(&pdev->dev, "Cannot allocate device data\n");
1044 mutex_init(&hdmi->mutex);
1045 hdmi->dev = &pdev->dev;
1047 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1048 if (IS_ERR(hdmi->hdmi_clk)) {
1049 ret = PTR_ERR(hdmi->hdmi_clk);
1050 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1054 rate = sh_hdmi_clk_configure(hdmi, pdata->lcd_chan->lcd_cfg[0].pixclock);
1060 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1062 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1063 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1068 hdmi->base = ioremap(res->start, resource_size(res));
1070 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1075 platform_set_drvdata(pdev, hdmi);
1077 /* Product and revision IDs are 0 in sh-mobile version */
1078 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1079 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1081 /* Set up LCDC callbacks */
1082 board_cfg = &pdata->lcd_chan->board_cfg;
1083 board_cfg->owner = THIS_MODULE;
1084 board_cfg->board_data = hdmi;
1085 board_cfg->display_on = sh_hdmi_display_on;
1086 board_cfg->display_off = sh_hdmi_display_off;
1088 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1090 pm_runtime_enable(&pdev->dev);
1091 pm_runtime_resume(&pdev->dev);
1093 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1094 dev_name(&pdev->dev), hdmi);
1096 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1103 pm_runtime_disable(&pdev->dev);
1104 iounmap(hdmi->base);
1106 release_mem_region(res->start, resource_size(res));
1108 clk_disable(hdmi->hdmi_clk);
1110 clk_put(hdmi->hdmi_clk);
1112 mutex_destroy(&hdmi->mutex);
1118 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1120 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1121 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1122 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1124 int irq = platform_get_irq(pdev, 0);
1126 board_cfg->display_on = NULL;
1127 board_cfg->display_off = NULL;
1128 board_cfg->board_data = NULL;
1129 board_cfg->owner = NULL;
1131 /* No new work will be scheduled, wait for running ISR */
1132 free_irq(irq, hdmi);
1133 /* Wait for already scheduled work */
1134 cancel_delayed_work_sync(&hdmi->edid_work);
1135 pm_runtime_disable(&pdev->dev);
1136 clk_disable(hdmi->hdmi_clk);
1137 clk_put(hdmi->hdmi_clk);
1138 iounmap(hdmi->base);
1139 release_mem_region(res->start, resource_size(res));
1140 mutex_destroy(&hdmi->mutex);
1146 static struct platform_driver sh_hdmi_driver = {
1147 .remove = __exit_p(sh_hdmi_remove),
1149 .name = "sh-mobile-hdmi",
1153 static int __init sh_hdmi_init(void)
1155 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1157 module_init(sh_hdmi_init);
1159 static void __exit sh_hdmi_exit(void)
1161 platform_driver_unregister(&sh_hdmi_driver);
1163 module_exit(sh_hdmi_exit);
1165 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1166 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1167 MODULE_LICENSE("GPL v2");