drivers/video/pxafb.c

   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/kernel.h>
  28 #include <linux/sched.h>
  29 #include <linux/errno.h>
  30 #include <linux/string.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/slab.h>
  33 #include <linux/mm.h>
  34 #include <linux/fb.h>
  35 #include <linux/delay.h>
  36 #include <linux/init.h>
  37 #include <linux/ioport.h>
  38 #include <linux/cpufreq.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/clk.h>
  42 #include <linux/err.h>
  43 #include <linux/completion.h>
  44 #include <linux/mutex.h>
  45 #include <linux/kthread.h>
  46 #include <linux/freezer.h>
  47
  48 #include <mach/hardware.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/div64.h>
  52 #include <mach/pxa-regs.h>
  53 #include <mach/bitfield.h>
  54 #include <mach/pxafb.h>
  55
  56 /*
  57  * Complain if VAR is out of range.
  58  */
  59 #define DEBUG_VAR 1
  60
  61 #include "pxafb.h"
  62
  63 /* Bits which should not be set in machine configuration structures */
  64 #define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
  65                                          LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
  66                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
  67
  68 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
  69                                          LCCR3_PCD | LCCR3_BPP)
  70
  71 static int pxafb_activate_var(struct fb_var_screeninfo *var,
  72                                 struct pxafb_info *);
  73 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  74 static void setup_base_frame(struct pxafb_info *fbi, int branch);
  75
  76 static unsigned long video_mem_size = 0;
  77
  78 static inline unsigned long
  79 lcd_readl(struct pxafb_info *fbi, unsigned int off)
  80 {
  81         return __raw_readl(fbi->mmio_base + off);
  82 }
  83
  84 static inline void
  85 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
  86 {
  87         __raw_writel(val, fbi->mmio_base + off);
  88 }
  89
  90 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  91 {
  92         unsigned long flags;
  93
  94         local_irq_save(flags);
  95         /*
  96          * We need to handle two requests being made at the same time.
  97          * There are two important cases:
  98          *  1. When we are changing VT (C_REENABLE) while unblanking
  99          *     (C_ENABLE) We must perform the unblanking, which will
 100          *     do our REENABLE for us.
 101          *  2. When we are blanking, but immediately unblank before
 102          *     we have blanked.  We do the "REENABLE" thing here as
 103          *     well, just to be sure.
 104          */
 105         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
 106                 state = (u_int) -1;
 107         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
 108                 state = C_REENABLE;
 109
 110         if (state != (u_int)-1) {
 111                 fbi->task_state = state;
 112                 schedule_work(&fbi->task);
 113         }
 114         local_irq_restore(flags);
 115 }
 116
 117 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
 118 {
 119         chan &= 0xffff;
 120         chan >>= 16 - bf->length;
 121         return chan << bf->offset;
 122 }
 123
 124 static int
 125 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 126                        u_int trans, struct fb_info *info)
 127 {
 128         struct pxafb_info *fbi = (struct pxafb_info *)info;
 129         u_int val;
 130
 131         if (regno >= fbi->palette_size)
 132                 return 1;
 133
 134         if (fbi->fb.var.grayscale) {
 135                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
 136                 return 0;
 137         }
 138
 139         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
 140         case LCCR4_PAL_FOR_0:
 141                 val  = ((red   >>  0) & 0xf800);
 142                 val |= ((green >>  5) & 0x07e0);
 143                 val |= ((blue  >> 11) & 0x001f);
 144                 fbi->palette_cpu[regno] = val;
 145                 break;
 146         case LCCR4_PAL_FOR_1:
 147                 val  = ((red   << 8) & 0x00f80000);
 148                 val |= ((green >> 0) & 0x0000fc00);
 149                 val |= ((blue  >> 8) & 0x000000f8);
 150                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 151                 break;
 152         case LCCR4_PAL_FOR_2:
 153                 val  = ((red   << 8) & 0x00fc0000);
 154                 val |= ((green >> 0) & 0x0000fc00);
 155                 val |= ((blue  >> 8) & 0x000000fc);
 156                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 157                 break;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int
 164 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 165                    u_int trans, struct fb_info *info)
 166 {
 167         struct pxafb_info *fbi = (struct pxafb_info *)info;
 168         unsigned int val;
 169         int ret = 1;
 170
 171         /*
 172          * If inverse mode was selected, invert all the colours
 173          * rather than the register number.  The register number
 174          * is what you poke into the framebuffer to produce the
 175          * colour you requested.
 176          */
 177         if (fbi->cmap_inverse) {
 178                 red   = 0xffff - red;
 179                 green = 0xffff - green;
 180                 blue  = 0xffff - blue;
 181         }
 182
 183         /*
 184          * If greyscale is true, then we convert the RGB value
 185          * to greyscale no matter what visual we are using.
 186          */
 187         if (fbi->fb.var.grayscale)
 188                 red = green = blue = (19595 * red + 38470 * green +
 189                                         7471 * blue) >> 16;
 190
 191         switch (fbi->fb.fix.visual) {
 192         case FB_VISUAL_TRUECOLOR:
 193                 /*
 194                  * 16-bit True Colour.  We encode the RGB value
 195                  * according to the RGB bitfield information.
 196                  */
 197                 if (regno < 16) {
 198                         u32 *pal = fbi->fb.pseudo_palette;
 199
 200                         val  = chan_to_field(red, &fbi->fb.var.red);
 201                         val |= chan_to_field(green, &fbi->fb.var.green);
 202                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 203
 204                         pal[regno] = val;
 205                         ret = 0;
 206                 }
 207                 break;
 208
 209         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 210         case FB_VISUAL_PSEUDOCOLOR:
 211                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 212                 break;
 213         }
 214
 215         return ret;
 216 }
 217
 218 /*
 219  *  pxafb_bpp_to_lccr3():
 220  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 221  */
 222 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
 223 {
 224         int ret = 0;
 225         switch (var->bits_per_pixel) {
 226         case 1:  ret = LCCR3_1BPP; break;
 227         case 2:  ret = LCCR3_2BPP; break;
 228         case 4:  ret = LCCR3_4BPP; break;
 229         case 8:  ret = LCCR3_8BPP; break;
 230         case 16: ret = LCCR3_16BPP; break;
 231         case 24:
 232                 switch (var->red.length + var->green.length +
 233                                 var->blue.length + var->transp.length) {
 234                 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
 235                 case 19: ret = LCCR3_19BPP_P; break;
 236                 }
 237                 break;
 238         case 32:
 239                 switch (var->red.length + var->green.length +
 240                                 var->blue.length + var->transp.length) {
 241                 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
 242                 case 19: ret = LCCR3_19BPP; break;
 243                 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
 244                 case 25: ret = LCCR3_25BPP; break;
 245                 }
 246                 break;
 247         }
 248         return ret;
 249 }
 250
 251 #ifdef CONFIG_CPU_FREQ
 252 /*
 253  *  pxafb_display_dma_period()
 254  *    Calculate the minimum period (in picoseconds) between two DMA
 255  *    requests for the LCD controller.  If we hit this, it means we're
 256  *    doing nothing but LCD DMA.
 257  */
 258 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 259 {
 260         /*
 261          * Period = pixclock * bits_per_byte * bytes_per_transfer
 262          *              / memory_bits_per_pixel;
 263          */
 264         return var->pixclock * 8 * 16 / var->bits_per_pixel;
 265 }
 266 #endif
 267
 268 /*
 269  * Select the smallest mode that allows the desired resolution to be
 270  * displayed. If desired parameters can be rounded up.
 271  */
 272 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
 273                                              struct fb_var_screeninfo *var)
 274 {
 275         struct pxafb_mode_info *mode = NULL;
 276         struct pxafb_mode_info *modelist = mach->modes;
 277         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
 278         unsigned int i;
 279
 280         for (i = 0; i < mach->num_modes; i++) {
 281                 if (modelist[i].xres >= var->xres &&
 282                     modelist[i].yres >= var->yres &&
 283                     modelist[i].xres < best_x &&
 284                     modelist[i].yres < best_y &&
 285                     modelist[i].bpp >= var->bits_per_pixel) {
 286                         best_x = modelist[i].xres;
 287                         best_y = modelist[i].yres;
 288                         mode = &modelist[i];
 289                 }
 290         }
 291
 292         return mode;
 293 }
 294
 295 static void pxafb_setmode(struct fb_var_screeninfo *var,
 296                           struct pxafb_mode_info *mode)
 297 {
 298         var->xres               = mode->xres;
 299         var->yres               = mode->yres;
 300         var->bits_per_pixel     = mode->bpp;
 301         var->pixclock           = mode->pixclock;
 302         var->hsync_len          = mode->hsync_len;
 303         var->left_margin        = mode->left_margin;
 304         var->right_margin       = mode->right_margin;
 305         var->vsync_len          = mode->vsync_len;
 306         var->upper_margin       = mode->upper_margin;
 307         var->lower_margin       = mode->lower_margin;
 308         var->sync               = mode->sync;
 309         var->grayscale          = mode->cmap_greyscale;
 310 }
 311
 312 /*
 313  *  pxafb_check_var():
 314  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 315  *    if it's too big, return -EINVAL.
 316  *
 317  *    Round up in the following order: bits_per_pixel, xres,
 318  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 319  *    bitfields, horizontal timing, vertical timing.
 320  */
 321 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 322 {
 323         struct pxafb_info *fbi = (struct pxafb_info *)info;
 324         struct pxafb_mach_info *inf = fbi->dev->platform_data;
 325
 326         if (var->xres < MIN_XRES)
 327                 var->xres = MIN_XRES;
 328         if (var->yres < MIN_YRES)
 329                 var->yres = MIN_YRES;
 330
 331         if (inf->fixed_modes) {
 332                 struct pxafb_mode_info *mode;
 333
 334                 mode = pxafb_getmode(inf, var);
 335                 if (!mode)
 336                         return -EINVAL;
 337                 pxafb_setmode(var, mode);
 338         } else {
 339                 if (var->xres > inf->modes->xres)
 340                         return -EINVAL;
 341                 if (var->yres > inf->modes->yres)
 342                         return -EINVAL;
 343                 if (var->bits_per_pixel > inf->modes->bpp)
 344                         return -EINVAL;
 345         }
 346
 347         /* we don't support xpan, force xres_virtual to be equal to xres */
 348         var->xres_virtual = var->xres;
 349
 350         if (var->accel_flags & FB_ACCELF_TEXT)
 351                 var->yres_virtual = fbi->fb.fix.smem_len /
 352                         (var->xres_virtual * var->bits_per_pixel / 8);
 353         else
 354                 var->yres_virtual = max(var->yres_virtual, var->yres);
 355
 356         /*
 357          * Setup the RGB parameters for this display.
 358          *
 359          * The pixel packing format is described on page 7-11 of the
 360          * PXA2XX Developer's Manual.
 361          */
 362         if (var->bits_per_pixel == 16) {
 363                 var->red.offset   = 11; var->red.length   = 5;
 364                 var->green.offset = 5;  var->green.length = 6;
 365                 var->blue.offset  = 0;  var->blue.length  = 5;
 366                 var->transp.offset = var->transp.length = 0;
 367         } else if (var->bits_per_pixel > 16) {
 368                 struct pxafb_mode_info *mode;
 369
 370                 mode = pxafb_getmode(inf, var);
 371                 if (!mode)
 372                         return -EINVAL;
 373
 374                 switch (mode->depth) {
 375                 case 18: /* RGB666 */
 376                         var->transp.offset = var->transp.length     = 0;
 377                         var->red.offset    = 12; var->red.length    = 6;
 378                         var->green.offset  = 6;  var->green.length  = 6;
 379                         var->blue.offset   = 0;  var->blue.length   = 6;
 380                         break;
 381                 case 19: /* RGBT666 */
 382                         var->transp.offset = 18; var->transp.length = 1;
 383                         var->red.offset    = 12; var->red.length    = 6;
 384                         var->green.offset  = 6;  var->green.length  = 6;
 385                         var->blue.offset   = 0;  var->blue.length   = 6;
 386                         break;
 387                 case 24: /* RGB888 */
 388                         var->transp.offset = var->transp.length     = 0;
 389                         var->red.offset    = 16; var->red.length    = 8;
 390                         var->green.offset  = 8;  var->green.length  = 8;
 391                         var->blue.offset   = 0;  var->blue.length   = 8;
 392                         break;
 393                 case 25: /* RGBT888 */
 394                         var->transp.offset = 24; var->transp.length = 1;
 395                         var->red.offset    = 16; var->red.length    = 8;
 396                         var->green.offset  = 8;  var->green.length  = 8;
 397                         var->blue.offset   = 0;  var->blue.length   = 8;
 398                         break;
 399                 default:
 400                         return -EINVAL;
 401                 }
 402         } else {
 403                 var->red.offset = var->green.offset = 0;
 404                 var->blue.offset = var->transp.offset = 0;
 405                 var->red.length   = 8;
 406                 var->green.length = 8;
 407                 var->blue.length  = 8;
 408                 var->transp.length = 0;
 409         }
 410
 411 #ifdef CONFIG_CPU_FREQ
 412         pr_debug("pxafb: dma period = %d ps\n",
 413                  pxafb_display_dma_period(var));
 414 #endif
 415
 416         return 0;
 417 }
 418
 419 static inline void pxafb_set_truecolor(u_int is_true_color)
 420 {
 421         /* do your machine-specific setup if needed */
 422 }
 423
 424 /*
 425  * pxafb_set_par():
 426  *      Set the user defined part of the display for the specified console
 427  */
 428 static int pxafb_set_par(struct fb_info *info)
 429 {
 430         struct pxafb_info *fbi = (struct pxafb_info *)info;
 431         struct fb_var_screeninfo *var = &info->var;
 432
 433         if (var->bits_per_pixel >= 16)
 434                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 435         else if (!fbi->cmap_static)
 436                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 437         else {
 438                 /*
 439                  * Some people have weird ideas about wanting static
 440                  * pseudocolor maps.  I suspect their user space
 441                  * applications are broken.
 442                  */
 443                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 444         }
 445
 446         fbi->fb.fix.line_length = var->xres_virtual *
 447                                   var->bits_per_pixel / 8;
 448         if (var->bits_per_pixel >= 16)
 449                 fbi->palette_size = 0;
 450         else
 451                 fbi->palette_size = var->bits_per_pixel == 1 ?
 452                                         4 : 1 << var->bits_per_pixel;
 453
 454         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
 455
 456         /*
 457          * Set (any) board control register to handle new color depth
 458          */
 459         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
 460
 461         if (fbi->fb.var.bits_per_pixel >= 16)
 462                 fb_dealloc_cmap(&fbi->fb.cmap);
 463         else
 464                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 465
 466         pxafb_activate_var(var, fbi);
 467
 468         return 0;
 469 }
 470
 471 static int pxafb_pan_display(struct fb_var_screeninfo *var,
 472                              struct fb_info *info)
 473 {
 474         struct pxafb_info *fbi = (struct pxafb_info *)info;
 475         int dma = DMA_MAX + DMA_BASE;
 476
 477         if (fbi->state != C_ENABLE)
 478                 return 0;
 479
 480         setup_base_frame(fbi, 1);
 481
 482         if (fbi->lccr0 & LCCR0_SDS)
 483                 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
 484
 485         lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
 486         return 0;
 487 }
 488
 489 /*
 490  * pxafb_blank():
 491  *      Blank the display by setting all palette values to zero.  Note, the
 492  *      16 bpp mode does not really use the palette, so this will not
 493  *      blank the display in all modes.
 494  */
 495 static int pxafb_blank(int blank, struct fb_info *info)
 496 {
 497         struct pxafb_info *fbi = (struct pxafb_info *)info;
 498         int i;
 499
 500         switch (blank) {
 501         case FB_BLANK_POWERDOWN:
 502         case FB_BLANK_VSYNC_SUSPEND:
 503         case FB_BLANK_HSYNC_SUSPEND:
 504         case FB_BLANK_NORMAL:
 505                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 506                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 507                         for (i = 0; i < fbi->palette_size; i++)
 508                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 509
 510                 pxafb_schedule_work(fbi, C_DISABLE);
 511                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 512                 break;
 513
 514         case FB_BLANK_UNBLANK:
 515                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 516                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 517                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 518                         fb_set_cmap(&fbi->fb.cmap, info);
 519                 pxafb_schedule_work(fbi, C_ENABLE);
 520         }
 521         return 0;
 522 }
 523
 524 static struct fb_ops pxafb_ops = {
 525         .owner          = THIS_MODULE,
 526         .fb_check_var   = pxafb_check_var,
 527         .fb_set_par     = pxafb_set_par,
 528         .fb_pan_display = pxafb_pan_display,
 529         .fb_setcolreg   = pxafb_setcolreg,
 530         .fb_fillrect    = cfb_fillrect,
 531         .fb_copyarea    = cfb_copyarea,
 532         .fb_imageblit   = cfb_imageblit,
 533         .fb_blank       = pxafb_blank,
 534 };
 535
 536 /*
 537  * Calculate the PCD value from the clock rate (in picoseconds).
 538  * We take account of the PPCR clock setting.
 539  * From PXA Developer's Manual:
 540  *
 541  *   PixelClock =      LCLK
 542  *                -------------
 543  *                2 ( PCD + 1 )
 544  *
 545  *   PCD =      LCLK
 546  *         ------------- - 1
 547  *         2(PixelClock)
 548  *
 549  * Where:
 550  *   LCLK = LCD/Memory Clock
 551  *   PCD = LCCR3[7:0]
 552  *
 553  * PixelClock here is in Hz while the pixclock argument given is the
 554  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
 555  *
 556  * The function get_lclk_frequency_10khz returns LCLK in units of
 557  * 10khz. Calling the result of this function lclk gives us the
 558  * following
 559  *
 560  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
 561  *          -------------------------------------- - 1
 562  *                          2
 563  *
 564  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
 565  */
 566 static inline unsigned int get_pcd(struct pxafb_info *fbi,
 567                                    unsigned int pixclock)
 568 {
 569         unsigned long long pcd;
 570
 571         /* FIXME: Need to take into account Double Pixel Clock mode
 572          * (DPC) bit? or perhaps set it based on the various clock
 573          * speeds */
 574         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
 575         pcd *= pixclock;
 576         do_div(pcd, 100000000 * 2);
 577         /* no need for this, since we should subtract 1 anyway. they cancel */
 578         /* pcd += 1; */ /* make up for integer math truncations */
 579         return (unsigned int)pcd;
 580 }
 581
 582 /*
 583  * Some touchscreens need hsync information from the video driver to
 584  * function correctly. We export it here.  Note that 'hsync_time' and
 585  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
 586  * of the hsync period in seconds.
 587  */
 588 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
 589 {
 590         unsigned long htime;
 591
 592         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
 593                 fbi->hsync_time = 0;
 594                 return;
 595         }
 596
 597         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
 598
 599         fbi->hsync_time = htime;
 600 }
 601
 602 unsigned long pxafb_get_hsync_time(struct device *dev)
 603 {
 604         struct pxafb_info *fbi = dev_get_drvdata(dev);
 605
 606         /* If display is blanked/suspended, hsync isn't active */
 607         if (!fbi || (fbi->state != C_ENABLE))
 608                 return 0;
 609
 610         return fbi->hsync_time;
 611 }
 612 EXPORT_SYMBOL(pxafb_get_hsync_time);
 613
 614 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
 615                 unsigned int offset, size_t size)
 616 {
 617         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
 618         unsigned int dma_desc_off, pal_desc_off;
 619
 620         if (dma < 0 || dma >= DMA_MAX * 2)
 621                 return -EINVAL;
 622
 623         dma_desc = &fbi->dma_buff->dma_desc[dma];
 624         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
 625
 626         dma_desc->fsadr = fbi->video_mem_phys + offset;
 627         dma_desc->fidr  = 0;
 628         dma_desc->ldcmd = size;
 629
 630         if (pal < 0 || pal >= PAL_MAX * 2) {
 631                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
 632                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
 633         } else {
 634                 pal_desc = &fbi->dma_buff->pal_desc[pal];
 635                 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
 636
 637                 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
 638                 pal_desc->fidr  = 0;
 639
 640                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
 641                         pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
 642                 else
 643                         pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
 644
 645                 pal_desc->ldcmd |= LDCMD_PAL;
 646
 647                 /* flip back and forth between palette and frame buffer */
 648                 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
 649                 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
 650                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
 651         }
 652
 653         return 0;
 654 }
 655
 656 static void setup_base_frame(struct pxafb_info *fbi, int branch)
 657 {
 658         struct fb_var_screeninfo *var = &fbi->fb.var;
 659         struct fb_fix_screeninfo *fix = &fbi->fb.fix;
 660         unsigned int nbytes, offset;
 661         int dma, pal, bpp = var->bits_per_pixel;
 662
 663         dma = DMA_BASE + (branch ? DMA_MAX : 0);
 664         pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
 665
 666         nbytes = fix->line_length * var->yres;
 667         offset = fix->line_length * var->yoffset;
 668
 669         if (fbi->lccr0 & LCCR0_SDS) {
 670                 nbytes = nbytes / 2;
 671                 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
 672         }
 673
 674         setup_frame_dma(fbi, dma, pal, offset, nbytes);
 675 }
 676
 677 #ifdef CONFIG_FB_PXA_SMARTPANEL
 678 static int setup_smart_dma(struct pxafb_info *fbi)
 679 {
 680         struct pxafb_dma_descriptor *dma_desc;
 681         unsigned long dma_desc_off, cmd_buff_off;
 682
 683         dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
 684         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
 685         cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
 686
 687         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
 688         dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
 689         dma_desc->fidr  = 0;
 690         dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
 691
 692         fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
 693         return 0;
 694 }
 695
 696 int pxafb_smart_flush(struct fb_info *info)
 697 {
 698         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 699         uint32_t prsr;
 700         int ret = 0;
 701
 702         /* disable controller until all registers are set up */
 703         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
 704
 705         /* 1. make it an even number of commands to align on 32-bit boundary
 706          * 2. add the interrupt command to the end of the chain so we can
 707          *    keep track of the end of the transfer
 708          */
 709
 710         while (fbi->n_smart_cmds & 1)
 711                 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
 712
 713         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
 714         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
 715         setup_smart_dma(fbi);
 716
 717         /* continue to execute next command */
 718         prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
 719         lcd_writel(fbi, PRSR, prsr);
 720
 721         /* stop the processor in case it executed "wait for sync" cmd */
 722         lcd_writel(fbi, CMDCR, 0x0001);
 723
 724         /* don't send interrupts for fifo underruns on channel 6 */
 725         lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
 726
 727         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
 728         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
 729         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
 730         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
 731         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
 732
 733         /* begin sending */
 734         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
 735
 736         if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
 737                 pr_warning("%s: timeout waiting for command done\n",
 738                                 __func__);
 739                 ret = -ETIMEDOUT;
 740         }
 741
 742         /* quick disable */
 743         prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
 744         lcd_writel(fbi, PRSR, prsr);
 745         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
 746         lcd_writel(fbi, FDADR6, 0);
 747         fbi->n_smart_cmds = 0;
 748         return ret;
 749 }
 750
 751 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
 752 {
 753         int i;
 754         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 755
 756         for (i = 0; i < n_cmds; i++, cmds++) {
 757                 /* if it is a software delay, flush and delay */
 758                 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
 759                         pxafb_smart_flush(info);
 760                         mdelay(*cmds & 0xff);
 761                         continue;
 762                 }
 763
 764                 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
 765                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
 766                         pxafb_smart_flush(info);
 767
 768                 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
 769         }
 770
 771         return 0;
 772 }
 773
 774 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
 775 {
 776         unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
 777         return (t == 0) ? 1 : t;
 778 }
 779
 780 static void setup_smart_timing(struct pxafb_info *fbi,
 781                                 struct fb_var_screeninfo *var)
 782 {
 783         struct pxafb_mach_info *inf = fbi->dev->platform_data;
 784         struct pxafb_mode_info *mode = &inf->modes[0];
 785         unsigned long lclk = clk_get_rate(fbi->clk);
 786         unsigned t1, t2, t3, t4;
 787
 788         t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
 789         t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
 790         t3 = mode->op_hold_time;
 791         t4 = mode->cmd_inh_time;
 792
 793         fbi->reg_lccr1 =
 794                 LCCR1_DisWdth(var->xres) |
 795                 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
 796                 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
 797                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
 798
 799         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
 800         fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
 801         fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
 802         fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
 803
 804         /* FIXME: make this configurable */
 805         fbi->reg_cmdcr = 1;
 806 }
 807
 808 static int pxafb_smart_thread(void *arg)
 809 {
 810         struct pxafb_info *fbi = arg;
 811         struct pxafb_mach_info *inf = fbi->dev->platform_data;
 812
 813         if (!fbi || !inf->smart_update) {
 814                 pr_err("%s: not properly initialized, thread terminated\n",
 815                                 __func__);
 816                 return -EINVAL;
 817         }
 818
 819         pr_debug("%s(): task starting\n", __func__);
 820
 821         set_freezable();
 822         while (!kthread_should_stop()) {
 823
 824                 if (try_to_freeze())
 825                         continue;
 826
 827                 mutex_lock(&fbi->ctrlr_lock);
 828
 829                 if (fbi->state == C_ENABLE) {
 830                         inf->smart_update(&fbi->fb);
 831                         complete(&fbi->refresh_done);
 832                 }
 833
 834                 mutex_unlock(&fbi->ctrlr_lock);
 835
 836                 set_current_state(TASK_INTERRUPTIBLE);
 837                 schedule_timeout(30 * HZ / 1000);
 838         }
 839
 840         pr_debug("%s(): task ending\n", __func__);
 841         return 0;
 842 }
 843
 844 static int pxafb_smart_init(struct pxafb_info *fbi)
 845 {
 846         if (!(fbi->lccr0 & LCCR0_LCDT))
 847                 return 0;
 848
 849         fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
 850         fbi->n_smart_cmds = 0;
 851
 852         init_completion(&fbi->command_done);
 853         init_completion(&fbi->refresh_done);
 854
 855         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
 856                                         "lcd_refresh");
 857         if (IS_ERR(fbi->smart_thread)) {
 858                 pr_err("%s: unable to create kernel thread\n", __func__);
 859                 return PTR_ERR(fbi->smart_thread);
 860         }
 861
 862         return 0;
 863 }
 864 #else
 865 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
 866 {
 867         return 0;
 868 }
 869
 870 int pxafb_smart_flush(struct fb_info *info)
 871 {
 872         return 0;
 873 }
 874
 875 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
 876 #endif /* CONFIG_FB_PXA_SMARTPANEL */
 877
 878 static void setup_parallel_timing(struct pxafb_info *fbi,
 879                                   struct fb_var_screeninfo *var)
 880 {
 881         unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
 882
 883         fbi->reg_lccr1 =
 884                 LCCR1_DisWdth(var->xres) +
 885                 LCCR1_HorSnchWdth(var->hsync_len) +
 886                 LCCR1_BegLnDel(var->left_margin) +
 887                 LCCR1_EndLnDel(var->right_margin);
 888
 889         /*
 890          * If we have a dual scan LCD, we need to halve
 891          * the YRES parameter.
 892          */
 893         lines_per_panel = var->yres;
 894         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
 895                 lines_per_panel /= 2;
 896
 897         fbi->reg_lccr2 =
 898                 LCCR2_DisHght(lines_per_panel) +
 899                 LCCR2_VrtSnchWdth(var->vsync_len) +
 900                 LCCR2_BegFrmDel(var->upper_margin) +
 901                 LCCR2_EndFrmDel(var->lower_margin);
 902
 903         fbi->reg_lccr3 = fbi->lccr3 |
 904                 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
 905                  LCCR3_HorSnchH : LCCR3_HorSnchL) |
 906                 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
 907                  LCCR3_VrtSnchH : LCCR3_VrtSnchL);
 908
 909         if (pcd) {
 910                 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
 911                 set_hsync_time(fbi, pcd);
 912         }
 913 }
 914
 915 /*
 916  * pxafb_activate_var():
 917  *      Configures LCD Controller based on entries in var parameter.
 918  *      Settings are only written to the controller if changes were made.
 919  */
 920 static int pxafb_activate_var(struct fb_var_screeninfo *var,
 921                               struct pxafb_info *fbi)
 922 {
 923         u_long flags;
 924
 925 #if DEBUG_VAR
 926         if (!(fbi->lccr0 & LCCR0_LCDT)) {
 927                 if (var->xres < 16 || var->xres > 1024)
 928                         printk(KERN_ERR "%s: invalid xres %d\n",
 929                                 fbi->fb.fix.id, var->xres);
 930                 switch (var->bits_per_pixel) {
 931                 case 1:
 932                 case 2:
 933                 case 4:
 934                 case 8:
 935                 case 16:
 936                 case 24:
 937                 case 32:
 938                         break;
 939                 default:
 940                         printk(KERN_ERR "%s: invalid bit depth %d\n",
 941                                fbi->fb.fix.id, var->bits_per_pixel);
 942                         break;
 943                 }
 944
 945                 if (var->hsync_len < 1 || var->hsync_len > 64)
 946                         printk(KERN_ERR "%s: invalid hsync_len %d\n",
 947                                 fbi->fb.fix.id, var->hsync_len);
 948                 if (var->left_margin < 1 || var->left_margin > 255)
 949                         printk(KERN_ERR "%s: invalid left_margin %d\n",
 950                                 fbi->fb.fix.id, var->left_margin);
 951                 if (var->right_margin < 1 || var->right_margin > 255)
 952                         printk(KERN_ERR "%s: invalid right_margin %d\n",
 953                                 fbi->fb.fix.id, var->right_margin);
 954                 if (var->yres < 1 || var->yres > 1024)
 955                         printk(KERN_ERR "%s: invalid yres %d\n",
 956                                 fbi->fb.fix.id, var->yres);
 957                 if (var->vsync_len < 1 || var->vsync_len > 64)
 958                         printk(KERN_ERR "%s: invalid vsync_len %d\n",
 959                                 fbi->fb.fix.id, var->vsync_len);
 960                 if (var->upper_margin < 0 || var->upper_margin > 255)
 961                         printk(KERN_ERR "%s: invalid upper_margin %d\n",
 962                                 fbi->fb.fix.id, var->upper_margin);
 963                 if (var->lower_margin < 0 || var->lower_margin > 255)
 964                         printk(KERN_ERR "%s: invalid lower_margin %d\n",
 965                                 fbi->fb.fix.id, var->lower_margin);
 966         }
 967 #endif
 968         /* Update shadow copy atomically */
 969         local_irq_save(flags);
 970
 971 #ifdef CONFIG_FB_PXA_SMARTPANEL
 972         if (fbi->lccr0 & LCCR0_LCDT)
 973                 setup_smart_timing(fbi, var);
 974         else
 975 #endif
 976                 setup_parallel_timing(fbi, var);
 977
 978         setup_base_frame(fbi, 0);
 979
 980         fbi->reg_lccr0 = fbi->lccr0 |
 981                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
 982                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
 983
 984         fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
 985
 986         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
 987         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
 988         local_irq_restore(flags);
 989
 990         /*
 991          * Only update the registers if the controller is enabled
 992          * and something has changed.
 993          */
 994         if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
 995             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
 996             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
 997             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
 998             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
 999             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1000                 pxafb_schedule_work(fbi, C_REENABLE);
1001
1002         return 0;
1003 }
1004
1005 /*
1006  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
1007  * Do not call them directly; set_ctrlr_state does the correct serialisation
1008  * to ensure that things happen in the right way 100% of time time.
1009  *      -- rmk
1010  */
1011 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1012 {
1013         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1014
1015         if (fbi->backlight_power)
1016                 fbi->backlight_power(on);
1017 }
1018
1019 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1020 {
1021         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1022
1023         if (fbi->lcd_power)
1024                 fbi->lcd_power(on, &fbi->fb.var);
1025 }
1026
1027 static void pxafb_enable_controller(struct pxafb_info *fbi)
1028 {
1029         pr_debug("pxafb: Enabling LCD controller\n");
1030         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1031         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1032         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1033         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1034         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1035         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1036
1037         /* enable LCD controller clock */
1038         clk_enable(fbi->clk);
1039
1040         if (fbi->lccr0 & LCCR0_LCDT)
1041                 return;
1042
1043         /* Sequence from 11.7.10 */
1044         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1045         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1046         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1047         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1048
1049         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1050         lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1051         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1052 }
1053
1054 static void pxafb_disable_controller(struct pxafb_info *fbi)
1055 {
1056         uint32_t lccr0;
1057
1058 #ifdef CONFIG_FB_PXA_SMARTPANEL
1059         if (fbi->lccr0 & LCCR0_LCDT) {
1060                 wait_for_completion_timeout(&fbi->refresh_done,
1061                                 200 * HZ / 1000);
1062                 return;
1063         }
1064 #endif
1065
1066         /* Clear LCD Status Register */
1067         lcd_writel(fbi, LCSR, 0xffffffff);
1068
1069         lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1070         lcd_writel(fbi, LCCR0, lccr0);
1071         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1072
1073         wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1074
1075         /* disable LCD controller clock */
1076         clk_disable(fbi->clk);
1077 }
1078
1079 /*
1080  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1081  */
1082 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1083 {
1084         struct pxafb_info *fbi = dev_id;
1085         unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1086
1087         if (lcsr & LCSR_LDD) {
1088                 lccr0 = lcd_readl(fbi, LCCR0);
1089                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1090                 complete(&fbi->disable_done);
1091         }
1092
1093 #ifdef CONFIG_FB_PXA_SMARTPANEL
1094         if (lcsr & LCSR_CMD_INT)
1095                 complete(&fbi->command_done);
1096 #endif
1097
1098         lcd_writel(fbi, LCSR, lcsr);
1099         return IRQ_HANDLED;
1100 }
1101
1102 /*
1103  * This function must be called from task context only, since it will
1104  * sleep when disabling the LCD controller, or if we get two contending
1105  * processes trying to alter state.
1106  */
1107 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1108 {
1109         u_int old_state;
1110
1111         mutex_lock(&fbi->ctrlr_lock);
1112
1113         old_state = fbi->state;
1114
1115         /*
1116          * Hack around fbcon initialisation.
1117          */
1118         if (old_state == C_STARTUP && state == C_REENABLE)
1119                 state = C_ENABLE;
1120
1121         switch (state) {
1122         case C_DISABLE_CLKCHANGE:
1123                 /*
1124                  * Disable controller for clock change.  If the
1125                  * controller is already disabled, then do nothing.
1126                  */
1127                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1128                         fbi->state = state;
1129                         /* TODO __pxafb_lcd_power(fbi, 0); */
1130                         pxafb_disable_controller(fbi);
1131                 }
1132                 break;
1133
1134         case C_DISABLE_PM:
1135         case C_DISABLE:
1136                 /*
1137                  * Disable controller
1138                  */
1139                 if (old_state != C_DISABLE) {
1140                         fbi->state = state;
1141                         __pxafb_backlight_power(fbi, 0);
1142                         __pxafb_lcd_power(fbi, 0);
1143                         if (old_state != C_DISABLE_CLKCHANGE)
1144                                 pxafb_disable_controller(fbi);
1145                 }
1146                 break;
1147
1148         case C_ENABLE_CLKCHANGE:
1149                 /*
1150                  * Enable the controller after clock change.  Only
1151                  * do this if we were disabled for the clock change.
1152                  */
1153                 if (old_state == C_DISABLE_CLKCHANGE) {
1154                         fbi->state = C_ENABLE;
1155                         pxafb_enable_controller(fbi);
1156                         /* TODO __pxafb_lcd_power(fbi, 1); */
1157                 }
1158                 break;
1159
1160         case C_REENABLE:
1161                 /*
1162                  * Re-enable the controller only if it was already
1163                  * enabled.  This is so we reprogram the control
1164                  * registers.
1165                  */
1166                 if (old_state == C_ENABLE) {
1167                         __pxafb_lcd_power(fbi, 0);
1168                         pxafb_disable_controller(fbi);
1169                         pxafb_enable_controller(fbi);
1170                         __pxafb_lcd_power(fbi, 1);
1171                 }
1172                 break;
1173
1174         case C_ENABLE_PM:
1175                 /*
1176                  * Re-enable the controller after PM.  This is not
1177                  * perfect - think about the case where we were doing
1178                  * a clock change, and we suspended half-way through.
1179                  */
1180                 if (old_state != C_DISABLE_PM)
1181                         break;
1182                 /* fall through */
1183
1184         case C_ENABLE:
1185                 /*
1186                  * Power up the LCD screen, enable controller, and
1187                  * turn on the backlight.
1188                  */
1189                 if (old_state != C_ENABLE) {
1190                         fbi->state = C_ENABLE;
1191                         pxafb_enable_controller(fbi);
1192                         __pxafb_lcd_power(fbi, 1);
1193                         __pxafb_backlight_power(fbi, 1);
1194                 }
1195                 break;
1196         }
1197         mutex_unlock(&fbi->ctrlr_lock);
1198 }
1199
1200 /*
1201  * Our LCD controller task (which is called when we blank or unblank)
1202  * via keventd.
1203  */
1204 static void pxafb_task(struct work_struct *work)
1205 {
1206         struct pxafb_info *fbi =
1207                 container_of(work, struct pxafb_info, task);
1208         u_int state = xchg(&fbi->task_state, -1);
1209
1210         set_ctrlr_state(fbi, state);
1211 }
1212
1213 #ifdef CONFIG_CPU_FREQ
1214 /*
1215  * CPU clock speed change handler.  We need to adjust the LCD timing
1216  * parameters when the CPU clock is adjusted by the power management
1217  * subsystem.
1218  *
1219  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1220  */
1221 static int
1222 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1223 {
1224         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1225         /* TODO struct cpufreq_freqs *f = data; */
1226         u_int pcd;
1227
1228         switch (val) {
1229         case CPUFREQ_PRECHANGE:
1230                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1231                 break;
1232
1233         case CPUFREQ_POSTCHANGE:
1234                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1235                 set_hsync_time(fbi, pcd);
1236                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1237                                   LCCR3_PixClkDiv(pcd);
1238                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1239                 break;
1240         }
1241         return 0;
1242 }
1243
1244 static int
1245 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1246 {
1247         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1248         struct fb_var_screeninfo *var = &fbi->fb.var;
1249         struct cpufreq_policy *policy = data;
1250
1251         switch (val) {
1252         case CPUFREQ_ADJUST:
1253         case CPUFREQ_INCOMPATIBLE:
1254                 pr_debug("min dma period: %d ps, "
1255                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1256                         policy->max);
1257                 /* TODO: fill in min/max values */
1258                 break;
1259         }
1260         return 0;
1261 }
1262 #endif
1263
1264 #ifdef CONFIG_PM
1265 /*
1266  * Power management hooks.  Note that we won't be called from IRQ context,
1267  * unlike the blank functions above, so we may sleep.
1268  */
1269 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1270 {
1271         struct pxafb_info *fbi = platform_get_drvdata(dev);
1272
1273         set_ctrlr_state(fbi, C_DISABLE_PM);
1274         return 0;
1275 }
1276
1277 static int pxafb_resume(struct platform_device *dev)
1278 {
1279         struct pxafb_info *fbi = platform_get_drvdata(dev);
1280
1281         set_ctrlr_state(fbi, C_ENABLE_PM);
1282         return 0;
1283 }
1284 #else
1285 #define pxafb_suspend   NULL
1286 #define pxafb_resume    NULL
1287 #endif
1288
1289 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1290 {
1291         int size = PAGE_ALIGN(fbi->video_mem_size);
1292
1293         fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1294         if (fbi->video_mem == NULL)
1295                 return -ENOMEM;
1296
1297         fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1298         fbi->video_mem_size = size;
1299
1300         fbi->fb.fix.smem_start  = fbi->video_mem_phys;
1301         fbi->fb.fix.smem_len    = fbi->video_mem_size;
1302         fbi->fb.screen_base     = fbi->video_mem;
1303
1304         return fbi->video_mem ? 0 : -ENOMEM;
1305 }
1306
1307 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1308                                    struct pxafb_mach_info *inf)
1309 {
1310         unsigned int lcd_conn = inf->lcd_conn;
1311         struct pxafb_mode_info *m;
1312         int i;
1313
1314         fbi->cmap_inverse       = inf->cmap_inverse;
1315         fbi->cmap_static        = inf->cmap_static;
1316
1317         switch (lcd_conn & LCD_TYPE_MASK) {
1318         case LCD_TYPE_MONO_STN:
1319                 fbi->lccr0 = LCCR0_CMS;
1320                 break;
1321         case LCD_TYPE_MONO_DSTN:
1322                 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1323                 break;
1324         case LCD_TYPE_COLOR_STN:
1325                 fbi->lccr0 = 0;
1326                 break;
1327         case LCD_TYPE_COLOR_DSTN:
1328                 fbi->lccr0 = LCCR0_SDS;
1329                 break;
1330         case LCD_TYPE_COLOR_TFT:
1331                 fbi->lccr0 = LCCR0_PAS;
1332                 break;
1333         case LCD_TYPE_SMART_PANEL:
1334                 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1335                 break;
1336         default:
1337                 /* fall back to backward compatibility way */
1338                 fbi->lccr0 = inf->lccr0;
1339                 fbi->lccr3 = inf->lccr3;
1340                 fbi->lccr4 = inf->lccr4;
1341                 goto decode_mode;
1342         }
1343
1344         if (lcd_conn == LCD_MONO_STN_8BPP)
1345                 fbi->lccr0 |= LCCR0_DPD;
1346
1347         fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1348
1349         fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1350         fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1351         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1352
1353 decode_mode:
1354         pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1355
1356         /* decide video memory size as follows:
1357          * 1. default to mode of maximum resolution
1358          * 2. allow platform to override
1359          * 3. allow module parameter to override
1360          */
1361         for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1362                 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1363                                 m->xres * m->yres * m->bpp / 8);
1364
1365         if (inf->video_mem_size > fbi->video_mem_size)
1366                 fbi->video_mem_size = inf->video_mem_size;
1367
1368         if (video_mem_size > fbi->video_mem_size)
1369                 fbi->video_mem_size = video_mem_size;
1370 }
1371
1372 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1373 {
1374         struct pxafb_info *fbi;
1375         void *addr;
1376         struct pxafb_mach_info *inf = dev->platform_data;
1377
1378         /* Alloc the pxafb_info and pseudo_palette in one step */
1379         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1380         if (!fbi)
1381                 return NULL;
1382
1383         memset(fbi, 0, sizeof(struct pxafb_info));
1384         fbi->dev = dev;
1385
1386         fbi->clk = clk_get(dev, "LCDCLK");
1387         if (IS_ERR(fbi->clk)) {
1388                 kfree(fbi);
1389                 return NULL;
1390         }
1391
1392         strcpy(fbi->fb.fix.id, PXA_NAME);
1393
1394         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1395         fbi->fb.fix.type_aux    = 0;
1396         fbi->fb.fix.xpanstep    = 0;
1397         fbi->fb.fix.ypanstep    = 1;
1398         fbi->fb.fix.ywrapstep   = 0;
1399         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1400
1401         fbi->fb.var.nonstd      = 0;
1402         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1403         fbi->fb.var.height      = -1;
1404         fbi->fb.var.width       = -1;
1405         fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1406         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1407
1408         fbi->fb.fbops           = &pxafb_ops;
1409         fbi->fb.flags           = FBINFO_DEFAULT;
1410         fbi->fb.node            = -1;
1411
1412         addr = fbi;
1413         addr = addr + sizeof(struct pxafb_info);
1414         fbi->fb.pseudo_palette  = addr;
1415
1416         fbi->state              = C_STARTUP;
1417         fbi->task_state         = (u_char)-1;
1418
1419         pxafb_decode_mach_info(fbi, inf);
1420
1421         init_waitqueue_head(&fbi->ctrlr_wait);
1422         INIT_WORK(&fbi->task, pxafb_task);
1423         mutex_init(&fbi->ctrlr_lock);
1424         init_completion(&fbi->disable_done);
1425
1426         return fbi;
1427 }
1428
1429 #ifdef CONFIG_FB_PXA_PARAMETERS
1430 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1431 {
1432         struct pxafb_mach_info *inf = dev->platform_data;
1433
1434         const char *name = this_opt+5;
1435         unsigned int namelen = strlen(name);
1436         int res_specified = 0, bpp_specified = 0;
1437         unsigned int xres = 0, yres = 0, bpp = 0;
1438         int yres_specified = 0;
1439         int i;
1440         for (i = namelen-1; i >= 0; i--) {
1441                 switch (name[i]) {
1442                 case '-':
1443                         namelen = i;
1444                         if (!bpp_specified && !yres_specified) {
1445                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1446                                 bpp_specified = 1;
1447                         } else
1448                                 goto done;
1449                         break;
1450                 case 'x':
1451                         if (!yres_specified) {
1452                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1453                                 yres_specified = 1;
1454                         } else
1455                                 goto done;
1456                         break;
1457                 case '0' ... '9':
1458                         break;
1459                 default:
1460                         goto done;
1461                 }
1462         }
1463         if (i < 0 && yres_specified) {
1464                 xres = simple_strtoul(name, NULL, 0);
1465                 res_specified = 1;
1466         }
1467 done:
1468         if (res_specified) {
1469                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1470                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1471         }
1472         if (bpp_specified)
1473                 switch (bpp) {
1474                 case 1:
1475                 case 2:
1476                 case 4:
1477                 case 8:
1478                 case 16:
1479                         inf->modes[0].bpp = bpp;
1480                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1481                         break;
1482                 default:
1483                         dev_err(dev, "Depth %d is not valid\n", bpp);
1484                         return -EINVAL;
1485                 }
1486         return 0;
1487 }
1488
1489 static int __devinit parse_opt(struct device *dev, char *this_opt)
1490 {
1491         struct pxafb_mach_info *inf = dev->platform_data;
1492         struct pxafb_mode_info *mode = &inf->modes[0];
1493         char s[64];
1494
1495         s[0] = '\0';
1496
1497         if (!strncmp(this_opt, "vmem:", 5)) {
1498                 video_mem_size = memparse(this_opt + 5, NULL);
1499         } else if (!strncmp(this_opt, "mode:", 5)) {
1500                 return parse_opt_mode(dev, this_opt);
1501         } else if (!strncmp(this_opt, "pixclock:", 9)) {
1502                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1503                 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1504         } else if (!strncmp(this_opt, "left:", 5)) {
1505                 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1506                 sprintf(s, "left: %u\n", mode->left_margin);
1507         } else if (!strncmp(this_opt, "right:", 6)) {
1508                 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1509                 sprintf(s, "right: %u\n", mode->right_margin);
1510         } else if (!strncmp(this_opt, "upper:", 6)) {
1511                 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1512                 sprintf(s, "upper: %u\n", mode->upper_margin);
1513         } else if (!strncmp(this_opt, "lower:", 6)) {
1514                 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1515                 sprintf(s, "lower: %u\n", mode->lower_margin);
1516         } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1517                 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1518                 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1519         } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1520                 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1521                 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1522         } else if (!strncmp(this_opt, "hsync:", 6)) {
1523                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1524                         sprintf(s, "hsync: Active Low\n");
1525                         mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1526                 } else {
1527                         sprintf(s, "hsync: Active High\n");
1528                         mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1529                 }
1530         } else if (!strncmp(this_opt, "vsync:", 6)) {
1531                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1532                         sprintf(s, "vsync: Active Low\n");
1533                         mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1534                 } else {
1535                         sprintf(s, "vsync: Active High\n");
1536                         mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1537                 }
1538         } else if (!strncmp(this_opt, "dpc:", 4)) {
1539                 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1540                         sprintf(s, "double pixel clock: false\n");
1541                         inf->lccr3 &= ~LCCR3_DPC;
1542                 } else {
1543                         sprintf(s, "double pixel clock: true\n");
1544                         inf->lccr3 |= LCCR3_DPC;
1545                 }
1546         } else if (!strncmp(this_opt, "outputen:", 9)) {
1547                 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1548                         sprintf(s, "output enable: active low\n");
1549                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1550                 } else {
1551                         sprintf(s, "output enable: active high\n");
1552                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1553                 }
1554         } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1555                 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1556                         sprintf(s, "pixel clock polarity: falling edge\n");
1557                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1558                 } else {
1559                         sprintf(s, "pixel clock polarity: rising edge\n");
1560                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1561                 }
1562         } else if (!strncmp(this_opt, "color", 5)) {
1563                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1564         } else if (!strncmp(this_opt, "mono", 4)) {
1565                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1566         } else if (!strncmp(this_opt, "active", 6)) {
1567                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1568         } else if (!strncmp(this_opt, "passive", 7)) {
1569                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1570         } else if (!strncmp(this_opt, "single", 6)) {
1571                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1572         } else if (!strncmp(this_opt, "dual", 4)) {
1573                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1574         } else if (!strncmp(this_opt, "4pix", 4)) {
1575                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1576         } else if (!strncmp(this_opt, "8pix", 4)) {
1577                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1578         } else {
1579                 dev_err(dev, "unknown option: %s\n", this_opt);
1580                 return -EINVAL;
1581         }
1582
1583         if (s[0] != '\0')
1584                 dev_info(dev, "override %s", s);
1585
1586         return 0;
1587 }
1588
1589 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1590 {
1591         char *this_opt;
1592         int ret;
1593
1594         if (!options || !*options)
1595                 return 0;
1596
1597         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1598
1599         /* could be made table driven or similar?... */
1600         while ((this_opt = strsep(&options, ",")) != NULL) {
1601                 ret = parse_opt(dev, this_opt);
1602                 if (ret)
1603                         return ret;
1604         }
1605         return 0;
1606 }
1607
1608 static char g_options[256] __devinitdata = "";
1609
1610 #ifndef MODULE
1611 static int __init pxafb_setup_options(void)
1612 {
1613         char *options = NULL;
1614
1615         if (fb_get_options("pxafb", &options))
1616                 return -ENODEV;
1617
1618         if (options)
1619                 strlcpy(g_options, options, sizeof(g_options));
1620
1621         return 0;
1622 }
1623 #else
1624 #define pxafb_setup_options()           (0)
1625
1626 module_param_string(options, g_options, sizeof(g_options), 0);
1627 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1628 #endif
1629
1630 #else
1631 #define pxafb_parse_options(...)        (0)
1632 #define pxafb_setup_options()           (0)
1633 #endif
1634
1635 #ifdef DEBUG_VAR
1636 /* Check for various illegal bit-combinations. Currently only
1637  * a warning is given. */
1638 static void __devinit pxafb_check_options(struct device *dev,
1639                                           struct pxafb_mach_info *inf)
1640 {
1641         if (inf->lcd_conn)
1642                 return;
1643
1644         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1645                 dev_warn(dev, "machine LCCR0 setting contains "
1646                                 "illegal bits: %08x\n",
1647                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1648         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1649                 dev_warn(dev, "machine LCCR3 setting contains "
1650                                 "illegal bits: %08x\n",
1651                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1652         if (inf->lccr0 & LCCR0_DPD &&
1653             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1654              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1655              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1656                 dev_warn(dev, "Double Pixel Data (DPD) mode is "
1657                                 "only valid in passive mono"
1658                                 " single panel mode\n");
1659         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1660             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1661                 dev_warn(dev, "Dual panel only valid in passive mode\n");
1662         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1663              (inf->modes->upper_margin || inf->modes->lower_margin))
1664                 dev_warn(dev, "Upper and lower margins must be 0 in "
1665                                 "passive mode\n");
1666 }
1667 #else
1668 #define pxafb_check_options(...)        do {} while (0)
1669 #endif
1670
1671 static int __devinit pxafb_probe(struct platform_device *dev)
1672 {
1673         struct pxafb_info *fbi;
1674         struct pxafb_mach_info *inf;
1675         struct resource *r;
1676         int irq, ret;
1677
1678         dev_dbg(&dev->dev, "pxafb_probe\n");
1679
1680         inf = dev->dev.platform_data;
1681         ret = -ENOMEM;
1682         fbi = NULL;
1683         if (!inf)
1684                 goto failed;
1685
1686         ret = pxafb_parse_options(&dev->dev, g_options);
1687         if (ret < 0)
1688                 goto failed;
1689
1690         pxafb_check_options(&dev->dev, inf);
1691
1692         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1693                         inf->modes->xres,
1694                         inf->modes->yres,
1695                         inf->modes->bpp);
1696         if (inf->modes->xres == 0 ||
1697             inf->modes->yres == 0 ||
1698             inf->modes->bpp == 0) {
1699                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1700                 ret = -EINVAL;
1701                 goto failed;
1702         }
1703
1704         fbi = pxafb_init_fbinfo(&dev->dev);
1705         if (!fbi) {
1706                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1707                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1708                 ret = -ENOMEM;
1709                 goto failed;
1710         }
1711
1712         fbi->backlight_power = inf->pxafb_backlight_power;
1713         fbi->lcd_power = inf->pxafb_lcd_power;
1714
1715         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1716         if (r == NULL) {
1717                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1718                 ret = -ENODEV;
1719                 goto failed_fbi;
1720         }
1721
1722         r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1723         if (r == NULL) {
1724                 dev_err(&dev->dev, "failed to request I/O memory\n");
1725                 ret = -EBUSY;
1726                 goto failed_fbi;
1727         }
1728
1729         fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1730         if (fbi->mmio_base == NULL) {
1731                 dev_err(&dev->dev, "failed to map I/O memory\n");
1732                 ret = -EBUSY;
1733                 goto failed_free_res;
1734         }
1735
1736         fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1737         fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
1738                                 &fbi->dma_buff_phys, GFP_KERNEL);
1739         if (fbi->dma_buff == NULL) {
1740                 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
1741                 ret = -ENOMEM;
1742                 goto failed_free_io;
1743         }
1744
1745         ret = pxafb_init_video_memory(fbi);
1746         if (ret) {
1747                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1748                 ret = -ENOMEM;
1749                 goto failed_free_dma;
1750         }
1751
1752         irq = platform_get_irq(dev, 0);
1753         if (irq < 0) {
1754                 dev_err(&dev->dev, "no IRQ defined\n");
1755                 ret = -ENODEV;
1756                 goto failed_free_mem;
1757         }
1758
1759         ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1760         if (ret) {
1761                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1762                 ret = -EBUSY;
1763                 goto failed_free_mem;
1764         }
1765
1766         ret = pxafb_smart_init(fbi);
1767         if (ret) {
1768                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1769                 goto failed_free_irq;
1770         }
1771
1772         /*
1773          * This makes sure that our colour bitfield
1774          * descriptors are correctly initialised.
1775          */
1776         ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1777         if (ret) {
1778                 dev_err(&dev->dev, "failed to get suitable mode\n");
1779                 goto failed_free_irq;
1780         }
1781
1782         ret = pxafb_set_par(&fbi->fb);
1783         if (ret) {
1784                 dev_err(&dev->dev, "Failed to set parameters\n");
1785                 goto failed_free_irq;
1786         }
1787
1788         platform_set_drvdata(dev, fbi);
1789
1790         ret = register_framebuffer(&fbi->fb);
1791         if (ret < 0) {
1792                 dev_err(&dev->dev,
1793                         "Failed to register framebuffer device: %d\n", ret);
1794                 goto failed_free_cmap;
1795         }
1796
1797 #ifdef CONFIG_CPU_FREQ
1798         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1799         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1800         cpufreq_register_notifier(&fbi->freq_transition,
1801                                 CPUFREQ_TRANSITION_NOTIFIER);
1802         cpufreq_register_notifier(&fbi->freq_policy,
1803                                 CPUFREQ_POLICY_NOTIFIER);
1804 #endif
1805
1806         /*
1807          * Ok, now enable the LCD controller
1808          */
1809         set_ctrlr_state(fbi, C_ENABLE);
1810
1811         return 0;
1812
1813 failed_free_cmap:
1814         if (fbi->fb.cmap.len)
1815                 fb_dealloc_cmap(&fbi->fb.cmap);
1816 failed_free_irq:
1817         free_irq(irq, fbi);
1818 failed_free_mem:
1819         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1820 failed_free_dma:
1821         dma_free_coherent(&dev->dev, fbi->dma_buff_size,
1822                         fbi->dma_buff, fbi->dma_buff_phys);
1823 failed_free_io:
1824         iounmap(fbi->mmio_base);
1825 failed_free_res:
1826         release_mem_region(r->start, r->end - r->start + 1);
1827 failed_fbi:
1828         clk_put(fbi->clk);
1829         platform_set_drvdata(dev, NULL);
1830         kfree(fbi);
1831 failed:
1832         return ret;
1833 }
1834
1835 static int __devexit pxafb_remove(struct platform_device *dev)
1836 {
1837         struct pxafb_info *fbi = platform_get_drvdata(dev);
1838         struct resource *r;
1839         int irq;
1840         struct fb_info *info;
1841
1842         if (!fbi)
1843                 return 0;
1844
1845         info = &fbi->fb;
1846
1847         unregister_framebuffer(info);
1848
1849         pxafb_disable_controller(fbi);
1850
1851         if (fbi->fb.cmap.len)
1852                 fb_dealloc_cmap(&fbi->fb.cmap);
1853
1854         irq = platform_get_irq(dev, 0);
1855         free_irq(irq, fbi);
1856
1857         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1858
1859         dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
1860                         fbi->dma_buff, fbi->dma_buff_phys);
1861
1862         iounmap(fbi->mmio_base);
1863
1864         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1865         release_mem_region(r->start, r->end - r->start + 1);
1866
1867         clk_put(fbi->clk);
1868         kfree(fbi);
1869
1870         return 0;
1871 }
1872
1873 static struct platform_driver pxafb_driver = {
1874         .probe          = pxafb_probe,
1875         .remove         = pxafb_remove,
1876         .suspend        = pxafb_suspend,
1877         .resume         = pxafb_resume,
1878         .driver         = {
1879                 .owner  = THIS_MODULE,
1880                 .name   = "pxa2xx-fb",
1881         },
1882 };
1883
1884 static int __init pxafb_init(void)
1885 {
1886         if (pxafb_setup_options())
1887                 return -EINVAL;
1888
1889         return platform_driver_register(&pxafb_driver);
1890 }
1891
1892 static void __exit pxafb_exit(void)
1893 {
1894         platform_driver_unregister(&pxafb_driver);
1895 }
1896
1897 module_init(pxafb_init);
1898 module_exit(pxafb_exit);
1899
1900 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1901 MODULE_LICENSE("GPL");