1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/delay.h>
25 #include <linux/slab.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
32 #include <plat/regs-usb-hsotg-phy.h>
33 #include <plat/regs-usb-hsotg.h>
34 #include <mach/regs-sys.h>
35 #include <plat/udc-hs.h>
37 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
41 * Unfortunately there seems to be a limit of the amount of data that can
42 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
43 * packets (which practially means 1 packet and 63 bytes of data) when the
46 * This means if we are wanting to move >127 bytes of data, we need to
47 * split the transactions up, but just doing one packet at a time does
48 * not work (this may be an implicit DATA0 PID on first packet of the
49 * transaction) and doing 2 packets is outside the controller's limits.
51 * If we try to lower the MPS size for EP0, then no transfers work properly
52 * for EP0, and the system will fail basic enumeration. As no cause for this
53 * has currently been found, we cannot support any large IN transfers for
56 #define EP0_MPS_LIMIT 64
62 * struct s3c_hsotg_ep - driver endpoint definition.
63 * @ep: The gadget layer representation of the endpoint.
64 * @name: The driver generated name for the endpoint.
65 * @queue: Queue of requests for this endpoint.
66 * @parent: Reference back to the parent device structure.
67 * @req: The current request that the endpoint is processing. This is
68 * used to indicate an request has been loaded onto the endpoint
69 * and has yet to be completed (maybe due to data move, or simply
70 * awaiting an ack from the core all the data has been completed).
71 * @debugfs: File entry for debugfs file for this endpoint.
72 * @lock: State lock to protect contents of endpoint.
73 * @dir_in: Set to true if this endpoint is of the IN direction, which
74 * means that it is sending data to the Host.
75 * @index: The index for the endpoint registers.
76 * @name: The name array passed to the USB core.
77 * @halted: Set if the endpoint has been halted.
78 * @periodic: Set if this is a periodic ep, such as Interrupt
79 * @sent_zlp: Set if we've sent a zero-length packet.
80 * @total_data: The total number of data bytes done.
81 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
82 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
83 * @last_load: The offset of data for the last start of request.
84 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
86 * This is the driver's state for each registered enpoint, allowing it
87 * to keep track of transactions that need doing. Each endpoint has a
88 * lock to protect the state, to try and avoid using an overall lock
89 * for the host controller as much as possible.
91 * For periodic IN endpoints, we have fifo_size and fifo_load to try
92 * and keep track of the amount of data in the periodic FIFO for each
93 * of these as we don't have a status register that tells us how much
94 * is in each of them. (note, this may actually be useless information
95 * as in shared-fifo mode periodic in acts like a single-frame packet
100 struct list_head queue;
101 struct s3c_hsotg *parent;
102 struct s3c_hsotg_req *req;
103 struct dentry *debugfs;
107 unsigned long total_data;
108 unsigned int size_loaded;
109 unsigned int last_load;
110 unsigned int fifo_load;
111 unsigned short fifo_size;
113 unsigned char dir_in;
116 unsigned int halted:1;
117 unsigned int periodic:1;
118 unsigned int sent_zlp:1;
123 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
126 * struct s3c_hsotg - driver state.
127 * @dev: The parent device supplied to the probe function
128 * @driver: USB gadget driver
129 * @plat: The platform specific configuration data.
130 * @regs: The memory area mapped for accessing registers.
131 * @regs_res: The resource that was allocated when claiming register space.
132 * @irq: The IRQ number we are using
133 * @debug_root: root directrory for debugfs.
134 * @debug_file: main status file for debugfs.
135 * @debug_fifo: FIFO status file for debugfs.
136 * @ep0_reply: Request used for ep0 reply.
137 * @ep0_buff: Buffer for EP0 reply data, if needed.
138 * @ctrl_buff: Buffer for EP0 control requests.
139 * @ctrl_req: Request for EP0 control packets.
140 * @eps: The endpoints being supplied to the gadget framework
144 struct usb_gadget_driver *driver;
145 struct s3c_hsotg_plat *plat;
148 struct resource *regs_res;
151 struct dentry *debug_root;
152 struct dentry *debug_file;
153 struct dentry *debug_fifo;
155 struct usb_request *ep0_reply;
156 struct usb_request *ctrl_req;
160 struct usb_gadget gadget;
161 struct s3c_hsotg_ep eps[];
165 * struct s3c_hsotg_req - data transfer request
166 * @req: The USB gadget request
167 * @queue: The list of requests for the endpoint this is queued for.
168 * @in_progress: Has already had size/packets written to core
169 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
171 struct s3c_hsotg_req {
172 struct usb_request req;
173 struct list_head queue;
174 unsigned char in_progress;
175 unsigned char mapped;
178 /* conversion functions */
179 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
181 return container_of(req, struct s3c_hsotg_req, req);
184 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
186 return container_of(ep, struct s3c_hsotg_ep, ep);
189 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
191 return container_of(gadget, struct s3c_hsotg, gadget);
194 static inline void __orr32(void __iomem *ptr, u32 val)
196 writel(readl(ptr) | val, ptr);
199 static inline void __bic32(void __iomem *ptr, u32 val)
201 writel(readl(ptr) & ~val, ptr);
204 /* forward decleration of functions */
205 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
208 * using_dma - return the DMA status of the driver.
209 * @hsotg: The driver state.
211 * Return true if we're using DMA.
213 * Currently, we have the DMA support code worked into everywhere
214 * that needs it, but the AMBA DMA implementation in the hardware can
215 * only DMA from 32bit aligned addresses. This means that gadgets such
216 * as the CDC Ethernet cannot work as they often pass packets which are
219 * Unfortunately the choice to use DMA or not is global to the controller
220 * and seems to be only settable when the controller is being put through
221 * a core reset. This means we either need to fix the gadgets to take
222 * account of DMA alignment, or add bounce buffers (yuerk).
224 * Until this issue is sorted out, we always return 'false'.
226 static inline bool using_dma(struct s3c_hsotg *hsotg)
228 return false; /* support is not complete */
232 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
233 * @hsotg: The device state
234 * @ints: A bitmask of the interrupts to enable
236 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
238 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
241 new_gsintmsk = gsintmsk | ints;
243 if (new_gsintmsk != gsintmsk) {
244 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
245 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
250 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
251 * @hsotg: The device state
252 * @ints: A bitmask of the interrupts to enable
254 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
256 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
259 new_gsintmsk = gsintmsk & ~ints;
261 if (new_gsintmsk != gsintmsk)
262 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
266 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
267 * @hsotg: The device state
268 * @ep: The endpoint index
269 * @dir_in: True if direction is in.
270 * @en: The enable value, true to enable
272 * Set or clear the mask for an individual endpoint's interrupt
275 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
276 unsigned int ep, unsigned int dir_in,
286 local_irq_save(flags);
287 daint = readl(hsotg->regs + S3C_DAINTMSK);
292 writel(daint, hsotg->regs + S3C_DAINTMSK);
293 local_irq_restore(flags);
297 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
298 * @hsotg: The device instance.
300 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
308 /* the ryu 2.6.24 release ahs
309 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
310 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
311 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
312 hsotg->regs + S3C_GNPTXFSIZ);
315 /* set FIFO sizes to 2048/1024 */
317 writel(2048, hsotg->regs + S3C_GRXFSIZ);
318 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
319 S3C_GNPTXFSIZ_NPTxFDep(1024),
320 hsotg->regs + S3C_GNPTXFSIZ);
322 /* arange all the rest of the TX FIFOs, as some versions of this
323 * block have overlapping default addresses. This also ensures
324 * that if the settings have been changed, then they are set to
327 /* start at the end of the GNPTXFSIZ, rounded up */
331 /* currently we allocate TX FIFOs for all possible endpoints,
332 * and assume that they are all the same size. */
334 for (ep = 0; ep <= 15; ep++) {
336 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
339 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
342 /* according to p428 of the design guide, we need to ensure that
343 * all fifos are flushed before continuing */
345 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
346 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
348 /* wait until the fifos are both flushed */
351 val = readl(hsotg->regs + S3C_GRSTCTL);
353 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
356 if (--timeout == 0) {
358 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
365 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
369 * @ep: USB endpoint to allocate request for.
370 * @flags: Allocation flags
372 * Allocate a new USB request structure appropriate for the specified endpoint
374 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
377 struct s3c_hsotg_req *req;
379 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
383 INIT_LIST_HEAD(&req->queue);
385 req->req.dma = DMA_ADDR_INVALID;
390 * is_ep_periodic - return true if the endpoint is in periodic mode.
391 * @hs_ep: The endpoint to query.
393 * Returns true if the endpoint is in periodic mode, meaning it is being
394 * used for an Interrupt or ISO transfer.
396 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
398 return hs_ep->periodic;
402 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
403 * @hsotg: The device state.
404 * @hs_ep: The endpoint for the request
405 * @hs_req: The request being processed.
407 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
408 * of a request to ensure the buffer is ready for access by the caller.
410 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
411 struct s3c_hsotg_ep *hs_ep,
412 struct s3c_hsotg_req *hs_req)
414 struct usb_request *req = &hs_req->req;
415 enum dma_data_direction dir;
417 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
419 /* ignore this if we're not moving any data */
420 if (hs_req->req.length == 0)
423 if (hs_req->mapped) {
424 /* we mapped this, so unmap and remove the dma */
426 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
428 req->dma = DMA_ADDR_INVALID;
431 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
436 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
437 * @hsotg: The controller state.
438 * @hs_ep: The endpoint we're going to write for.
439 * @hs_req: The request to write data for.
441 * This is called when the TxFIFO has some space in it to hold a new
442 * transmission and we have something to give it. The actual setup of
443 * the data size is done elsewhere, so all we have to do is to actually
446 * The return value is zero if there is more space (or nothing was done)
447 * otherwise -ENOSPC is returned if the FIFO space was used up.
449 * This routine is only needed for PIO
451 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
452 struct s3c_hsotg_ep *hs_ep,
453 struct s3c_hsotg_req *hs_req)
455 bool periodic = is_ep_periodic(hs_ep);
456 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
457 int buf_pos = hs_req->req.actual;
458 int to_write = hs_ep->size_loaded;
463 to_write -= (buf_pos - hs_ep->last_load);
465 /* if there's nothing to write, get out early */
470 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
474 /* work out how much data was loaded so we can calculate
475 * how much data is left in the fifo. */
477 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
479 /* if shared fifo, we cannot write anything until the
480 * previous data has been completely sent.
482 if (hs_ep->fifo_load != 0) {
483 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
487 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
489 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
491 /* how much of the data has moved */
492 size_done = hs_ep->size_loaded - size_left;
494 /* how much data is left in the fifo */
495 can_write = hs_ep->fifo_load - size_done;
496 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
497 __func__, can_write);
499 can_write = hs_ep->fifo_size - can_write;
500 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
501 __func__, can_write);
503 if (can_write <= 0) {
504 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
508 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
510 "%s: no queue slots available (0x%08x)\n",
513 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
517 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
518 can_write *= 4; /* fifo size is in 32bit quantities. */
521 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
522 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
524 /* limit to 512 bytes of data, it seems at least on the non-periodic
525 * FIFO, requests of >512 cause the endpoint to get stuck with a
526 * fragment of the end of the transfer in it.
531 /* see if we can write data */
533 if (to_write > can_write) {
534 to_write = can_write;
535 pkt_round = to_write % hs_ep->ep.maxpacket;
537 /* Not sure, but we probably shouldn't be writing partial
538 * packets into the FIFO, so round the write down to an
539 * exact number of packets.
541 * Note, we do not currently check to see if we can ever
542 * write a full packet or not to the FIFO.
546 to_write -= pkt_round;
548 /* enable correct FIFO interrupt to alert us when there
549 * is more room left. */
551 s3c_hsotg_en_gsint(hsotg,
552 periodic ? S3C_GINTSTS_PTxFEmp :
553 S3C_GINTSTS_NPTxFEmp);
556 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
557 to_write, hs_req->req.length, can_write, buf_pos);
562 hs_req->req.actual = buf_pos + to_write;
563 hs_ep->total_data += to_write;
566 hs_ep->fifo_load += to_write;
568 to_write = DIV_ROUND_UP(to_write, 4);
569 data = hs_req->req.buf + buf_pos;
571 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
573 return (to_write >= can_write) ? -ENOSPC : 0;
577 * get_ep_limit - get the maximum data legnth for this endpoint
578 * @hs_ep: The endpoint
580 * Return the maximum data that can be queued in one go on a given endpoint
581 * so that transfers that are too long can be split.
583 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
585 int index = hs_ep->index;
590 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
591 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
594 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
596 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
603 /* we made the constant loading easier above by using +1 */
607 /* constrain by packet count if maxpkts*pktsize is greater
608 * than the length register size. */
610 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
611 maxsize = maxpkt * hs_ep->ep.maxpacket;
617 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
618 * @hsotg: The controller state.
619 * @hs_ep: The endpoint to process a request for
620 * @hs_req: The request to start.
621 * @continuing: True if we are doing more for the current request.
623 * Start the given request running by setting the endpoint registers
624 * appropriately, and writing any data to the FIFOs.
626 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
627 struct s3c_hsotg_ep *hs_ep,
628 struct s3c_hsotg_req *hs_req,
631 struct usb_request *ureq = &hs_req->req;
632 int index = hs_ep->index;
633 int dir_in = hs_ep->dir_in;
643 if (hs_ep->req && !continuing) {
644 dev_err(hsotg->dev, "%s: active request\n", __func__);
647 } else if (hs_ep->req != hs_req && continuing) {
649 "%s: continue different req\n", __func__);
655 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
656 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
658 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
659 __func__, readl(hsotg->regs + epctrl_reg), index,
660 hs_ep->dir_in ? "in" : "out");
662 length = ureq->length - ureq->actual;
666 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
667 ureq->buf, length, ureq->dma,
668 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
670 maxreq = get_ep_limit(hs_ep);
671 if (length > maxreq) {
672 int round = maxreq % hs_ep->ep.maxpacket;
674 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
675 __func__, length, maxreq, round);
677 /* round down to multiple of packets */
685 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
687 packets = 1; /* send one packet if length is zero. */
689 if (dir_in && index != 0)
690 epsize = S3C_DxEPTSIZ_MC(1);
694 if (index != 0 && ureq->zero) {
695 /* test for the packets being exactly right for the
698 if (length == (packets * hs_ep->ep.maxpacket))
702 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
703 epsize |= S3C_DxEPTSIZ_XferSize(length);
705 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
706 __func__, packets, length, ureq->length, epsize, epsize_reg);
708 /* store the request as the current one we're doing */
711 /* write size / packets */
712 writel(epsize, hsotg->regs + epsize_reg);
714 ctrl = readl(hsotg->regs + epctrl_reg);
716 if (ctrl & S3C_DxEPCTL_Stall) {
717 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
719 /* not sure what we can do here, if it is EP0 then we should
720 * get this cleared once the endpoint has transmitted the
721 * STALL packet, otherwise it needs to be cleared by the
726 if (using_dma(hsotg)) {
727 unsigned int dma_reg;
729 /* write DMA address to control register, buffer already
730 * synced by s3c_hsotg_ep_queue(). */
732 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
733 writel(ureq->dma, hsotg->regs + dma_reg);
735 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
736 __func__, ureq->dma, dma_reg);
739 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
740 ctrl |= S3C_DxEPCTL_USBActEp;
741 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
743 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
744 writel(ctrl, hsotg->regs + epctrl_reg);
746 /* set these, it seems that DMA support increments past the end
747 * of the packet buffer so we need to calculate the length from
748 * this information. */
749 hs_ep->size_loaded = length;
750 hs_ep->last_load = ureq->actual;
752 if (dir_in && !using_dma(hsotg)) {
753 /* set these anyway, we may need them for non-periodic in */
754 hs_ep->fifo_load = 0;
756 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
759 /* clear the INTknTXFEmpMsk when we start request, more as a aide
760 * to debugging to see what is going on. */
762 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
763 hsotg->regs + S3C_DIEPINT(index));
765 /* Note, trying to clear the NAK here causes problems with transmit
766 * on the S3C6400 ending up with the TXFIFO becomming full. */
768 /* check ep is enabled */
769 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
771 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
772 index, readl(hsotg->regs + epctrl_reg));
774 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
775 __func__, readl(hsotg->regs + epctrl_reg));
779 * s3c_hsotg_map_dma - map the DMA memory being used for the request
780 * @hsotg: The device state.
781 * @hs_ep: The endpoint the request is on.
782 * @req: The request being processed.
784 * We've been asked to queue a request, so ensure that the memory buffer
785 * is correctly setup for DMA. If we've been passed an extant DMA address
786 * then ensure the buffer has been synced to memory. If our buffer has no
787 * DMA memory, then we map the memory and mark our request to allow us to
788 * cleanup on completion.
790 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
791 struct s3c_hsotg_ep *hs_ep,
792 struct usb_request *req)
794 enum dma_data_direction dir;
795 struct s3c_hsotg_req *hs_req = our_req(req);
797 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
799 /* if the length is zero, ignore the DMA data */
800 if (hs_req->req.length == 0)
803 if (req->dma == DMA_ADDR_INVALID) {
806 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
808 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
812 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
815 dma_unmap_single(hsotg->dev, dma, req->length, dir);
822 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
829 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
830 __func__, req->buf, req->length);
835 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
838 struct s3c_hsotg_req *hs_req = our_req(req);
839 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
840 struct s3c_hsotg *hs = hs_ep->parent;
841 unsigned long irqflags;
844 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
845 ep->name, req, req->length, req->buf, req->no_interrupt,
846 req->zero, req->short_not_ok);
848 /* initialise status of the request */
849 INIT_LIST_HEAD(&hs_req->queue);
851 req->status = -EINPROGRESS;
853 /* if we're using DMA, sync the buffers as necessary */
855 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
860 spin_lock_irqsave(&hs_ep->lock, irqflags);
862 first = list_empty(&hs_ep->queue);
863 list_add_tail(&hs_req->queue, &hs_ep->queue);
866 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
868 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
873 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
874 struct usb_request *req)
876 struct s3c_hsotg_req *hs_req = our_req(req);
882 * s3c_hsotg_complete_oursetup - setup completion callback
883 * @ep: The endpoint the request was on.
884 * @req: The request completed.
886 * Called on completion of any requests the driver itself
887 * submitted that need cleaning up.
889 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
890 struct usb_request *req)
892 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
893 struct s3c_hsotg *hsotg = hs_ep->parent;
895 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
897 s3c_hsotg_ep_free_request(ep, req);
901 * ep_from_windex - convert control wIndex value to endpoint
902 * @hsotg: The driver state.
903 * @windex: The control request wIndex field (in host order).
905 * Convert the given wIndex into a pointer to an driver endpoint
906 * structure, or return NULL if it is not a valid endpoint.
908 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
911 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
912 int dir = (windex & USB_DIR_IN) ? 1 : 0;
913 int idx = windex & 0x7F;
918 if (idx > S3C_HSOTG_EPS)
921 if (idx && ep->dir_in != dir)
928 * s3c_hsotg_send_reply - send reply to control request
929 * @hsotg: The device state
931 * @buff: Buffer for request
932 * @length: Length of reply.
934 * Create a request and queue it on the given endpoint. This is useful as
935 * an internal method of sending replies to certain control requests, etc.
937 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
938 struct s3c_hsotg_ep *ep,
942 struct usb_request *req;
945 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
947 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
948 hsotg->ep0_reply = req;
950 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
954 req->buf = hsotg->ep0_buff;
955 req->length = length;
956 req->zero = 1; /* always do zero-length final transfer */
957 req->complete = s3c_hsotg_complete_oursetup;
960 memcpy(req->buf, buff, length);
964 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
966 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
974 * s3c_hsotg_process_req_status - process request GET_STATUS
975 * @hsotg: The device state
976 * @ctrl: USB control request
978 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
979 struct usb_ctrlrequest *ctrl)
981 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
982 struct s3c_hsotg_ep *ep;
986 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
989 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
993 switch (ctrl->bRequestType & USB_RECIP_MASK) {
994 case USB_RECIP_DEVICE:
995 reply = cpu_to_le16(0); /* bit 0 => self powered,
996 * bit 1 => remote wakeup */
999 case USB_RECIP_INTERFACE:
1000 /* currently, the data result should be zero */
1001 reply = cpu_to_le16(0);
1004 case USB_RECIP_ENDPOINT:
1005 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1009 reply = cpu_to_le16(ep->halted ? 1 : 0);
1016 if (le16_to_cpu(ctrl->wLength) != 2)
1019 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1021 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1028 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1031 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1032 * @hsotg: The device state
1033 * @ctrl: USB control request
1035 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1036 struct usb_ctrlrequest *ctrl)
1038 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1039 struct s3c_hsotg_ep *ep;
1041 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1042 __func__, set ? "SET" : "CLEAR");
1044 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1045 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1047 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1048 __func__, le16_to_cpu(ctrl->wIndex));
1052 switch (le16_to_cpu(ctrl->wValue)) {
1053 case USB_ENDPOINT_HALT:
1054 s3c_hsotg_ep_sethalt(&ep->ep, set);
1061 return -ENOENT; /* currently only deal with endpoint */
1067 * s3c_hsotg_process_control - process a control request
1068 * @hsotg: The device state
1069 * @ctrl: The control request received
1071 * The controller has received the SETUP phase of a control request, and
1072 * needs to work out what to do next (and whether to pass it on to the
1075 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1076 struct usb_ctrlrequest *ctrl)
1078 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1084 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1085 ctrl->bRequest, ctrl->bRequestType,
1086 ctrl->wValue, ctrl->wLength);
1088 /* record the direction of the request, for later use when enquing
1089 * packets onto EP0. */
1091 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1092 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1094 /* if we've no data with this request, then the last part of the
1095 * transaction is going to implicitly be IN. */
1096 if (ctrl->wLength == 0)
1099 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1100 switch (ctrl->bRequest) {
1101 case USB_REQ_SET_ADDRESS:
1102 dcfg = readl(hsotg->regs + S3C_DCFG);
1103 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1104 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1105 writel(dcfg, hsotg->regs + S3C_DCFG);
1107 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1109 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1112 case USB_REQ_GET_STATUS:
1113 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1116 case USB_REQ_CLEAR_FEATURE:
1117 case USB_REQ_SET_FEATURE:
1118 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1123 /* as a fallback, try delivering it to the driver to deal with */
1125 if (ret == 0 && hsotg->driver) {
1126 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1128 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1133 /* need to generate zlp in reply or take data */
1134 /* todo - deal with any data we might be sent? */
1135 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1139 /* the request is either unhandlable, or is not formatted correctly
1140 * so respond with a STALL for the status stage to indicate failure.
1147 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1148 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1150 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1151 * taken effect, so no need to clear later. */
1153 ctrl = readl(hsotg->regs + reg);
1154 ctrl |= S3C_DxEPCTL_Stall;
1155 ctrl |= S3C_DxEPCTL_CNAK;
1156 writel(ctrl, hsotg->regs + reg);
1159 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1160 ctrl, reg, readl(hsotg->regs + reg));
1162 /* don't belive we need to anything more to get the EP
1163 * to reply with a STALL packet */
1167 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1170 * s3c_hsotg_complete_setup - completion of a setup transfer
1171 * @ep: The endpoint the request was on.
1172 * @req: The request completed.
1174 * Called on completion of any requests the driver itself submitted for
1177 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1178 struct usb_request *req)
1180 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1181 struct s3c_hsotg *hsotg = hs_ep->parent;
1183 if (req->status < 0) {
1184 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1188 if (req->actual == 0)
1189 s3c_hsotg_enqueue_setup(hsotg);
1191 s3c_hsotg_process_control(hsotg, req->buf);
1195 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1196 * @hsotg: The device state.
1198 * Enqueue a request on EP0 if necessary to received any SETUP packets
1199 * received from the host.
1201 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1203 struct usb_request *req = hsotg->ctrl_req;
1204 struct s3c_hsotg_req *hs_req = our_req(req);
1207 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1211 req->buf = hsotg->ctrl_buff;
1212 req->complete = s3c_hsotg_complete_setup;
1214 if (!list_empty(&hs_req->queue)) {
1215 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1219 hsotg->eps[0].dir_in = 0;
1221 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1223 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1224 /* Don't think there's much we can do other than watch the
1230 * get_ep_head - return the first request on the endpoint
1231 * @hs_ep: The controller endpoint to get
1233 * Get the first request on the endpoint.
1235 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1237 if (list_empty(&hs_ep->queue))
1240 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1244 * s3c_hsotg_complete_request - complete a request given to us
1245 * @hsotg: The device state.
1246 * @hs_ep: The endpoint the request was on.
1247 * @hs_req: The request to complete.
1248 * @result: The result code (0 => Ok, otherwise errno)
1250 * The given request has finished, so call the necessary completion
1251 * if it has one and then look to see if we can start a new request
1254 * Note, expects the ep to already be locked as appropriate.
1256 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1257 struct s3c_hsotg_ep *hs_ep,
1258 struct s3c_hsotg_req *hs_req,
1264 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1268 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1269 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1271 /* only replace the status if we've not already set an error
1272 * from a previous transaction */
1274 if (hs_req->req.status == -EINPROGRESS)
1275 hs_req->req.status = result;
1278 list_del_init(&hs_req->queue);
1280 if (using_dma(hsotg))
1281 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1283 /* call the complete request with the locks off, just in case the
1284 * request tries to queue more work for this endpoint. */
1286 if (hs_req->req.complete) {
1287 spin_unlock(&hs_ep->lock);
1288 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1289 spin_lock(&hs_ep->lock);
1292 /* Look to see if there is anything else to do. Note, the completion
1293 * of the previous request may have caused a new request to be started
1294 * so be careful when doing this. */
1296 if (!hs_ep->req && result >= 0) {
1297 restart = !list_empty(&hs_ep->queue);
1299 hs_req = get_ep_head(hs_ep);
1300 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1306 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1307 * @hsotg: The device state.
1308 * @hs_ep: The endpoint the request was on.
1309 * @hs_req: The request to complete.
1310 * @result: The result code (0 => Ok, otherwise errno)
1312 * See s3c_hsotg_complete_request(), but called with the endpoint's
1315 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1316 struct s3c_hsotg_ep *hs_ep,
1317 struct s3c_hsotg_req *hs_req,
1320 unsigned long flags;
1322 spin_lock_irqsave(&hs_ep->lock, flags);
1323 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1324 spin_unlock_irqrestore(&hs_ep->lock, flags);
1328 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1329 * @hsotg: The device state.
1330 * @ep_idx: The endpoint index for the data
1331 * @size: The size of data in the fifo, in bytes
1333 * The FIFO status shows there is data to read from the FIFO for a given
1334 * endpoint, so sort out whether we need to read the data into a request
1335 * that has been made for that endpoint.
1337 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1339 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1340 struct s3c_hsotg_req *hs_req = hs_ep->req;
1341 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1347 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1350 dev_warn(hsotg->dev,
1351 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1352 __func__, size, ep_idx, epctl);
1354 /* dump the data from the FIFO, we've nothing we can do */
1355 for (ptr = 0; ptr < size; ptr += 4)
1361 spin_lock(&hs_ep->lock);
1364 read_ptr = hs_req->req.actual;
1365 max_req = hs_req->req.length - read_ptr;
1367 if (to_read > max_req) {
1368 /* more data appeared than we where willing
1369 * to deal with in this request.
1372 /* currently we don't deal this */
1376 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1377 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1379 hs_ep->total_data += to_read;
1380 hs_req->req.actual += to_read;
1381 to_read = DIV_ROUND_UP(to_read, 4);
1383 /* note, we might over-write the buffer end by 3 bytes depending on
1384 * alignment of the data. */
1385 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1387 spin_unlock(&hs_ep->lock);
1391 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1392 * @hsotg: The device instance
1393 * @req: The request currently on this endpoint
1395 * Generate a zero-length IN packet request for terminating a SETUP
1398 * Note, since we don't write any data to the TxFIFO, then it is
1399 * currently belived that we do not need to wait for any space in
1402 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1403 struct s3c_hsotg_req *req)
1408 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1412 if (req->req.length == 0) {
1413 hsotg->eps[0].sent_zlp = 1;
1414 s3c_hsotg_enqueue_setup(hsotg);
1418 hsotg->eps[0].dir_in = 1;
1419 hsotg->eps[0].sent_zlp = 1;
1421 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1423 /* issue a zero-sized packet to terminate this */
1424 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1425 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1427 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1428 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1429 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1430 ctrl |= S3C_DxEPCTL_USBActEp;
1431 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1435 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1436 * @hsotg: The device instance
1437 * @epnum: The endpoint received from
1438 * @was_setup: Set if processing a SetupDone event.
1440 * The RXFIFO has delivered an OutDone event, which means that the data
1441 * transfer for an OUT endpoint has been completed, either by a short
1442 * packet or by the finish of a transfer.
1444 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1445 int epnum, bool was_setup)
1447 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1448 struct s3c_hsotg_req *hs_req = hs_ep->req;
1449 struct usb_request *req = &hs_req->req;
1453 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1457 if (using_dma(hsotg)) {
1458 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1462 /* Calculate the size of the transfer by checking how much
1463 * is left in the endpoint size register and then working it
1464 * out from the amount we loaded for the transfer.
1466 * We need to do this as DMA pointers are always 32bit aligned
1467 * so may overshoot/undershoot the transfer.
1470 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1472 size_done = hs_ep->size_loaded - size_left;
1473 size_done += hs_ep->last_load;
1475 req->actual = size_done;
1478 if (req->actual < req->length && req->short_not_ok) {
1479 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1480 __func__, req->actual, req->length);
1482 /* todo - what should we return here? there's no one else
1483 * even bothering to check the status. */
1487 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1488 s3c_hsotg_send_zlp(hsotg, hs_req);
1491 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1495 * s3c_hsotg_read_frameno - read current frame number
1496 * @hsotg: The device instance
1498 * Return the current frame number
1500 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1504 dsts = readl(hsotg->regs + S3C_DSTS);
1505 dsts &= S3C_DSTS_SOFFN_MASK;
1506 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1512 * s3c_hsotg_handle_rx - RX FIFO has data
1513 * @hsotg: The device instance
1515 * The IRQ handler has detected that the RX FIFO has some data in it
1516 * that requires processing, so find out what is in there and do the
1519 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1520 * chunks, so if you have x packets received on an endpoint you'll get x
1521 * FIFO events delivered, each with a packet's worth of data in it.
1523 * When using DMA, we should not be processing events from the RXFIFO
1524 * as the actual data should be sent to the memory directly and we turn
1525 * on the completion interrupts to get notifications of transfer completion.
1527 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1529 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1530 u32 epnum, status, size;
1532 WARN_ON(using_dma(hsotg));
1534 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1535 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1537 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1538 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1541 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1542 __func__, grxstsr, size, epnum);
1544 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1546 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1547 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1548 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1551 case __status(S3C_GRXSTS_PktSts_OutDone):
1552 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1553 s3c_hsotg_read_frameno(hsotg));
1555 if (!using_dma(hsotg))
1556 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1559 case __status(S3C_GRXSTS_PktSts_SetupDone):
1561 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1562 s3c_hsotg_read_frameno(hsotg),
1563 readl(hsotg->regs + S3C_DOEPCTL(0)));
1565 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1568 case __status(S3C_GRXSTS_PktSts_OutRX):
1569 s3c_hsotg_rx_data(hsotg, epnum, size);
1572 case __status(S3C_GRXSTS_PktSts_SetupRX):
1574 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1575 s3c_hsotg_read_frameno(hsotg),
1576 readl(hsotg->regs + S3C_DOEPCTL(0)));
1578 s3c_hsotg_rx_data(hsotg, epnum, size);
1582 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1585 s3c_hsotg_dump(hsotg);
1591 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1592 * @mps: The maximum packet size in bytes.
1594 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1598 return S3C_D0EPCTL_MPS_64;
1600 return S3C_D0EPCTL_MPS_32;
1602 return S3C_D0EPCTL_MPS_16;
1604 return S3C_D0EPCTL_MPS_8;
1607 /* bad max packet size, warn and return invalid result */
1613 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1614 * @hsotg: The driver state.
1615 * @ep: The index number of the endpoint
1616 * @mps: The maximum packet size in bytes
1618 * Configure the maximum packet size for the given endpoint, updating
1619 * the hardware control registers to reflect this.
1621 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1622 unsigned int ep, unsigned int mps)
1624 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1625 void __iomem *regs = hsotg->regs;
1630 /* EP0 is a special case */
1631 mpsval = s3c_hsotg_ep0_mps(mps);
1635 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1641 hs_ep->ep.maxpacket = mps;
1643 /* update both the in and out endpoint controldir_ registers, even
1644 * if one of the directions may not be in use. */
1646 reg = readl(regs + S3C_DIEPCTL(ep));
1647 reg &= ~S3C_DxEPCTL_MPS_MASK;
1649 writel(reg, regs + S3C_DIEPCTL(ep));
1651 reg = readl(regs + S3C_DOEPCTL(ep));
1652 reg &= ~S3C_DxEPCTL_MPS_MASK;
1654 writel(reg, regs + S3C_DOEPCTL(ep));
1659 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1664 * s3c_hsotg_trytx - check to see if anything needs transmitting
1665 * @hsotg: The driver state
1666 * @hs_ep: The driver endpoint to check.
1668 * Check to see if there is a request that has data to send, and if so
1669 * make an attempt to write data into the FIFO.
1671 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1672 struct s3c_hsotg_ep *hs_ep)
1674 struct s3c_hsotg_req *hs_req = hs_ep->req;
1676 if (!hs_ep->dir_in || !hs_req)
1679 if (hs_req->req.actual < hs_req->req.length) {
1680 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1682 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1689 * s3c_hsotg_complete_in - complete IN transfer
1690 * @hsotg: The device state.
1691 * @hs_ep: The endpoint that has just completed.
1693 * An IN transfer has been completed, update the transfer's state and then
1694 * call the relevant completion routines.
1696 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1697 struct s3c_hsotg_ep *hs_ep)
1699 struct s3c_hsotg_req *hs_req = hs_ep->req;
1700 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1701 int size_left, size_done;
1704 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1708 /* Calculate the size of the transfer by checking how much is left
1709 * in the endpoint size register and then working it out from
1710 * the amount we loaded for the transfer.
1712 * We do this even for DMA, as the transfer may have incremented
1713 * past the end of the buffer (DMA transfers are always 32bit
1717 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1719 size_done = hs_ep->size_loaded - size_left;
1720 size_done += hs_ep->last_load;
1722 if (hs_req->req.actual != size_done)
1723 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1724 __func__, hs_req->req.actual, size_done);
1726 hs_req->req.actual = size_done;
1728 /* if we did all of the transfer, and there is more data left
1729 * around, then try restarting the rest of the request */
1731 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1732 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1733 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1735 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1739 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1740 * @hsotg: The driver state
1741 * @idx: The index for the endpoint (0..15)
1742 * @dir_in: Set if this is an IN endpoint
1744 * Process and clear any interrupt pending for an individual endpoint
1746 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1749 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1750 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1751 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1752 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1756 ints = readl(hsotg->regs + epint_reg);
1758 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1759 __func__, idx, dir_in ? "in" : "out", ints);
1761 if (ints & S3C_DxEPINT_XferCompl) {
1763 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1764 __func__, readl(hsotg->regs + epctl_reg),
1765 readl(hsotg->regs + epsiz_reg));
1767 /* we get OutDone from the FIFO, so we only need to look
1768 * at completing IN requests here */
1770 s3c_hsotg_complete_in(hsotg, hs_ep);
1773 s3c_hsotg_enqueue_setup(hsotg);
1774 } else if (using_dma(hsotg)) {
1775 /* We're using DMA, we need to fire an OutDone here
1776 * as we ignore the RXFIFO. */
1778 s3c_hsotg_handle_outdone(hsotg, idx, false);
1781 clear |= S3C_DxEPINT_XferCompl;
1784 if (ints & S3C_DxEPINT_EPDisbld) {
1785 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1786 clear |= S3C_DxEPINT_EPDisbld;
1789 if (ints & S3C_DxEPINT_AHBErr) {
1790 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1791 clear |= S3C_DxEPINT_AHBErr;
1794 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1795 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1797 if (using_dma(hsotg) && idx == 0) {
1798 /* this is the notification we've received a
1799 * setup packet. In non-DMA mode we'd get this
1800 * from the RXFIFO, instead we need to process
1801 * the setup here. */
1806 s3c_hsotg_handle_outdone(hsotg, 0, true);
1809 clear |= S3C_DxEPINT_Setup;
1812 if (ints & S3C_DxEPINT_Back2BackSetup) {
1813 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1814 clear |= S3C_DxEPINT_Back2BackSetup;
1818 /* not sure if this is important, but we'll clear it anyway
1820 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1821 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1823 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1826 /* this probably means something bad is happening */
1827 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1828 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1830 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1834 writel(clear, hsotg->regs + epint_reg);
1838 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1839 * @hsotg: The device state.
1841 * Handle updating the device settings after the enumeration phase has
1844 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1846 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1847 int ep0_mps = 0, ep_mps;
1849 /* This should signal the finish of the enumeration phase
1850 * of the USB handshaking, so we should now know what rate
1851 * we connected at. */
1853 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1855 /* note, since we're limited by the size of transfer on EP0, and
1856 * it seems IN transfers must be a even number of packets we do
1857 * not advertise a 64byte MPS on EP0. */
1859 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1860 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1861 case S3C_DSTS_EnumSpd_FS:
1862 case S3C_DSTS_EnumSpd_FS48:
1863 hsotg->gadget.speed = USB_SPEED_FULL;
1864 dev_info(hsotg->dev, "new device is full-speed\n");
1866 ep0_mps = EP0_MPS_LIMIT;
1870 case S3C_DSTS_EnumSpd_HS:
1871 dev_info(hsotg->dev, "new device is high-speed\n");
1872 hsotg->gadget.speed = USB_SPEED_HIGH;
1874 ep0_mps = EP0_MPS_LIMIT;
1878 case S3C_DSTS_EnumSpd_LS:
1879 hsotg->gadget.speed = USB_SPEED_LOW;
1880 dev_info(hsotg->dev, "new device is low-speed\n");
1882 /* note, we don't actually support LS in this driver at the
1883 * moment, and the documentation seems to imply that it isn't
1884 * supported by the PHYs on some of the devices.
1889 /* we should now know the maximum packet size for an
1890 * endpoint, so set the endpoints to a default value. */
1894 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1895 for (i = 1; i < S3C_HSOTG_EPS; i++)
1896 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1899 /* ensure after enumeration our EP0 is active */
1901 s3c_hsotg_enqueue_setup(hsotg);
1903 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1904 readl(hsotg->regs + S3C_DIEPCTL0),
1905 readl(hsotg->regs + S3C_DOEPCTL0));
1909 * kill_all_requests - remove all requests from the endpoint's queue
1910 * @hsotg: The device state.
1911 * @ep: The endpoint the requests may be on.
1912 * @result: The result code to use.
1913 * @force: Force removal of any current requests
1915 * Go through the requests on the given endpoint and mark them
1916 * completed with the given result code.
1918 static void kill_all_requests(struct s3c_hsotg *hsotg,
1919 struct s3c_hsotg_ep *ep,
1920 int result, bool force)
1922 struct s3c_hsotg_req *req, *treq;
1923 unsigned long flags;
1925 spin_lock_irqsave(&ep->lock, flags);
1927 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1928 /* currently, we can't do much about an already
1929 * running request on an in endpoint */
1931 if (ep->req == req && ep->dir_in && !force)
1934 s3c_hsotg_complete_request(hsotg, ep, req,
1938 spin_unlock_irqrestore(&ep->lock, flags);
1941 #define call_gadget(_hs, _entry) \
1942 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1943 (_hs)->driver && (_hs)->driver->_entry) \
1944 (_hs)->driver->_entry(&(_hs)->gadget);
1947 * s3c_hsotg_disconnect_irq - disconnect irq service
1948 * @hsotg: The device state.
1950 * A disconnect IRQ has been received, meaning that the host has
1951 * lost contact with the bus. Remove all current transactions
1952 * and signal the gadget driver that this has happened.
1954 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1958 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1959 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1961 call_gadget(hsotg, disconnect);
1965 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1966 * @hsotg: The device state:
1967 * @periodic: True if this is a periodic FIFO interrupt
1969 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1971 struct s3c_hsotg_ep *ep;
1974 /* look through for any more data to transmit */
1976 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
1977 ep = &hsotg->eps[epno];
1982 if ((periodic && !ep->periodic) ||
1983 (!periodic && ep->periodic))
1986 ret = s3c_hsotg_trytx(hsotg, ep);
1992 static struct s3c_hsotg *our_hsotg;
1994 /* IRQ flags which will trigger a retry around the IRQ loop */
1995 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
1996 S3C_GINTSTS_PTxFEmp | \
2000 * s3c_hsotg_irq - handle device interrupt
2001 * @irq: The IRQ number triggered
2002 * @pw: The pw value when registered the handler.
2004 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2006 struct s3c_hsotg *hsotg = pw;
2007 int retry_count = 8;
2012 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2013 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2015 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2016 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2020 if (gintsts & S3C_GINTSTS_OTGInt) {
2021 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2023 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2025 writel(otgint, hsotg->regs + S3C_GOTGINT);
2026 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
2029 if (gintsts & S3C_GINTSTS_DisconnInt) {
2030 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2031 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2033 s3c_hsotg_disconnect_irq(hsotg);
2036 if (gintsts & S3C_GINTSTS_SessReqInt) {
2037 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2038 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2041 if (gintsts & S3C_GINTSTS_EnumDone) {
2042 s3c_hsotg_irq_enumdone(hsotg);
2043 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2046 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2047 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2048 readl(hsotg->regs + S3C_DSTS),
2049 readl(hsotg->regs + S3C_GOTGCTL));
2051 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2054 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2055 u32 daint = readl(hsotg->regs + S3C_DAINT);
2056 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2057 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2060 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2062 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2064 s3c_hsotg_epint(hsotg, ep, 0);
2067 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2069 s3c_hsotg_epint(hsotg, ep, 1);
2072 writel(daint, hsotg->regs + S3C_DAINT);
2073 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2074 hsotg->regs + S3C_GINTSTS);
2077 if (gintsts & S3C_GINTSTS_USBRst) {
2078 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2079 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2080 readl(hsotg->regs + S3C_GNPTXSTS));
2082 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2084 /* it seems after a reset we can end up with a situation
2085 * where the TXFIFO still has data in it... the docs
2086 * suggest resetting all the fifos, so use the init_fifo
2087 * code to relayout and flush the fifos.
2090 s3c_hsotg_init_fifo(hsotg);
2092 s3c_hsotg_enqueue_setup(hsotg);
2094 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2097 /* check both FIFOs */
2099 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2100 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2102 /* Disable the interrupt to stop it happening again
2103 * unless one of these endpoint routines decides that
2104 * it needs re-enabling */
2106 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2107 s3c_hsotg_irq_fifoempty(hsotg, false);
2109 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2112 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2113 dev_dbg(hsotg->dev, "PTxFEmp\n");
2115 /* See note in S3C_GINTSTS_NPTxFEmp */
2117 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2118 s3c_hsotg_irq_fifoempty(hsotg, true);
2120 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2123 if (gintsts & S3C_GINTSTS_RxFLvl) {
2124 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2125 * we need to retry s3c_hsotg_handle_rx if this is still
2128 s3c_hsotg_handle_rx(hsotg);
2129 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2132 if (gintsts & S3C_GINTSTS_ModeMis) {
2133 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2134 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2137 if (gintsts & S3C_GINTSTS_USBSusp) {
2138 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2139 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2141 call_gadget(hsotg, suspend);
2144 if (gintsts & S3C_GINTSTS_WkUpInt) {
2145 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2146 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2148 call_gadget(hsotg, resume);
2151 if (gintsts & S3C_GINTSTS_ErlySusp) {
2152 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2153 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2156 /* these next two seem to crop-up occasionally causing the core
2157 * to shutdown the USB transfer, so try clearing them and logging
2160 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2161 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2163 s3c_hsotg_dump(hsotg);
2165 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2166 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2169 if (gintsts & S3C_GINTSTS_GINNakEff) {
2170 dev_info(hsotg->dev, "GINNakEff triggered\n");
2172 s3c_hsotg_dump(hsotg);
2174 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2175 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2178 /* if we've had fifo events, we should try and go around the
2179 * loop again to see if there's any point in returning yet. */
2181 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2188 * s3c_hsotg_ep_enable - enable the given endpoint
2189 * @ep: The USB endpint to configure
2190 * @desc: The USB endpoint descriptor to configure with.
2192 * This is called from the USB gadget code's usb_ep_enable().
2194 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2195 const struct usb_endpoint_descriptor *desc)
2197 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2198 struct s3c_hsotg *hsotg = hs_ep->parent;
2199 unsigned long flags;
2200 int index = hs_ep->index;
2208 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2209 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2210 desc->wMaxPacketSize, desc->bInterval);
2212 /* not to be called for EP0 */
2213 WARN_ON(index == 0);
2215 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2216 if (dir_in != hs_ep->dir_in) {
2217 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2221 mps = le16_to_cpu(desc->wMaxPacketSize);
2223 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2225 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2226 epctrl = readl(hsotg->regs + epctrl_reg);
2228 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2229 __func__, epctrl, epctrl_reg);
2231 spin_lock_irqsave(&hs_ep->lock, flags);
2233 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2234 epctrl |= S3C_DxEPCTL_MPS(mps);
2236 /* mark the endpoint as active, otherwise the core may ignore
2237 * transactions entirely for this endpoint */
2238 epctrl |= S3C_DxEPCTL_USBActEp;
2240 /* set the NAK status on the endpoint, otherwise we might try and
2241 * do something with data that we've yet got a request to process
2242 * since the RXFIFO will take data for an endpoint even if the
2243 * size register hasn't been set.
2246 epctrl |= S3C_DxEPCTL_SNAK;
2248 /* update the endpoint state */
2249 hs_ep->ep.maxpacket = mps;
2251 /* default, set to non-periodic */
2252 hs_ep->periodic = 0;
2254 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2255 case USB_ENDPOINT_XFER_ISOC:
2256 dev_err(hsotg->dev, "no current ISOC support\n");
2260 case USB_ENDPOINT_XFER_BULK:
2261 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2264 case USB_ENDPOINT_XFER_INT:
2266 /* Allocate our TxFNum by simply using the index
2267 * of the endpoint for the moment. We could do
2268 * something better if the host indicates how
2269 * many FIFOs we are expecting to use. */
2271 hs_ep->periodic = 1;
2272 epctrl |= S3C_DxEPCTL_TxFNum(index);
2275 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2278 case USB_ENDPOINT_XFER_CONTROL:
2279 epctrl |= S3C_DxEPCTL_EPType_Control;
2283 /* for non control endpoints, set PID to D0 */
2285 epctrl |= S3C_DxEPCTL_SetD0PID;
2287 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2290 writel(epctrl, hsotg->regs + epctrl_reg);
2291 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2292 __func__, readl(hsotg->regs + epctrl_reg));
2294 /* enable the endpoint interrupt */
2295 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2298 spin_unlock_irqrestore(&hs_ep->lock, flags);
2302 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2304 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2305 struct s3c_hsotg *hsotg = hs_ep->parent;
2306 int dir_in = hs_ep->dir_in;
2307 int index = hs_ep->index;
2308 unsigned long flags;
2312 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2314 if (ep == &hsotg->eps[0].ep) {
2315 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2319 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2321 /* terminate all requests with shutdown */
2322 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2324 spin_lock_irqsave(&hs_ep->lock, flags);
2326 ctrl = readl(hsotg->regs + epctrl_reg);
2327 ctrl &= ~S3C_DxEPCTL_EPEna;
2328 ctrl &= ~S3C_DxEPCTL_USBActEp;
2329 ctrl |= S3C_DxEPCTL_SNAK;
2331 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2332 writel(ctrl, hsotg->regs + epctrl_reg);
2334 /* disable endpoint interrupts */
2335 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2337 spin_unlock_irqrestore(&hs_ep->lock, flags);
2342 * on_list - check request is on the given endpoint
2343 * @ep: The endpoint to check.
2344 * @test: The request to test if it is on the endpoint.
2346 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2348 struct s3c_hsotg_req *req, *treq;
2350 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2358 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2360 struct s3c_hsotg_req *hs_req = our_req(req);
2361 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2362 struct s3c_hsotg *hs = hs_ep->parent;
2363 unsigned long flags;
2365 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2367 if (hs_req == hs_ep->req) {
2368 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2369 return -EINPROGRESS;
2372 spin_lock_irqsave(&hs_ep->lock, flags);
2374 if (!on_list(hs_ep, hs_req)) {
2375 spin_unlock_irqrestore(&hs_ep->lock, flags);
2379 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2380 spin_unlock_irqrestore(&hs_ep->lock, flags);
2385 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2387 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2388 struct s3c_hsotg *hs = hs_ep->parent;
2389 int index = hs_ep->index;
2390 unsigned long irqflags;
2394 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2396 spin_lock_irqsave(&hs_ep->lock, irqflags);
2398 /* write both IN and OUT control registers */
2400 epreg = S3C_DIEPCTL(index);
2401 epctl = readl(hs->regs + epreg);
2404 epctl |= S3C_DxEPCTL_Stall;
2406 epctl &= ~S3C_DxEPCTL_Stall;
2408 writel(epctl, hs->regs + epreg);
2410 epreg = S3C_DOEPCTL(index);
2411 epctl = readl(hs->regs + epreg);
2414 epctl |= S3C_DxEPCTL_Stall;
2416 epctl &= ~S3C_DxEPCTL_Stall;
2418 writel(epctl, hs->regs + epreg);
2420 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2425 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2426 .enable = s3c_hsotg_ep_enable,
2427 .disable = s3c_hsotg_ep_disable,
2428 .alloc_request = s3c_hsotg_ep_alloc_request,
2429 .free_request = s3c_hsotg_ep_free_request,
2430 .queue = s3c_hsotg_ep_queue,
2431 .dequeue = s3c_hsotg_ep_dequeue,
2432 .set_halt = s3c_hsotg_ep_sethalt,
2433 /* note, don't belive we have any call for the fifo routines */
2437 * s3c_hsotg_corereset - issue softreset to the core
2438 * @hsotg: The device state
2440 * Issue a soft reset to the core, and await the core finishing it.
2442 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2447 dev_dbg(hsotg->dev, "resetting core\n");
2449 /* issue soft reset */
2450 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2454 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2455 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2457 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2458 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2465 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2467 if (timeout-- < 0) {
2468 dev_info(hsotg->dev,
2469 "%s: reset failed, GRSTCTL=%08x\n",
2474 if (grstctl & S3C_GRSTCTL_CSftRst)
2477 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2480 break; /* reset done */
2483 dev_dbg(hsotg->dev, "reset successful\n");
2487 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2489 struct s3c_hsotg *hsotg = our_hsotg;
2493 printk(KERN_ERR "%s: called with no device\n", __func__);
2498 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2502 if (driver->speed != USB_SPEED_HIGH &&
2503 driver->speed != USB_SPEED_FULL) {
2504 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2507 if (!driver->bind || !driver->setup) {
2508 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2512 WARN_ON(hsotg->driver);
2514 driver->driver.bus = NULL;
2515 hsotg->driver = driver;
2516 hsotg->gadget.dev.driver = &driver->driver;
2517 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2518 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2520 ret = device_add(&hsotg->gadget.dev);
2522 dev_err(hsotg->dev, "failed to register gadget device\n");
2526 ret = driver->bind(&hsotg->gadget);
2528 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2530 hsotg->gadget.dev.driver = NULL;
2531 hsotg->driver = NULL;
2535 /* we must now enable ep0 ready for host detection and then
2536 * set configuration. */
2538 s3c_hsotg_corereset(hsotg);
2540 /* set the PLL on, remove the HNP/SRP and set the PHY */
2541 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2542 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2544 /* looks like soft-reset changes state of FIFOs */
2545 s3c_hsotg_init_fifo(hsotg);
2547 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2549 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2551 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2552 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2553 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2554 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2555 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2556 S3C_GINTSTS_ErlySusp,
2557 hsotg->regs + S3C_GINTMSK);
2559 if (using_dma(hsotg))
2560 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2561 S3C_GAHBCFG_HBstLen_Incr4,
2562 hsotg->regs + S3C_GAHBCFG);
2564 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2566 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2567 * up being flooded with interrupts if the host is polling the
2568 * endpoint to try and read data. */
2570 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2571 S3C_DIEPMSK_INTknEPMisMsk |
2572 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2573 hsotg->regs + S3C_DIEPMSK);
2575 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2576 * DMA mode we may need this. */
2577 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2578 S3C_DOEPMSK_EPDisbldMsk |
2579 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2580 S3C_DIEPMSK_TimeOUTMsk) : 0),
2581 hsotg->regs + S3C_DOEPMSK);
2583 writel(0, hsotg->regs + S3C_DAINTMSK);
2585 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2586 readl(hsotg->regs + S3C_DIEPCTL0),
2587 readl(hsotg->regs + S3C_DOEPCTL0));
2589 /* enable in and out endpoint interrupts */
2590 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2592 /* Enable the RXFIFO when in slave mode, as this is how we collect
2593 * the data. In DMA mode, we get events from the FIFO but also
2594 * things we cannot process, so do not use it. */
2595 if (!using_dma(hsotg))
2596 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2598 /* Enable interrupts for EP0 in and out */
2599 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2600 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2602 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2603 udelay(10); /* see openiboot */
2604 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2606 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2608 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2609 writing to the EPCTL register.. */
2611 /* set to read 1 8byte packet */
2612 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2613 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2615 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2616 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2617 S3C_DxEPCTL_USBActEp,
2618 hsotg->regs + S3C_DOEPCTL0);
2620 /* enable, but don't activate EP0in */
2621 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2622 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2624 s3c_hsotg_enqueue_setup(hsotg);
2626 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2627 readl(hsotg->regs + S3C_DIEPCTL0),
2628 readl(hsotg->regs + S3C_DOEPCTL0));
2630 /* clear global NAKs */
2631 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2632 hsotg->regs + S3C_DCTL);
2634 /* must be at-least 3ms to allow bus to see disconnect */
2637 /* remove the soft-disconnect and let's go */
2638 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2640 /* report to the user, and return */
2642 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2646 hsotg->driver = NULL;
2647 hsotg->gadget.dev.driver = NULL;
2650 EXPORT_SYMBOL(usb_gadget_register_driver);
2652 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2654 struct s3c_hsotg *hsotg = our_hsotg;
2660 if (!driver || driver != hsotg->driver || !driver->unbind)
2663 /* all endpoints should be shutdown */
2664 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2665 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2667 call_gadget(hsotg, disconnect);
2669 driver->unbind(&hsotg->gadget);
2670 hsotg->driver = NULL;
2671 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2673 device_del(&hsotg->gadget.dev);
2675 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2676 driver->driver.name);
2680 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2682 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2684 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2687 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2688 .get_frame = s3c_hsotg_gadget_getframe,
2692 * s3c_hsotg_initep - initialise a single endpoint
2693 * @hsotg: The device state.
2694 * @hs_ep: The endpoint to be initialised.
2695 * @epnum: The endpoint number
2697 * Initialise the given endpoint (as part of the probe and device state
2698 * creation) to give to the gadget driver. Setup the endpoint name, any
2699 * direction information and other state that may be required.
2701 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2702 struct s3c_hsotg_ep *hs_ep,
2710 else if ((epnum % 2) == 0) {
2717 hs_ep->index = epnum;
2719 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2721 INIT_LIST_HEAD(&hs_ep->queue);
2722 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2724 spin_lock_init(&hs_ep->lock);
2726 /* add to the list of endpoints known by the gadget driver */
2728 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2730 hs_ep->parent = hsotg;
2731 hs_ep->ep.name = hs_ep->name;
2732 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2733 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2735 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2736 * an OUT endpoint, we may as well do this if in future the
2737 * code is changed to make each endpoint's direction changeable.
2740 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2741 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2743 /* if we're using dma, we need to set the next-endpoint pointer
2744 * to be something valid.
2747 if (using_dma(hsotg)) {
2748 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2749 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2750 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2755 * s3c_hsotg_otgreset - reset the OtG phy block
2756 * @hsotg: The host state.
2758 * Power up the phy, set the basic configuration and start the PHY.
2760 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2764 writel(0, S3C_PHYPWR);
2767 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2769 writel(osc | 0x10, S3C_PHYCLK);
2771 /* issue a full set of resets to the otg and core */
2773 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2774 udelay(20); /* at-least 10uS */
2775 writel(0, S3C_RSTCON);
2779 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2781 /* unmask subset of endpoint interrupts */
2783 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2784 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2785 hsotg->regs + S3C_DIEPMSK);
2787 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2788 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2789 hsotg->regs + S3C_DOEPMSK);
2791 writel(0, hsotg->regs + S3C_DAINTMSK);
2793 /* Be in disconnected state until gadget is registered */
2794 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2797 /* post global nak until we're ready */
2798 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2799 hsotg->regs + S3C_DCTL);
2804 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2805 readl(hsotg->regs + S3C_GRXFSIZ),
2806 readl(hsotg->regs + S3C_GNPTXFSIZ));
2808 s3c_hsotg_init_fifo(hsotg);
2810 /* set the PLL on, remove the HNP/SRP and set the PHY */
2811 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2812 hsotg->regs + S3C_GUSBCFG);
2814 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2815 hsotg->regs + S3C_GAHBCFG);
2818 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2820 struct device *dev = hsotg->dev;
2821 void __iomem *regs = hsotg->regs;
2825 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2826 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2827 readl(regs + S3C_DIEPMSK));
2829 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2830 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2832 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2833 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2835 /* show periodic fifo settings */
2837 for (idx = 1; idx <= 15; idx++) {
2838 val = readl(regs + S3C_DPTXFSIZn(idx));
2839 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2840 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2841 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2844 for (idx = 0; idx < 15; idx++) {
2846 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2847 readl(regs + S3C_DIEPCTL(idx)),
2848 readl(regs + S3C_DIEPTSIZ(idx)),
2849 readl(regs + S3C_DIEPDMA(idx)));
2851 val = readl(regs + S3C_DOEPCTL(idx));
2853 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2854 idx, readl(regs + S3C_DOEPCTL(idx)),
2855 readl(regs + S3C_DOEPTSIZ(idx)),
2856 readl(regs + S3C_DOEPDMA(idx)));
2860 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2861 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2866 * state_show - debugfs: show overall driver and device state.
2867 * @seq: The seq file to write to.
2868 * @v: Unused parameter.
2870 * This debugfs entry shows the overall state of the hardware and
2871 * some general information about each of the endpoints available
2874 static int state_show(struct seq_file *seq, void *v)
2876 struct s3c_hsotg *hsotg = seq->private;
2877 void __iomem *regs = hsotg->regs;
2880 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2881 readl(regs + S3C_DCFG),
2882 readl(regs + S3C_DCTL),
2883 readl(regs + S3C_DSTS));
2885 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2886 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2888 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2889 readl(regs + S3C_GINTMSK),
2890 readl(regs + S3C_GINTSTS));
2892 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2893 readl(regs + S3C_DAINTMSK),
2894 readl(regs + S3C_DAINT));
2896 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2897 readl(regs + S3C_GNPTXSTS),
2898 readl(regs + S3C_GRXSTSR));
2900 seq_printf(seq, "\nEndpoint status:\n");
2902 for (idx = 0; idx < 15; idx++) {
2905 in = readl(regs + S3C_DIEPCTL(idx));
2906 out = readl(regs + S3C_DOEPCTL(idx));
2908 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2911 in = readl(regs + S3C_DIEPTSIZ(idx));
2912 out = readl(regs + S3C_DOEPTSIZ(idx));
2914 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2917 seq_printf(seq, "\n");
2923 static int state_open(struct inode *inode, struct file *file)
2925 return single_open(file, state_show, inode->i_private);
2928 static const struct file_operations state_fops = {
2929 .owner = THIS_MODULE,
2932 .llseek = seq_lseek,
2933 .release = single_release,
2937 * fifo_show - debugfs: show the fifo information
2938 * @seq: The seq_file to write data to.
2939 * @v: Unused parameter.
2941 * Show the FIFO information for the overall fifo and all the
2942 * periodic transmission FIFOs.
2944 static int fifo_show(struct seq_file *seq, void *v)
2946 struct s3c_hsotg *hsotg = seq->private;
2947 void __iomem *regs = hsotg->regs;
2951 seq_printf(seq, "Non-periodic FIFOs:\n");
2952 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2954 val = readl(regs + S3C_GNPTXFSIZ);
2955 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2956 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
2957 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
2959 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
2961 for (idx = 1; idx <= 15; idx++) {
2962 val = readl(regs + S3C_DPTXFSIZn(idx));
2964 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2965 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2966 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2972 static int fifo_open(struct inode *inode, struct file *file)
2974 return single_open(file, fifo_show, inode->i_private);
2977 static const struct file_operations fifo_fops = {
2978 .owner = THIS_MODULE,
2981 .llseek = seq_lseek,
2982 .release = single_release,
2986 static const char *decode_direction(int is_in)
2988 return is_in ? "in" : "out";
2992 * ep_show - debugfs: show the state of an endpoint.
2993 * @seq: The seq_file to write data to.
2994 * @v: Unused parameter.
2996 * This debugfs entry shows the state of the given endpoint (one is
2997 * registered for each available).
2999 static int ep_show(struct seq_file *seq, void *v)
3001 struct s3c_hsotg_ep *ep = seq->private;
3002 struct s3c_hsotg *hsotg = ep->parent;
3003 struct s3c_hsotg_req *req;
3004 void __iomem *regs = hsotg->regs;
3005 int index = ep->index;
3006 int show_limit = 15;
3007 unsigned long flags;
3009 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3010 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3012 /* first show the register state */
3014 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3015 readl(regs + S3C_DIEPCTL(index)),
3016 readl(regs + S3C_DOEPCTL(index)));
3018 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3019 readl(regs + S3C_DIEPDMA(index)),
3020 readl(regs + S3C_DOEPDMA(index)));
3022 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3023 readl(regs + S3C_DIEPINT(index)),
3024 readl(regs + S3C_DOEPINT(index)));
3026 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3027 readl(regs + S3C_DIEPTSIZ(index)),
3028 readl(regs + S3C_DOEPTSIZ(index)));
3030 seq_printf(seq, "\n");
3031 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3032 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3034 seq_printf(seq, "request list (%p,%p):\n",
3035 ep->queue.next, ep->queue.prev);
3037 spin_lock_irqsave(&ep->lock, flags);
3039 list_for_each_entry(req, &ep->queue, queue) {
3040 if (--show_limit < 0) {
3041 seq_printf(seq, "not showing more requests...\n");
3045 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3046 req == ep->req ? '*' : ' ',
3047 req, req->req.length, req->req.buf);
3048 seq_printf(seq, "%d done, res %d\n",
3049 req->req.actual, req->req.status);
3052 spin_unlock_irqrestore(&ep->lock, flags);
3057 static int ep_open(struct inode *inode, struct file *file)
3059 return single_open(file, ep_show, inode->i_private);
3062 static const struct file_operations ep_fops = {
3063 .owner = THIS_MODULE,
3066 .llseek = seq_lseek,
3067 .release = single_release,
3071 * s3c_hsotg_create_debug - create debugfs directory and files
3072 * @hsotg: The driver state
3074 * Create the debugfs files to allow the user to get information
3075 * about the state of the system. The directory name is created
3076 * with the same name as the device itself, in case we end up
3077 * with multiple blocks in future systems.
3079 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3081 struct dentry *root;
3084 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3085 hsotg->debug_root = root;
3087 dev_err(hsotg->dev, "cannot create debug root\n");
3091 /* create general state file */
3093 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3094 hsotg, &state_fops);
3096 if (IS_ERR(hsotg->debug_file))
3097 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3099 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3102 if (IS_ERR(hsotg->debug_fifo))
3103 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3105 /* create one file for each endpoint */
3107 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3108 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3110 ep->debugfs = debugfs_create_file(ep->name, 0444,
3111 root, ep, &ep_fops);
3113 if (IS_ERR(ep->debugfs))
3114 dev_err(hsotg->dev, "failed to create %s debug file\n",
3120 * s3c_hsotg_delete_debug - cleanup debugfs entries
3121 * @hsotg: The driver state
3123 * Cleanup (remove) the debugfs files for use on module exit.
3125 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3129 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3130 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3131 debugfs_remove(ep->debugfs);
3134 debugfs_remove(hsotg->debug_file);
3135 debugfs_remove(hsotg->debug_fifo);
3136 debugfs_remove(hsotg->debug_root);
3140 * s3c_hsotg_gate - set the hardware gate for the block
3141 * @pdev: The device we bound to
3144 * Set the hardware gate setting into the block. If we end up on
3145 * something other than an S3C64XX, then we might need to change this
3146 * to using a platform data callback, or some other mechanism.
3148 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3150 unsigned long flags;
3153 local_irq_save(flags);
3155 others = __raw_readl(S3C64XX_OTHERS);
3157 others |= S3C64XX_OTHERS_USBMASK;
3159 others &= ~S3C64XX_OTHERS_USBMASK;
3160 __raw_writel(others, S3C64XX_OTHERS);
3162 local_irq_restore(flags);
3165 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3167 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3169 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3170 struct device *dev = &pdev->dev;
3171 struct s3c_hsotg *hsotg;
3172 struct resource *res;
3177 plat = &s3c_hsotg_default_pdata;
3179 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3180 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3183 dev_err(dev, "cannot get memory\n");
3190 platform_set_drvdata(pdev, hsotg);
3192 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3194 dev_err(dev, "cannot find register resource 0\n");
3199 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3201 if (!hsotg->regs_res) {
3202 dev_err(dev, "cannot reserve registers\n");
3207 hsotg->regs = ioremap(res->start, resource_size(res));
3209 dev_err(dev, "cannot map registers\n");
3214 ret = platform_get_irq(pdev, 0);
3216 dev_err(dev, "cannot find IRQ\n");
3222 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3224 dev_err(dev, "cannot claim IRQ\n");
3228 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3230 device_initialize(&hsotg->gadget.dev);
3232 dev_set_name(&hsotg->gadget.dev, "gadget");
3234 hsotg->gadget.is_dualspeed = 1;
3235 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3236 hsotg->gadget.name = dev_name(dev);
3238 hsotg->gadget.dev.parent = dev;
3239 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3241 /* setup endpoint information */
3243 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3244 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3246 /* allocate EP0 request */
3248 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3250 if (!hsotg->ctrl_req) {
3251 dev_err(dev, "failed to allocate ctrl req\n");
3255 /* reset the system */
3257 s3c_hsotg_gate(pdev, true);
3259 s3c_hsotg_otgreset(hsotg);
3260 s3c_hsotg_corereset(hsotg);
3261 s3c_hsotg_init(hsotg);
3263 /* initialise the endpoints now the core has been initialised */
3264 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3265 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3267 s3c_hsotg_create_debug(hsotg);
3269 s3c_hsotg_dump(hsotg);
3275 iounmap(hsotg->regs);
3278 release_resource(hsotg->regs_res);
3279 kfree(hsotg->regs_res);
3286 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3288 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3290 s3c_hsotg_delete_debug(hsotg);
3292 usb_gadget_unregister_driver(hsotg->driver);
3294 free_irq(hsotg->irq, hsotg);
3295 iounmap(hsotg->regs);
3297 release_resource(hsotg->regs_res);
3298 kfree(hsotg->regs_res);
3300 s3c_hsotg_gate(pdev, false);
3307 #define s3c_hsotg_suspend NULL
3308 #define s3c_hsotg_resume NULL
3311 static struct platform_driver s3c_hsotg_driver = {
3313 .name = "s3c-hsotg",
3314 .owner = THIS_MODULE,
3316 .probe = s3c_hsotg_probe,
3317 .remove = __devexit_p(s3c_hsotg_remove),
3318 .suspend = s3c_hsotg_suspend,
3319 .resume = s3c_hsotg_resume,
3322 static int __init s3c_hsotg_modinit(void)
3324 return platform_driver_register(&s3c_hsotg_driver);
3327 static void __exit s3c_hsotg_modexit(void)
3329 platform_driver_unregister(&s3c_hsotg_driver);
3332 module_init(s3c_hsotg_modinit);
3333 module_exit(s3c_hsotg_modexit);
3335 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3336 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3337 MODULE_LICENSE("GPL");
3338 MODULE_ALIAS("platform:s3c-hsotg");