1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
34 #include <plat/regs-usb-hsotg-phy.h>
35 #include <plat/regs-usb-hsotg.h>
36 #include <mach/regs-sys.h>
37 #include <plat/udc-hs.h>
39 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 * Unfortunately there seems to be a limit of the amount of data that can
44 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
45 * packets (which practially means 1 packet and 63 bytes of data) when the
48 * This means if we are wanting to move >127 bytes of data, we need to
49 * split the transactions up, but just doing one packet at a time does
50 * not work (this may be an implicit DATA0 PID on first packet of the
51 * transaction) and doing 2 packets is outside the controller's limits.
53 * If we try to lower the MPS size for EP0, then no transfers work properly
54 * for EP0, and the system will fail basic enumeration. As no cause for this
55 * has currently been found, we cannot support any large IN transfers for
58 #define EP0_MPS_LIMIT 64
64 * struct s3c_hsotg_ep - driver endpoint definition.
65 * @ep: The gadget layer representation of the endpoint.
66 * @name: The driver generated name for the endpoint.
67 * @queue: Queue of requests for this endpoint.
68 * @parent: Reference back to the parent device structure.
69 * @req: The current request that the endpoint is processing. This is
70 * used to indicate an request has been loaded onto the endpoint
71 * and has yet to be completed (maybe due to data move, or simply
72 * awaiting an ack from the core all the data has been completed).
73 * @debugfs: File entry for debugfs file for this endpoint.
74 * @lock: State lock to protect contents of endpoint.
75 * @dir_in: Set to true if this endpoint is of the IN direction, which
76 * means that it is sending data to the Host.
77 * @index: The index for the endpoint registers.
78 * @name: The name array passed to the USB core.
79 * @halted: Set if the endpoint has been halted.
80 * @periodic: Set if this is a periodic ep, such as Interrupt
81 * @sent_zlp: Set if we've sent a zero-length packet.
82 * @total_data: The total number of data bytes done.
83 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
84 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
85 * @last_load: The offset of data for the last start of request.
86 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
88 * This is the driver's state for each registered enpoint, allowing it
89 * to keep track of transactions that need doing. Each endpoint has a
90 * lock to protect the state, to try and avoid using an overall lock
91 * for the host controller as much as possible.
93 * For periodic IN endpoints, we have fifo_size and fifo_load to try
94 * and keep track of the amount of data in the periodic FIFO for each
95 * of these as we don't have a status register that tells us how much
96 * is in each of them. (note, this may actually be useless information
97 * as in shared-fifo mode periodic in acts like a single-frame packet
100 struct s3c_hsotg_ep {
102 struct list_head queue;
103 struct s3c_hsotg *parent;
104 struct s3c_hsotg_req *req;
105 struct dentry *debugfs;
109 unsigned long total_data;
110 unsigned int size_loaded;
111 unsigned int last_load;
112 unsigned int fifo_load;
113 unsigned short fifo_size;
115 unsigned char dir_in;
118 unsigned int halted:1;
119 unsigned int periodic:1;
120 unsigned int sent_zlp:1;
125 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
128 * struct s3c_hsotg - driver state.
129 * @dev: The parent device supplied to the probe function
130 * @driver: USB gadget driver
131 * @plat: The platform specific configuration data.
132 * @regs: The memory area mapped for accessing registers.
133 * @regs_res: The resource that was allocated when claiming register space.
134 * @irq: The IRQ number we are using
135 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
136 * @debug_root: root directrory for debugfs.
137 * @debug_file: main status file for debugfs.
138 * @debug_fifo: FIFO status file for debugfs.
139 * @ep0_reply: Request used for ep0 reply.
140 * @ep0_buff: Buffer for EP0 reply data, if needed.
141 * @ctrl_buff: Buffer for EP0 control requests.
142 * @ctrl_req: Request for EP0 control packets.
143 * @eps: The endpoints being supplied to the gadget framework
147 struct usb_gadget_driver *driver;
148 struct s3c_hsotg_plat *plat;
151 struct resource *regs_res;
154 unsigned int dedicated_fifos:1;
156 struct dentry *debug_root;
157 struct dentry *debug_file;
158 struct dentry *debug_fifo;
160 struct usb_request *ep0_reply;
161 struct usb_request *ctrl_req;
165 struct usb_gadget gadget;
166 struct s3c_hsotg_ep eps[];
170 * struct s3c_hsotg_req - data transfer request
171 * @req: The USB gadget request
172 * @queue: The list of requests for the endpoint this is queued for.
173 * @in_progress: Has already had size/packets written to core
174 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
176 struct s3c_hsotg_req {
177 struct usb_request req;
178 struct list_head queue;
179 unsigned char in_progress;
180 unsigned char mapped;
183 /* conversion functions */
184 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
186 return container_of(req, struct s3c_hsotg_req, req);
189 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
191 return container_of(ep, struct s3c_hsotg_ep, ep);
194 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
196 return container_of(gadget, struct s3c_hsotg, gadget);
199 static inline void __orr32(void __iomem *ptr, u32 val)
201 writel(readl(ptr) | val, ptr);
204 static inline void __bic32(void __iomem *ptr, u32 val)
206 writel(readl(ptr) & ~val, ptr);
209 /* forward decleration of functions */
210 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
213 * using_dma - return the DMA status of the driver.
214 * @hsotg: The driver state.
216 * Return true if we're using DMA.
218 * Currently, we have the DMA support code worked into everywhere
219 * that needs it, but the AMBA DMA implementation in the hardware can
220 * only DMA from 32bit aligned addresses. This means that gadgets such
221 * as the CDC Ethernet cannot work as they often pass packets which are
224 * Unfortunately the choice to use DMA or not is global to the controller
225 * and seems to be only settable when the controller is being put through
226 * a core reset. This means we either need to fix the gadgets to take
227 * account of DMA alignment, or add bounce buffers (yuerk).
229 * Until this issue is sorted out, we always return 'false'.
231 static inline bool using_dma(struct s3c_hsotg *hsotg)
233 return false; /* support is not complete */
237 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
238 * @hsotg: The device state
239 * @ints: A bitmask of the interrupts to enable
241 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
243 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
246 new_gsintmsk = gsintmsk | ints;
248 if (new_gsintmsk != gsintmsk) {
249 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
250 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
255 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
256 * @hsotg: The device state
257 * @ints: A bitmask of the interrupts to enable
259 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
261 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
264 new_gsintmsk = gsintmsk & ~ints;
266 if (new_gsintmsk != gsintmsk)
267 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
271 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
272 * @hsotg: The device state
273 * @ep: The endpoint index
274 * @dir_in: True if direction is in.
275 * @en: The enable value, true to enable
277 * Set or clear the mask for an individual endpoint's interrupt
280 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
281 unsigned int ep, unsigned int dir_in,
291 local_irq_save(flags);
292 daint = readl(hsotg->regs + S3C_DAINTMSK);
297 writel(daint, hsotg->regs + S3C_DAINTMSK);
298 local_irq_restore(flags);
302 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
303 * @hsotg: The device instance.
305 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
313 /* the ryu 2.6.24 release ahs
314 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
315 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
316 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
317 hsotg->regs + S3C_GNPTXFSIZ);
320 /* set FIFO sizes to 2048/1024 */
322 writel(2048, hsotg->regs + S3C_GRXFSIZ);
323 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
324 S3C_GNPTXFSIZ_NPTxFDep(1024),
325 hsotg->regs + S3C_GNPTXFSIZ);
327 /* arange all the rest of the TX FIFOs, as some versions of this
328 * block have overlapping default addresses. This also ensures
329 * that if the settings have been changed, then they are set to
332 /* start at the end of the GNPTXFSIZ, rounded up */
336 /* currently we allocate TX FIFOs for all possible endpoints,
337 * and assume that they are all the same size. */
339 for (ep = 0; ep <= 15; ep++) {
341 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
344 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
347 /* according to p428 of the design guide, we need to ensure that
348 * all fifos are flushed before continuing */
350 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
351 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
353 /* wait until the fifos are both flushed */
356 val = readl(hsotg->regs + S3C_GRSTCTL);
358 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
361 if (--timeout == 0) {
363 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
370 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
374 * @ep: USB endpoint to allocate request for.
375 * @flags: Allocation flags
377 * Allocate a new USB request structure appropriate for the specified endpoint
379 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
382 struct s3c_hsotg_req *req;
384 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
388 INIT_LIST_HEAD(&req->queue);
390 req->req.dma = DMA_ADDR_INVALID;
395 * is_ep_periodic - return true if the endpoint is in periodic mode.
396 * @hs_ep: The endpoint to query.
398 * Returns true if the endpoint is in periodic mode, meaning it is being
399 * used for an Interrupt or ISO transfer.
401 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
403 return hs_ep->periodic;
407 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
408 * @hsotg: The device state.
409 * @hs_ep: The endpoint for the request
410 * @hs_req: The request being processed.
412 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
413 * of a request to ensure the buffer is ready for access by the caller.
415 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
416 struct s3c_hsotg_ep *hs_ep,
417 struct s3c_hsotg_req *hs_req)
419 struct usb_request *req = &hs_req->req;
420 enum dma_data_direction dir;
422 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
424 /* ignore this if we're not moving any data */
425 if (hs_req->req.length == 0)
428 if (hs_req->mapped) {
429 /* we mapped this, so unmap and remove the dma */
431 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
433 req->dma = DMA_ADDR_INVALID;
436 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
441 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
442 * @hsotg: The controller state.
443 * @hs_ep: The endpoint we're going to write for.
444 * @hs_req: The request to write data for.
446 * This is called when the TxFIFO has some space in it to hold a new
447 * transmission and we have something to give it. The actual setup of
448 * the data size is done elsewhere, so all we have to do is to actually
451 * The return value is zero if there is more space (or nothing was done)
452 * otherwise -ENOSPC is returned if the FIFO space was used up.
454 * This routine is only needed for PIO
456 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
457 struct s3c_hsotg_ep *hs_ep,
458 struct s3c_hsotg_req *hs_req)
460 bool periodic = is_ep_periodic(hs_ep);
461 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
462 int buf_pos = hs_req->req.actual;
463 int to_write = hs_ep->size_loaded;
468 to_write -= (buf_pos - hs_ep->last_load);
470 /* if there's nothing to write, get out early */
474 if (periodic && !hsotg->dedicated_fifos) {
475 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
479 /* work out how much data was loaded so we can calculate
480 * how much data is left in the fifo. */
482 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
484 /* if shared fifo, we cannot write anything until the
485 * previous data has been completely sent.
487 if (hs_ep->fifo_load != 0) {
488 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
492 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
494 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
496 /* how much of the data has moved */
497 size_done = hs_ep->size_loaded - size_left;
499 /* how much data is left in the fifo */
500 can_write = hs_ep->fifo_load - size_done;
501 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
502 __func__, can_write);
504 can_write = hs_ep->fifo_size - can_write;
505 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
506 __func__, can_write);
508 if (can_write <= 0) {
509 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
512 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
513 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
518 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
520 "%s: no queue slots available (0x%08x)\n",
523 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
527 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
528 can_write *= 4; /* fifo size is in 32bit quantities. */
531 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
532 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
534 /* limit to 512 bytes of data, it seems at least on the non-periodic
535 * FIFO, requests of >512 cause the endpoint to get stuck with a
536 * fragment of the end of the transfer in it.
541 /* limit the write to one max-packet size worth of data, but allow
542 * the transfer to return that it did not run out of fifo space
544 if (to_write > hs_ep->ep.maxpacket) {
545 to_write = hs_ep->ep.maxpacket;
547 s3c_hsotg_en_gsint(hsotg,
548 periodic ? S3C_GINTSTS_PTxFEmp :
549 S3C_GINTSTS_NPTxFEmp);
552 /* see if we can write data */
554 if (to_write > can_write) {
555 to_write = can_write;
556 pkt_round = to_write % hs_ep->ep.maxpacket;
558 /* Not sure, but we probably shouldn't be writing partial
559 * packets into the FIFO, so round the write down to an
560 * exact number of packets.
562 * Note, we do not currently check to see if we can ever
563 * write a full packet or not to the FIFO.
567 to_write -= pkt_round;
569 /* enable correct FIFO interrupt to alert us when there
570 * is more room left. */
572 s3c_hsotg_en_gsint(hsotg,
573 periodic ? S3C_GINTSTS_PTxFEmp :
574 S3C_GINTSTS_NPTxFEmp);
577 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
578 to_write, hs_req->req.length, can_write, buf_pos);
583 hs_req->req.actual = buf_pos + to_write;
584 hs_ep->total_data += to_write;
587 hs_ep->fifo_load += to_write;
589 to_write = DIV_ROUND_UP(to_write, 4);
590 data = hs_req->req.buf + buf_pos;
592 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
594 return (to_write >= can_write) ? -ENOSPC : 0;
598 * get_ep_limit - get the maximum data legnth for this endpoint
599 * @hs_ep: The endpoint
601 * Return the maximum data that can be queued in one go on a given endpoint
602 * so that transfers that are too long can be split.
604 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
606 int index = hs_ep->index;
611 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
612 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
616 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
622 /* we made the constant loading easier above by using +1 */
626 /* constrain by packet count if maxpkts*pktsize is greater
627 * than the length register size. */
629 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
630 maxsize = maxpkt * hs_ep->ep.maxpacket;
636 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
637 * @hsotg: The controller state.
638 * @hs_ep: The endpoint to process a request for
639 * @hs_req: The request to start.
640 * @continuing: True if we are doing more for the current request.
642 * Start the given request running by setting the endpoint registers
643 * appropriately, and writing any data to the FIFOs.
645 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
646 struct s3c_hsotg_ep *hs_ep,
647 struct s3c_hsotg_req *hs_req,
650 struct usb_request *ureq = &hs_req->req;
651 int index = hs_ep->index;
652 int dir_in = hs_ep->dir_in;
662 if (hs_ep->req && !continuing) {
663 dev_err(hsotg->dev, "%s: active request\n", __func__);
666 } else if (hs_ep->req != hs_req && continuing) {
668 "%s: continue different req\n", __func__);
674 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
675 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
677 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
678 __func__, readl(hsotg->regs + epctrl_reg), index,
679 hs_ep->dir_in ? "in" : "out");
681 length = ureq->length - ureq->actual;
685 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
686 ureq->buf, length, ureq->dma,
687 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
689 maxreq = get_ep_limit(hs_ep);
690 if (length > maxreq) {
691 int round = maxreq % hs_ep->ep.maxpacket;
693 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
694 __func__, length, maxreq, round);
696 /* round down to multiple of packets */
704 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
706 packets = 1; /* send one packet if length is zero. */
708 if (dir_in && index != 0)
709 epsize = S3C_DxEPTSIZ_MC(1);
713 if (index != 0 && ureq->zero) {
714 /* test for the packets being exactly right for the
717 if (length == (packets * hs_ep->ep.maxpacket))
721 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
722 epsize |= S3C_DxEPTSIZ_XferSize(length);
724 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
725 __func__, packets, length, ureq->length, epsize, epsize_reg);
727 /* store the request as the current one we're doing */
730 /* write size / packets */
731 writel(epsize, hsotg->regs + epsize_reg);
733 ctrl = readl(hsotg->regs + epctrl_reg);
735 if (ctrl & S3C_DxEPCTL_Stall) {
736 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
738 /* not sure what we can do here, if it is EP0 then we should
739 * get this cleared once the endpoint has transmitted the
740 * STALL packet, otherwise it needs to be cleared by the
745 if (using_dma(hsotg)) {
746 unsigned int dma_reg;
748 /* write DMA address to control register, buffer already
749 * synced by s3c_hsotg_ep_queue(). */
751 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
752 writel(ureq->dma, hsotg->regs + dma_reg);
754 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
755 __func__, ureq->dma, dma_reg);
758 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
759 ctrl |= S3C_DxEPCTL_USBActEp;
760 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
762 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
763 writel(ctrl, hsotg->regs + epctrl_reg);
765 /* set these, it seems that DMA support increments past the end
766 * of the packet buffer so we need to calculate the length from
767 * this information. */
768 hs_ep->size_loaded = length;
769 hs_ep->last_load = ureq->actual;
771 if (dir_in && !using_dma(hsotg)) {
772 /* set these anyway, we may need them for non-periodic in */
773 hs_ep->fifo_load = 0;
775 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
778 /* clear the INTknTXFEmpMsk when we start request, more as a aide
779 * to debugging to see what is going on. */
781 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
782 hsotg->regs + S3C_DIEPINT(index));
784 /* Note, trying to clear the NAK here causes problems with transmit
785 * on the S3C6400 ending up with the TXFIFO becomming full. */
787 /* check ep is enabled */
788 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
790 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
791 index, readl(hsotg->regs + epctrl_reg));
793 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
794 __func__, readl(hsotg->regs + epctrl_reg));
798 * s3c_hsotg_map_dma - map the DMA memory being used for the request
799 * @hsotg: The device state.
800 * @hs_ep: The endpoint the request is on.
801 * @req: The request being processed.
803 * We've been asked to queue a request, so ensure that the memory buffer
804 * is correctly setup for DMA. If we've been passed an extant DMA address
805 * then ensure the buffer has been synced to memory. If our buffer has no
806 * DMA memory, then we map the memory and mark our request to allow us to
807 * cleanup on completion.
809 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
810 struct s3c_hsotg_ep *hs_ep,
811 struct usb_request *req)
813 enum dma_data_direction dir;
814 struct s3c_hsotg_req *hs_req = our_req(req);
816 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
818 /* if the length is zero, ignore the DMA data */
819 if (hs_req->req.length == 0)
822 if (req->dma == DMA_ADDR_INVALID) {
825 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
827 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
831 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
834 dma_unmap_single(hsotg->dev, dma, req->length, dir);
841 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
848 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
849 __func__, req->buf, req->length);
854 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
857 struct s3c_hsotg_req *hs_req = our_req(req);
858 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
859 struct s3c_hsotg *hs = hs_ep->parent;
860 unsigned long irqflags;
863 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
864 ep->name, req, req->length, req->buf, req->no_interrupt,
865 req->zero, req->short_not_ok);
867 /* initialise status of the request */
868 INIT_LIST_HEAD(&hs_req->queue);
870 req->status = -EINPROGRESS;
872 /* if we're using DMA, sync the buffers as necessary */
874 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
879 spin_lock_irqsave(&hs_ep->lock, irqflags);
881 first = list_empty(&hs_ep->queue);
882 list_add_tail(&hs_req->queue, &hs_ep->queue);
885 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
887 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
892 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
893 struct usb_request *req)
895 struct s3c_hsotg_req *hs_req = our_req(req);
901 * s3c_hsotg_complete_oursetup - setup completion callback
902 * @ep: The endpoint the request was on.
903 * @req: The request completed.
905 * Called on completion of any requests the driver itself
906 * submitted that need cleaning up.
908 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
909 struct usb_request *req)
911 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
912 struct s3c_hsotg *hsotg = hs_ep->parent;
914 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
916 s3c_hsotg_ep_free_request(ep, req);
920 * ep_from_windex - convert control wIndex value to endpoint
921 * @hsotg: The driver state.
922 * @windex: The control request wIndex field (in host order).
924 * Convert the given wIndex into a pointer to an driver endpoint
925 * structure, or return NULL if it is not a valid endpoint.
927 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
930 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
931 int dir = (windex & USB_DIR_IN) ? 1 : 0;
932 int idx = windex & 0x7F;
937 if (idx > S3C_HSOTG_EPS)
940 if (idx && ep->dir_in != dir)
947 * s3c_hsotg_send_reply - send reply to control request
948 * @hsotg: The device state
950 * @buff: Buffer for request
951 * @length: Length of reply.
953 * Create a request and queue it on the given endpoint. This is useful as
954 * an internal method of sending replies to certain control requests, etc.
956 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
957 struct s3c_hsotg_ep *ep,
961 struct usb_request *req;
964 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
966 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
967 hsotg->ep0_reply = req;
969 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
973 req->buf = hsotg->ep0_buff;
974 req->length = length;
975 req->zero = 1; /* always do zero-length final transfer */
976 req->complete = s3c_hsotg_complete_oursetup;
979 memcpy(req->buf, buff, length);
983 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
985 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
993 * s3c_hsotg_process_req_status - process request GET_STATUS
994 * @hsotg: The device state
995 * @ctrl: USB control request
997 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
998 struct usb_ctrlrequest *ctrl)
1000 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1001 struct s3c_hsotg_ep *ep;
1005 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1008 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1012 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1013 case USB_RECIP_DEVICE:
1014 reply = cpu_to_le16(0); /* bit 0 => self powered,
1015 * bit 1 => remote wakeup */
1018 case USB_RECIP_INTERFACE:
1019 /* currently, the data result should be zero */
1020 reply = cpu_to_le16(0);
1023 case USB_RECIP_ENDPOINT:
1024 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1028 reply = cpu_to_le16(ep->halted ? 1 : 0);
1035 if (le16_to_cpu(ctrl->wLength) != 2)
1038 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1040 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1047 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1050 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1051 * @hsotg: The device state
1052 * @ctrl: USB control request
1054 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1055 struct usb_ctrlrequest *ctrl)
1057 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1058 struct s3c_hsotg_ep *ep;
1060 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1061 __func__, set ? "SET" : "CLEAR");
1063 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1064 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1066 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1067 __func__, le16_to_cpu(ctrl->wIndex));
1071 switch (le16_to_cpu(ctrl->wValue)) {
1072 case USB_ENDPOINT_HALT:
1073 s3c_hsotg_ep_sethalt(&ep->ep, set);
1080 return -ENOENT; /* currently only deal with endpoint */
1086 * s3c_hsotg_process_control - process a control request
1087 * @hsotg: The device state
1088 * @ctrl: The control request received
1090 * The controller has received the SETUP phase of a control request, and
1091 * needs to work out what to do next (and whether to pass it on to the
1094 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1095 struct usb_ctrlrequest *ctrl)
1097 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1103 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1104 ctrl->bRequest, ctrl->bRequestType,
1105 ctrl->wValue, ctrl->wLength);
1107 /* record the direction of the request, for later use when enquing
1108 * packets onto EP0. */
1110 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1111 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1113 /* if we've no data with this request, then the last part of the
1114 * transaction is going to implicitly be IN. */
1115 if (ctrl->wLength == 0)
1118 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1119 switch (ctrl->bRequest) {
1120 case USB_REQ_SET_ADDRESS:
1121 dcfg = readl(hsotg->regs + S3C_DCFG);
1122 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1123 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1124 writel(dcfg, hsotg->regs + S3C_DCFG);
1126 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1128 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1131 case USB_REQ_GET_STATUS:
1132 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1135 case USB_REQ_CLEAR_FEATURE:
1136 case USB_REQ_SET_FEATURE:
1137 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1142 /* as a fallback, try delivering it to the driver to deal with */
1144 if (ret == 0 && hsotg->driver) {
1145 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1147 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1152 /* need to generate zlp in reply or take data */
1153 /* todo - deal with any data we might be sent? */
1154 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1158 /* the request is either unhandlable, or is not formatted correctly
1159 * so respond with a STALL for the status stage to indicate failure.
1166 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1167 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1169 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later. */
1172 ctrl = readl(hsotg->regs + reg);
1173 ctrl |= S3C_DxEPCTL_Stall;
1174 ctrl |= S3C_DxEPCTL_CNAK;
1175 writel(ctrl, hsotg->regs + reg);
1178 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1179 ctrl, reg, readl(hsotg->regs + reg));
1181 /* don't belive we need to anything more to get the EP
1182 * to reply with a STALL packet */
1186 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1189 * s3c_hsotg_complete_setup - completion of a setup transfer
1190 * @ep: The endpoint the request was on.
1191 * @req: The request completed.
1193 * Called on completion of any requests the driver itself submitted for
1196 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1197 struct usb_request *req)
1199 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1200 struct s3c_hsotg *hsotg = hs_ep->parent;
1202 if (req->status < 0) {
1203 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1207 if (req->actual == 0)
1208 s3c_hsotg_enqueue_setup(hsotg);
1210 s3c_hsotg_process_control(hsotg, req->buf);
1214 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1215 * @hsotg: The device state.
1217 * Enqueue a request on EP0 if necessary to received any SETUP packets
1218 * received from the host.
1220 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1222 struct usb_request *req = hsotg->ctrl_req;
1223 struct s3c_hsotg_req *hs_req = our_req(req);
1226 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1230 req->buf = hsotg->ctrl_buff;
1231 req->complete = s3c_hsotg_complete_setup;
1233 if (!list_empty(&hs_req->queue)) {
1234 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1238 hsotg->eps[0].dir_in = 0;
1240 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1242 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1243 /* Don't think there's much we can do other than watch the
1249 * get_ep_head - return the first request on the endpoint
1250 * @hs_ep: The controller endpoint to get
1252 * Get the first request on the endpoint.
1254 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1256 if (list_empty(&hs_ep->queue))
1259 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1263 * s3c_hsotg_complete_request - complete a request given to us
1264 * @hsotg: The device state.
1265 * @hs_ep: The endpoint the request was on.
1266 * @hs_req: The request to complete.
1267 * @result: The result code (0 => Ok, otherwise errno)
1269 * The given request has finished, so call the necessary completion
1270 * if it has one and then look to see if we can start a new request
1273 * Note, expects the ep to already be locked as appropriate.
1275 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1276 struct s3c_hsotg_ep *hs_ep,
1277 struct s3c_hsotg_req *hs_req,
1283 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1287 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1288 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1290 /* only replace the status if we've not already set an error
1291 * from a previous transaction */
1293 if (hs_req->req.status == -EINPROGRESS)
1294 hs_req->req.status = result;
1297 list_del_init(&hs_req->queue);
1299 if (using_dma(hsotg))
1300 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1302 /* call the complete request with the locks off, just in case the
1303 * request tries to queue more work for this endpoint. */
1305 if (hs_req->req.complete) {
1306 spin_unlock(&hs_ep->lock);
1307 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1308 spin_lock(&hs_ep->lock);
1311 /* Look to see if there is anything else to do. Note, the completion
1312 * of the previous request may have caused a new request to be started
1313 * so be careful when doing this. */
1315 if (!hs_ep->req && result >= 0) {
1316 restart = !list_empty(&hs_ep->queue);
1318 hs_req = get_ep_head(hs_ep);
1319 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1325 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1326 * @hsotg: The device state.
1327 * @hs_ep: The endpoint the request was on.
1328 * @hs_req: The request to complete.
1329 * @result: The result code (0 => Ok, otherwise errno)
1331 * See s3c_hsotg_complete_request(), but called with the endpoint's
1334 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1335 struct s3c_hsotg_ep *hs_ep,
1336 struct s3c_hsotg_req *hs_req,
1339 unsigned long flags;
1341 spin_lock_irqsave(&hs_ep->lock, flags);
1342 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1343 spin_unlock_irqrestore(&hs_ep->lock, flags);
1347 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1348 * @hsotg: The device state.
1349 * @ep_idx: The endpoint index for the data
1350 * @size: The size of data in the fifo, in bytes
1352 * The FIFO status shows there is data to read from the FIFO for a given
1353 * endpoint, so sort out whether we need to read the data into a request
1354 * that has been made for that endpoint.
1356 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1358 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1359 struct s3c_hsotg_req *hs_req = hs_ep->req;
1360 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1366 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1369 dev_warn(hsotg->dev,
1370 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1371 __func__, size, ep_idx, epctl);
1373 /* dump the data from the FIFO, we've nothing we can do */
1374 for (ptr = 0; ptr < size; ptr += 4)
1380 spin_lock(&hs_ep->lock);
1383 read_ptr = hs_req->req.actual;
1384 max_req = hs_req->req.length - read_ptr;
1386 if (to_read > max_req) {
1387 /* more data appeared than we where willing
1388 * to deal with in this request.
1391 /* currently we don't deal this */
1395 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1396 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1398 hs_ep->total_data += to_read;
1399 hs_req->req.actual += to_read;
1400 to_read = DIV_ROUND_UP(to_read, 4);
1402 /* note, we might over-write the buffer end by 3 bytes depending on
1403 * alignment of the data. */
1404 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1406 spin_unlock(&hs_ep->lock);
1410 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1411 * @hsotg: The device instance
1412 * @req: The request currently on this endpoint
1414 * Generate a zero-length IN packet request for terminating a SETUP
1417 * Note, since we don't write any data to the TxFIFO, then it is
1418 * currently belived that we do not need to wait for any space in
1421 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1422 struct s3c_hsotg_req *req)
1427 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1431 if (req->req.length == 0) {
1432 hsotg->eps[0].sent_zlp = 1;
1433 s3c_hsotg_enqueue_setup(hsotg);
1437 hsotg->eps[0].dir_in = 1;
1438 hsotg->eps[0].sent_zlp = 1;
1440 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1442 /* issue a zero-sized packet to terminate this */
1443 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1444 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1446 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1447 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1448 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1449 ctrl |= S3C_DxEPCTL_USBActEp;
1450 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1454 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1455 * @hsotg: The device instance
1456 * @epnum: The endpoint received from
1457 * @was_setup: Set if processing a SetupDone event.
1459 * The RXFIFO has delivered an OutDone event, which means that the data
1460 * transfer for an OUT endpoint has been completed, either by a short
1461 * packet or by the finish of a transfer.
1463 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1464 int epnum, bool was_setup)
1466 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1467 struct s3c_hsotg_req *hs_req = hs_ep->req;
1468 struct usb_request *req = &hs_req->req;
1472 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1476 if (using_dma(hsotg)) {
1477 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1481 /* Calculate the size of the transfer by checking how much
1482 * is left in the endpoint size register and then working it
1483 * out from the amount we loaded for the transfer.
1485 * We need to do this as DMA pointers are always 32bit aligned
1486 * so may overshoot/undershoot the transfer.
1489 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1491 size_done = hs_ep->size_loaded - size_left;
1492 size_done += hs_ep->last_load;
1494 req->actual = size_done;
1497 if (req->actual < req->length && req->short_not_ok) {
1498 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1499 __func__, req->actual, req->length);
1501 /* todo - what should we return here? there's no one else
1502 * even bothering to check the status. */
1506 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1507 s3c_hsotg_send_zlp(hsotg, hs_req);
1510 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1514 * s3c_hsotg_read_frameno - read current frame number
1515 * @hsotg: The device instance
1517 * Return the current frame number
1519 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1523 dsts = readl(hsotg->regs + S3C_DSTS);
1524 dsts &= S3C_DSTS_SOFFN_MASK;
1525 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1531 * s3c_hsotg_handle_rx - RX FIFO has data
1532 * @hsotg: The device instance
1534 * The IRQ handler has detected that the RX FIFO has some data in it
1535 * that requires processing, so find out what is in there and do the
1538 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1539 * chunks, so if you have x packets received on an endpoint you'll get x
1540 * FIFO events delivered, each with a packet's worth of data in it.
1542 * When using DMA, we should not be processing events from the RXFIFO
1543 * as the actual data should be sent to the memory directly and we turn
1544 * on the completion interrupts to get notifications of transfer completion.
1546 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1548 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1549 u32 epnum, status, size;
1551 WARN_ON(using_dma(hsotg));
1553 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1554 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1556 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1557 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1560 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1561 __func__, grxstsr, size, epnum);
1563 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1565 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1566 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1567 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1570 case __status(S3C_GRXSTS_PktSts_OutDone):
1571 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1572 s3c_hsotg_read_frameno(hsotg));
1574 if (!using_dma(hsotg))
1575 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1578 case __status(S3C_GRXSTS_PktSts_SetupDone):
1580 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1581 s3c_hsotg_read_frameno(hsotg),
1582 readl(hsotg->regs + S3C_DOEPCTL(0)));
1584 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1587 case __status(S3C_GRXSTS_PktSts_OutRX):
1588 s3c_hsotg_rx_data(hsotg, epnum, size);
1591 case __status(S3C_GRXSTS_PktSts_SetupRX):
1593 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1594 s3c_hsotg_read_frameno(hsotg),
1595 readl(hsotg->regs + S3C_DOEPCTL(0)));
1597 s3c_hsotg_rx_data(hsotg, epnum, size);
1601 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1604 s3c_hsotg_dump(hsotg);
1610 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1611 * @mps: The maximum packet size in bytes.
1613 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1617 return S3C_D0EPCTL_MPS_64;
1619 return S3C_D0EPCTL_MPS_32;
1621 return S3C_D0EPCTL_MPS_16;
1623 return S3C_D0EPCTL_MPS_8;
1626 /* bad max packet size, warn and return invalid result */
1632 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1633 * @hsotg: The driver state.
1634 * @ep: The index number of the endpoint
1635 * @mps: The maximum packet size in bytes
1637 * Configure the maximum packet size for the given endpoint, updating
1638 * the hardware control registers to reflect this.
1640 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1641 unsigned int ep, unsigned int mps)
1643 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1644 void __iomem *regs = hsotg->regs;
1649 /* EP0 is a special case */
1650 mpsval = s3c_hsotg_ep0_mps(mps);
1654 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1660 hs_ep->ep.maxpacket = mps;
1662 /* update both the in and out endpoint controldir_ registers, even
1663 * if one of the directions may not be in use. */
1665 reg = readl(regs + S3C_DIEPCTL(ep));
1666 reg &= ~S3C_DxEPCTL_MPS_MASK;
1668 writel(reg, regs + S3C_DIEPCTL(ep));
1670 reg = readl(regs + S3C_DOEPCTL(ep));
1671 reg &= ~S3C_DxEPCTL_MPS_MASK;
1673 writel(reg, regs + S3C_DOEPCTL(ep));
1678 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1683 * s3c_hsotg_trytx - check to see if anything needs transmitting
1684 * @hsotg: The driver state
1685 * @hs_ep: The driver endpoint to check.
1687 * Check to see if there is a request that has data to send, and if so
1688 * make an attempt to write data into the FIFO.
1690 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1691 struct s3c_hsotg_ep *hs_ep)
1693 struct s3c_hsotg_req *hs_req = hs_ep->req;
1695 if (!hs_ep->dir_in || !hs_req)
1698 if (hs_req->req.actual < hs_req->req.length) {
1699 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1701 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1708 * s3c_hsotg_complete_in - complete IN transfer
1709 * @hsotg: The device state.
1710 * @hs_ep: The endpoint that has just completed.
1712 * An IN transfer has been completed, update the transfer's state and then
1713 * call the relevant completion routines.
1715 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1716 struct s3c_hsotg_ep *hs_ep)
1718 struct s3c_hsotg_req *hs_req = hs_ep->req;
1719 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1720 int size_left, size_done;
1723 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1727 /* Calculate the size of the transfer by checking how much is left
1728 * in the endpoint size register and then working it out from
1729 * the amount we loaded for the transfer.
1731 * We do this even for DMA, as the transfer may have incremented
1732 * past the end of the buffer (DMA transfers are always 32bit
1736 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1738 size_done = hs_ep->size_loaded - size_left;
1739 size_done += hs_ep->last_load;
1741 if (hs_req->req.actual != size_done)
1742 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1743 __func__, hs_req->req.actual, size_done);
1745 hs_req->req.actual = size_done;
1747 /* if we did all of the transfer, and there is more data left
1748 * around, then try restarting the rest of the request */
1750 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1751 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1752 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1754 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1758 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1759 * @hsotg: The driver state
1760 * @idx: The index for the endpoint (0..15)
1761 * @dir_in: Set if this is an IN endpoint
1763 * Process and clear any interrupt pending for an individual endpoint
1765 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1768 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1769 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1770 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1771 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1775 ints = readl(hsotg->regs + epint_reg);
1777 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1778 __func__, idx, dir_in ? "in" : "out", ints);
1780 if (ints & S3C_DxEPINT_XferCompl) {
1782 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1783 __func__, readl(hsotg->regs + epctl_reg),
1784 readl(hsotg->regs + epsiz_reg));
1786 /* we get OutDone from the FIFO, so we only need to look
1787 * at completing IN requests here */
1789 s3c_hsotg_complete_in(hsotg, hs_ep);
1791 if (idx == 0 && !hs_ep->req)
1792 s3c_hsotg_enqueue_setup(hsotg);
1793 } else if (using_dma(hsotg)) {
1794 /* We're using DMA, we need to fire an OutDone here
1795 * as we ignore the RXFIFO. */
1797 s3c_hsotg_handle_outdone(hsotg, idx, false);
1800 clear |= S3C_DxEPINT_XferCompl;
1803 if (ints & S3C_DxEPINT_EPDisbld) {
1804 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1805 clear |= S3C_DxEPINT_EPDisbld;
1808 if (ints & S3C_DxEPINT_AHBErr) {
1809 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1810 clear |= S3C_DxEPINT_AHBErr;
1813 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1814 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1816 if (using_dma(hsotg) && idx == 0) {
1817 /* this is the notification we've received a
1818 * setup packet. In non-DMA mode we'd get this
1819 * from the RXFIFO, instead we need to process
1820 * the setup here. */
1825 s3c_hsotg_handle_outdone(hsotg, 0, true);
1828 clear |= S3C_DxEPINT_Setup;
1831 if (ints & S3C_DxEPINT_Back2BackSetup) {
1832 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1833 clear |= S3C_DxEPINT_Back2BackSetup;
1837 /* not sure if this is important, but we'll clear it anyway
1839 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1840 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1842 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1845 /* this probably means something bad is happening */
1846 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1847 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1849 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1852 /* FIFO has space or is empty (see GAHBCFG) */
1853 if (hsotg->dedicated_fifos &&
1854 ints & S3C_DIEPMSK_TxFIFOEmpty) {
1855 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1857 s3c_hsotg_trytx(hsotg, hs_ep);
1858 clear |= S3C_DIEPMSK_TxFIFOEmpty;
1862 writel(clear, hsotg->regs + epint_reg);
1866 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1867 * @hsotg: The device state.
1869 * Handle updating the device settings after the enumeration phase has
1872 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1874 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1875 int ep0_mps = 0, ep_mps;
1877 /* This should signal the finish of the enumeration phase
1878 * of the USB handshaking, so we should now know what rate
1879 * we connected at. */
1881 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1883 /* note, since we're limited by the size of transfer on EP0, and
1884 * it seems IN transfers must be a even number of packets we do
1885 * not advertise a 64byte MPS on EP0. */
1887 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1888 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1889 case S3C_DSTS_EnumSpd_FS:
1890 case S3C_DSTS_EnumSpd_FS48:
1891 hsotg->gadget.speed = USB_SPEED_FULL;
1892 dev_info(hsotg->dev, "new device is full-speed\n");
1894 ep0_mps = EP0_MPS_LIMIT;
1898 case S3C_DSTS_EnumSpd_HS:
1899 dev_info(hsotg->dev, "new device is high-speed\n");
1900 hsotg->gadget.speed = USB_SPEED_HIGH;
1902 ep0_mps = EP0_MPS_LIMIT;
1906 case S3C_DSTS_EnumSpd_LS:
1907 hsotg->gadget.speed = USB_SPEED_LOW;
1908 dev_info(hsotg->dev, "new device is low-speed\n");
1910 /* note, we don't actually support LS in this driver at the
1911 * moment, and the documentation seems to imply that it isn't
1912 * supported by the PHYs on some of the devices.
1917 /* we should now know the maximum packet size for an
1918 * endpoint, so set the endpoints to a default value. */
1922 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1923 for (i = 1; i < S3C_HSOTG_EPS; i++)
1924 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1927 /* ensure after enumeration our EP0 is active */
1929 s3c_hsotg_enqueue_setup(hsotg);
1931 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1932 readl(hsotg->regs + S3C_DIEPCTL0),
1933 readl(hsotg->regs + S3C_DOEPCTL0));
1937 * kill_all_requests - remove all requests from the endpoint's queue
1938 * @hsotg: The device state.
1939 * @ep: The endpoint the requests may be on.
1940 * @result: The result code to use.
1941 * @force: Force removal of any current requests
1943 * Go through the requests on the given endpoint and mark them
1944 * completed with the given result code.
1946 static void kill_all_requests(struct s3c_hsotg *hsotg,
1947 struct s3c_hsotg_ep *ep,
1948 int result, bool force)
1950 struct s3c_hsotg_req *req, *treq;
1951 unsigned long flags;
1953 spin_lock_irqsave(&ep->lock, flags);
1955 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1956 /* currently, we can't do much about an already
1957 * running request on an in endpoint */
1959 if (ep->req == req && ep->dir_in && !force)
1962 s3c_hsotg_complete_request(hsotg, ep, req,
1966 spin_unlock_irqrestore(&ep->lock, flags);
1969 #define call_gadget(_hs, _entry) \
1970 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1971 (_hs)->driver && (_hs)->driver->_entry) \
1972 (_hs)->driver->_entry(&(_hs)->gadget);
1975 * s3c_hsotg_disconnect_irq - disconnect irq service
1976 * @hsotg: The device state.
1978 * A disconnect IRQ has been received, meaning that the host has
1979 * lost contact with the bus. Remove all current transactions
1980 * and signal the gadget driver that this has happened.
1982 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1986 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1987 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1989 call_gadget(hsotg, disconnect);
1993 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1994 * @hsotg: The device state:
1995 * @periodic: True if this is a periodic FIFO interrupt
1997 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1999 struct s3c_hsotg_ep *ep;
2002 /* look through for any more data to transmit */
2004 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
2005 ep = &hsotg->eps[epno];
2010 if ((periodic && !ep->periodic) ||
2011 (!periodic && ep->periodic))
2014 ret = s3c_hsotg_trytx(hsotg, ep);
2020 static struct s3c_hsotg *our_hsotg;
2022 /* IRQ flags which will trigger a retry around the IRQ loop */
2023 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2024 S3C_GINTSTS_PTxFEmp | \
2028 * s3c_hsotg_irq - handle device interrupt
2029 * @irq: The IRQ number triggered
2030 * @pw: The pw value when registered the handler.
2032 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2034 struct s3c_hsotg *hsotg = pw;
2035 int retry_count = 8;
2040 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2041 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2043 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2044 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2048 if (gintsts & S3C_GINTSTS_OTGInt) {
2049 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2051 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2053 writel(otgint, hsotg->regs + S3C_GOTGINT);
2054 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
2057 if (gintsts & S3C_GINTSTS_DisconnInt) {
2058 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2059 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2061 s3c_hsotg_disconnect_irq(hsotg);
2064 if (gintsts & S3C_GINTSTS_SessReqInt) {
2065 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2066 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2069 if (gintsts & S3C_GINTSTS_EnumDone) {
2070 s3c_hsotg_irq_enumdone(hsotg);
2071 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2074 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2075 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2076 readl(hsotg->regs + S3C_DSTS),
2077 readl(hsotg->regs + S3C_GOTGCTL));
2079 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2082 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2083 u32 daint = readl(hsotg->regs + S3C_DAINT);
2084 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2085 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2088 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2090 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2092 s3c_hsotg_epint(hsotg, ep, 0);
2095 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2097 s3c_hsotg_epint(hsotg, ep, 1);
2100 writel(daint, hsotg->regs + S3C_DAINT);
2101 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2102 hsotg->regs + S3C_GINTSTS);
2105 if (gintsts & S3C_GINTSTS_USBRst) {
2106 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2107 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2108 readl(hsotg->regs + S3C_GNPTXSTS));
2110 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2112 /* it seems after a reset we can end up with a situation
2113 * where the TXFIFO still has data in it... the docs
2114 * suggest resetting all the fifos, so use the init_fifo
2115 * code to relayout and flush the fifos.
2118 s3c_hsotg_init_fifo(hsotg);
2120 s3c_hsotg_enqueue_setup(hsotg);
2122 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2125 /* check both FIFOs */
2127 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2128 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2130 /* Disable the interrupt to stop it happening again
2131 * unless one of these endpoint routines decides that
2132 * it needs re-enabling */
2134 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2135 s3c_hsotg_irq_fifoempty(hsotg, false);
2137 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2140 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2141 dev_dbg(hsotg->dev, "PTxFEmp\n");
2143 /* See note in S3C_GINTSTS_NPTxFEmp */
2145 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2146 s3c_hsotg_irq_fifoempty(hsotg, true);
2148 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2151 if (gintsts & S3C_GINTSTS_RxFLvl) {
2152 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2153 * we need to retry s3c_hsotg_handle_rx if this is still
2156 s3c_hsotg_handle_rx(hsotg);
2157 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2160 if (gintsts & S3C_GINTSTS_ModeMis) {
2161 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2162 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2165 if (gintsts & S3C_GINTSTS_USBSusp) {
2166 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2167 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2169 call_gadget(hsotg, suspend);
2172 if (gintsts & S3C_GINTSTS_WkUpInt) {
2173 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2174 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2176 call_gadget(hsotg, resume);
2179 if (gintsts & S3C_GINTSTS_ErlySusp) {
2180 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2181 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2184 /* these next two seem to crop-up occasionally causing the core
2185 * to shutdown the USB transfer, so try clearing them and logging
2188 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2189 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2191 s3c_hsotg_dump(hsotg);
2193 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2194 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2197 if (gintsts & S3C_GINTSTS_GINNakEff) {
2198 dev_info(hsotg->dev, "GINNakEff triggered\n");
2200 s3c_hsotg_dump(hsotg);
2202 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2203 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2206 /* if we've had fifo events, we should try and go around the
2207 * loop again to see if there's any point in returning yet. */
2209 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2216 * s3c_hsotg_ep_enable - enable the given endpoint
2217 * @ep: The USB endpint to configure
2218 * @desc: The USB endpoint descriptor to configure with.
2220 * This is called from the USB gadget code's usb_ep_enable().
2222 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2223 const struct usb_endpoint_descriptor *desc)
2225 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2226 struct s3c_hsotg *hsotg = hs_ep->parent;
2227 unsigned long flags;
2228 int index = hs_ep->index;
2236 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2237 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2238 desc->wMaxPacketSize, desc->bInterval);
2240 /* not to be called for EP0 */
2241 WARN_ON(index == 0);
2243 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2244 if (dir_in != hs_ep->dir_in) {
2245 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2249 mps = le16_to_cpu(desc->wMaxPacketSize);
2251 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2253 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2254 epctrl = readl(hsotg->regs + epctrl_reg);
2256 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2257 __func__, epctrl, epctrl_reg);
2259 spin_lock_irqsave(&hs_ep->lock, flags);
2261 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2262 epctrl |= S3C_DxEPCTL_MPS(mps);
2264 /* mark the endpoint as active, otherwise the core may ignore
2265 * transactions entirely for this endpoint */
2266 epctrl |= S3C_DxEPCTL_USBActEp;
2268 /* set the NAK status on the endpoint, otherwise we might try and
2269 * do something with data that we've yet got a request to process
2270 * since the RXFIFO will take data for an endpoint even if the
2271 * size register hasn't been set.
2274 epctrl |= S3C_DxEPCTL_SNAK;
2276 /* update the endpoint state */
2277 hs_ep->ep.maxpacket = mps;
2279 /* default, set to non-periodic */
2280 hs_ep->periodic = 0;
2282 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2283 case USB_ENDPOINT_XFER_ISOC:
2284 dev_err(hsotg->dev, "no current ISOC support\n");
2288 case USB_ENDPOINT_XFER_BULK:
2289 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2292 case USB_ENDPOINT_XFER_INT:
2294 /* Allocate our TxFNum by simply using the index
2295 * of the endpoint for the moment. We could do
2296 * something better if the host indicates how
2297 * many FIFOs we are expecting to use. */
2299 hs_ep->periodic = 1;
2300 epctrl |= S3C_DxEPCTL_TxFNum(index);
2303 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2306 case USB_ENDPOINT_XFER_CONTROL:
2307 epctrl |= S3C_DxEPCTL_EPType_Control;
2311 /* if the hardware has dedicated fifos, we must give each IN EP
2312 * a unique tx-fifo even if it is non-periodic.
2314 if (dir_in && hsotg->dedicated_fifos)
2315 epctrl |= S3C_DxEPCTL_TxFNum(index);
2317 /* for non control endpoints, set PID to D0 */
2319 epctrl |= S3C_DxEPCTL_SetD0PID;
2321 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2324 writel(epctrl, hsotg->regs + epctrl_reg);
2325 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2326 __func__, readl(hsotg->regs + epctrl_reg));
2328 /* enable the endpoint interrupt */
2329 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2332 spin_unlock_irqrestore(&hs_ep->lock, flags);
2336 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2338 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2339 struct s3c_hsotg *hsotg = hs_ep->parent;
2340 int dir_in = hs_ep->dir_in;
2341 int index = hs_ep->index;
2342 unsigned long flags;
2346 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2348 if (ep == &hsotg->eps[0].ep) {
2349 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2353 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2355 /* terminate all requests with shutdown */
2356 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2358 spin_lock_irqsave(&hs_ep->lock, flags);
2360 ctrl = readl(hsotg->regs + epctrl_reg);
2361 ctrl &= ~S3C_DxEPCTL_EPEna;
2362 ctrl &= ~S3C_DxEPCTL_USBActEp;
2363 ctrl |= S3C_DxEPCTL_SNAK;
2365 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2366 writel(ctrl, hsotg->regs + epctrl_reg);
2368 /* disable endpoint interrupts */
2369 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2371 spin_unlock_irqrestore(&hs_ep->lock, flags);
2376 * on_list - check request is on the given endpoint
2377 * @ep: The endpoint to check.
2378 * @test: The request to test if it is on the endpoint.
2380 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2382 struct s3c_hsotg_req *req, *treq;
2384 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2392 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2394 struct s3c_hsotg_req *hs_req = our_req(req);
2395 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2396 struct s3c_hsotg *hs = hs_ep->parent;
2397 unsigned long flags;
2399 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2401 if (hs_req == hs_ep->req) {
2402 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2403 return -EINPROGRESS;
2406 spin_lock_irqsave(&hs_ep->lock, flags);
2408 if (!on_list(hs_ep, hs_req)) {
2409 spin_unlock_irqrestore(&hs_ep->lock, flags);
2413 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2414 spin_unlock_irqrestore(&hs_ep->lock, flags);
2419 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2421 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2422 struct s3c_hsotg *hs = hs_ep->parent;
2423 int index = hs_ep->index;
2424 unsigned long irqflags;
2428 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2430 spin_lock_irqsave(&hs_ep->lock, irqflags);
2432 /* write both IN and OUT control registers */
2434 epreg = S3C_DIEPCTL(index);
2435 epctl = readl(hs->regs + epreg);
2438 epctl |= S3C_DxEPCTL_Stall;
2440 epctl &= ~S3C_DxEPCTL_Stall;
2442 writel(epctl, hs->regs + epreg);
2444 epreg = S3C_DOEPCTL(index);
2445 epctl = readl(hs->regs + epreg);
2448 epctl |= S3C_DxEPCTL_Stall;
2450 epctl &= ~S3C_DxEPCTL_Stall;
2452 writel(epctl, hs->regs + epreg);
2454 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2459 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2460 .enable = s3c_hsotg_ep_enable,
2461 .disable = s3c_hsotg_ep_disable,
2462 .alloc_request = s3c_hsotg_ep_alloc_request,
2463 .free_request = s3c_hsotg_ep_free_request,
2464 .queue = s3c_hsotg_ep_queue,
2465 .dequeue = s3c_hsotg_ep_dequeue,
2466 .set_halt = s3c_hsotg_ep_sethalt,
2467 /* note, don't belive we have any call for the fifo routines */
2471 * s3c_hsotg_corereset - issue softreset to the core
2472 * @hsotg: The device state
2474 * Issue a soft reset to the core, and await the core finishing it.
2476 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2481 dev_dbg(hsotg->dev, "resetting core\n");
2483 /* issue soft reset */
2484 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2488 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2489 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2491 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2492 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2499 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2501 if (timeout-- < 0) {
2502 dev_info(hsotg->dev,
2503 "%s: reset failed, GRSTCTL=%08x\n",
2508 if (grstctl & S3C_GRSTCTL_CSftRst)
2511 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2514 break; /* reset done */
2517 dev_dbg(hsotg->dev, "reset successful\n");
2521 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2523 struct s3c_hsotg *hsotg = our_hsotg;
2527 printk(KERN_ERR "%s: called with no device\n", __func__);
2532 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2536 if (driver->speed != USB_SPEED_HIGH &&
2537 driver->speed != USB_SPEED_FULL) {
2538 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2541 if (!driver->bind || !driver->setup) {
2542 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2546 WARN_ON(hsotg->driver);
2548 driver->driver.bus = NULL;
2549 hsotg->driver = driver;
2550 hsotg->gadget.dev.driver = &driver->driver;
2551 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2552 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2554 ret = device_add(&hsotg->gadget.dev);
2556 dev_err(hsotg->dev, "failed to register gadget device\n");
2560 ret = driver->bind(&hsotg->gadget);
2562 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2564 hsotg->gadget.dev.driver = NULL;
2565 hsotg->driver = NULL;
2569 /* we must now enable ep0 ready for host detection and then
2570 * set configuration. */
2572 s3c_hsotg_corereset(hsotg);
2574 /* set the PLL on, remove the HNP/SRP and set the PHY */
2575 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2576 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2578 /* looks like soft-reset changes state of FIFOs */
2579 s3c_hsotg_init_fifo(hsotg);
2581 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2583 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2585 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2586 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2587 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2588 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2589 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2590 S3C_GINTSTS_ErlySusp,
2591 hsotg->regs + S3C_GINTMSK);
2593 if (using_dma(hsotg))
2594 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2595 S3C_GAHBCFG_HBstLen_Incr4,
2596 hsotg->regs + S3C_GAHBCFG);
2598 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2600 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2601 * up being flooded with interrupts if the host is polling the
2602 * endpoint to try and read data. */
2604 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2605 S3C_DIEPMSK_INTknEPMisMsk |
2606 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2607 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2608 hsotg->regs + S3C_DIEPMSK);
2610 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2611 * DMA mode we may need this. */
2612 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2613 S3C_DOEPMSK_EPDisbldMsk |
2614 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2615 S3C_DIEPMSK_TimeOUTMsk) : 0),
2616 hsotg->regs + S3C_DOEPMSK);
2618 writel(0, hsotg->regs + S3C_DAINTMSK);
2620 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2621 readl(hsotg->regs + S3C_DIEPCTL0),
2622 readl(hsotg->regs + S3C_DOEPCTL0));
2624 /* enable in and out endpoint interrupts */
2625 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2627 /* Enable the RXFIFO when in slave mode, as this is how we collect
2628 * the data. In DMA mode, we get events from the FIFO but also
2629 * things we cannot process, so do not use it. */
2630 if (!using_dma(hsotg))
2631 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2633 /* Enable interrupts for EP0 in and out */
2634 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2635 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2637 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2638 udelay(10); /* see openiboot */
2639 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2641 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2643 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2644 writing to the EPCTL register.. */
2646 /* set to read 1 8byte packet */
2647 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2648 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2650 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2651 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2652 S3C_DxEPCTL_USBActEp,
2653 hsotg->regs + S3C_DOEPCTL0);
2655 /* enable, but don't activate EP0in */
2656 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2657 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2659 s3c_hsotg_enqueue_setup(hsotg);
2661 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2662 readl(hsotg->regs + S3C_DIEPCTL0),
2663 readl(hsotg->regs + S3C_DOEPCTL0));
2665 /* clear global NAKs */
2666 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2667 hsotg->regs + S3C_DCTL);
2669 /* must be at-least 3ms to allow bus to see disconnect */
2672 /* remove the soft-disconnect and let's go */
2673 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2675 /* report to the user, and return */
2677 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2681 hsotg->driver = NULL;
2682 hsotg->gadget.dev.driver = NULL;
2685 EXPORT_SYMBOL(usb_gadget_register_driver);
2687 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2689 struct s3c_hsotg *hsotg = our_hsotg;
2695 if (!driver || driver != hsotg->driver || !driver->unbind)
2698 /* all endpoints should be shutdown */
2699 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2700 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2702 call_gadget(hsotg, disconnect);
2704 driver->unbind(&hsotg->gadget);
2705 hsotg->driver = NULL;
2706 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2708 device_del(&hsotg->gadget.dev);
2710 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2711 driver->driver.name);
2715 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2717 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2719 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2722 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2723 .get_frame = s3c_hsotg_gadget_getframe,
2727 * s3c_hsotg_initep - initialise a single endpoint
2728 * @hsotg: The device state.
2729 * @hs_ep: The endpoint to be initialised.
2730 * @epnum: The endpoint number
2732 * Initialise the given endpoint (as part of the probe and device state
2733 * creation) to give to the gadget driver. Setup the endpoint name, any
2734 * direction information and other state that may be required.
2736 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2737 struct s3c_hsotg_ep *hs_ep,
2745 else if ((epnum % 2) == 0) {
2752 hs_ep->index = epnum;
2754 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2756 INIT_LIST_HEAD(&hs_ep->queue);
2757 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2759 spin_lock_init(&hs_ep->lock);
2761 /* add to the list of endpoints known by the gadget driver */
2763 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2765 hs_ep->parent = hsotg;
2766 hs_ep->ep.name = hs_ep->name;
2767 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2768 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2770 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2771 * an OUT endpoint, we may as well do this if in future the
2772 * code is changed to make each endpoint's direction changeable.
2775 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2776 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2778 /* if we're using dma, we need to set the next-endpoint pointer
2779 * to be something valid.
2782 if (using_dma(hsotg)) {
2783 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2784 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2785 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2790 * s3c_hsotg_otgreset - reset the OtG phy block
2791 * @hsotg: The host state.
2793 * Power up the phy, set the basic configuration and start the PHY.
2795 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2799 writel(0, S3C_PHYPWR);
2802 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2804 writel(osc | 0x10, S3C_PHYCLK);
2806 /* issue a full set of resets to the otg and core */
2808 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2809 udelay(20); /* at-least 10uS */
2810 writel(0, S3C_RSTCON);
2814 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2818 /* unmask subset of endpoint interrupts */
2820 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2821 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2822 hsotg->regs + S3C_DIEPMSK);
2824 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2825 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2826 hsotg->regs + S3C_DOEPMSK);
2828 writel(0, hsotg->regs + S3C_DAINTMSK);
2830 /* Be in disconnected state until gadget is registered */
2831 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2834 /* post global nak until we're ready */
2835 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2836 hsotg->regs + S3C_DCTL);
2841 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2842 readl(hsotg->regs + S3C_GRXFSIZ),
2843 readl(hsotg->regs + S3C_GNPTXFSIZ));
2845 s3c_hsotg_init_fifo(hsotg);
2847 /* set the PLL on, remove the HNP/SRP and set the PHY */
2848 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2849 hsotg->regs + S3C_GUSBCFG);
2851 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2852 hsotg->regs + S3C_GAHBCFG);
2854 /* check hardware configuration */
2856 cfg4 = readl(hsotg->regs + 0x50);
2857 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2859 dev_info(hsotg->dev, "%s fifos\n",
2860 hsotg->dedicated_fifos ? "dedicated" : "shared");
2863 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2865 struct device *dev = hsotg->dev;
2866 void __iomem *regs = hsotg->regs;
2870 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2871 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2872 readl(regs + S3C_DIEPMSK));
2874 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2875 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2877 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2878 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2880 /* show periodic fifo settings */
2882 for (idx = 1; idx <= 15; idx++) {
2883 val = readl(regs + S3C_DPTXFSIZn(idx));
2884 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2885 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2886 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2889 for (idx = 0; idx < 15; idx++) {
2891 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2892 readl(regs + S3C_DIEPCTL(idx)),
2893 readl(regs + S3C_DIEPTSIZ(idx)),
2894 readl(regs + S3C_DIEPDMA(idx)));
2896 val = readl(regs + S3C_DOEPCTL(idx));
2898 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2899 idx, readl(regs + S3C_DOEPCTL(idx)),
2900 readl(regs + S3C_DOEPTSIZ(idx)),
2901 readl(regs + S3C_DOEPDMA(idx)));
2905 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2906 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2911 * state_show - debugfs: show overall driver and device state.
2912 * @seq: The seq file to write to.
2913 * @v: Unused parameter.
2915 * This debugfs entry shows the overall state of the hardware and
2916 * some general information about each of the endpoints available
2919 static int state_show(struct seq_file *seq, void *v)
2921 struct s3c_hsotg *hsotg = seq->private;
2922 void __iomem *regs = hsotg->regs;
2925 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2926 readl(regs + S3C_DCFG),
2927 readl(regs + S3C_DCTL),
2928 readl(regs + S3C_DSTS));
2930 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2931 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2933 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2934 readl(regs + S3C_GINTMSK),
2935 readl(regs + S3C_GINTSTS));
2937 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2938 readl(regs + S3C_DAINTMSK),
2939 readl(regs + S3C_DAINT));
2941 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2942 readl(regs + S3C_GNPTXSTS),
2943 readl(regs + S3C_GRXSTSR));
2945 seq_printf(seq, "\nEndpoint status:\n");
2947 for (idx = 0; idx < 15; idx++) {
2950 in = readl(regs + S3C_DIEPCTL(idx));
2951 out = readl(regs + S3C_DOEPCTL(idx));
2953 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2956 in = readl(regs + S3C_DIEPTSIZ(idx));
2957 out = readl(regs + S3C_DOEPTSIZ(idx));
2959 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2962 seq_printf(seq, "\n");
2968 static int state_open(struct inode *inode, struct file *file)
2970 return single_open(file, state_show, inode->i_private);
2973 static const struct file_operations state_fops = {
2974 .owner = THIS_MODULE,
2977 .llseek = seq_lseek,
2978 .release = single_release,
2982 * fifo_show - debugfs: show the fifo information
2983 * @seq: The seq_file to write data to.
2984 * @v: Unused parameter.
2986 * Show the FIFO information for the overall fifo and all the
2987 * periodic transmission FIFOs.
2989 static int fifo_show(struct seq_file *seq, void *v)
2991 struct s3c_hsotg *hsotg = seq->private;
2992 void __iomem *regs = hsotg->regs;
2996 seq_printf(seq, "Non-periodic FIFOs:\n");
2997 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2999 val = readl(regs + S3C_GNPTXFSIZ);
3000 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3001 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
3002 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
3004 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3006 for (idx = 1; idx <= 15; idx++) {
3007 val = readl(regs + S3C_DPTXFSIZn(idx));
3009 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3010 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
3011 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
3017 static int fifo_open(struct inode *inode, struct file *file)
3019 return single_open(file, fifo_show, inode->i_private);
3022 static const struct file_operations fifo_fops = {
3023 .owner = THIS_MODULE,
3026 .llseek = seq_lseek,
3027 .release = single_release,
3031 static const char *decode_direction(int is_in)
3033 return is_in ? "in" : "out";
3037 * ep_show - debugfs: show the state of an endpoint.
3038 * @seq: The seq_file to write data to.
3039 * @v: Unused parameter.
3041 * This debugfs entry shows the state of the given endpoint (one is
3042 * registered for each available).
3044 static int ep_show(struct seq_file *seq, void *v)
3046 struct s3c_hsotg_ep *ep = seq->private;
3047 struct s3c_hsotg *hsotg = ep->parent;
3048 struct s3c_hsotg_req *req;
3049 void __iomem *regs = hsotg->regs;
3050 int index = ep->index;
3051 int show_limit = 15;
3052 unsigned long flags;
3054 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3055 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3057 /* first show the register state */
3059 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3060 readl(regs + S3C_DIEPCTL(index)),
3061 readl(regs + S3C_DOEPCTL(index)));
3063 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3064 readl(regs + S3C_DIEPDMA(index)),
3065 readl(regs + S3C_DOEPDMA(index)));
3067 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3068 readl(regs + S3C_DIEPINT(index)),
3069 readl(regs + S3C_DOEPINT(index)));
3071 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3072 readl(regs + S3C_DIEPTSIZ(index)),
3073 readl(regs + S3C_DOEPTSIZ(index)));
3075 seq_printf(seq, "\n");
3076 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3077 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3079 seq_printf(seq, "request list (%p,%p):\n",
3080 ep->queue.next, ep->queue.prev);
3082 spin_lock_irqsave(&ep->lock, flags);
3084 list_for_each_entry(req, &ep->queue, queue) {
3085 if (--show_limit < 0) {
3086 seq_printf(seq, "not showing more requests...\n");
3090 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3091 req == ep->req ? '*' : ' ',
3092 req, req->req.length, req->req.buf);
3093 seq_printf(seq, "%d done, res %d\n",
3094 req->req.actual, req->req.status);
3097 spin_unlock_irqrestore(&ep->lock, flags);
3102 static int ep_open(struct inode *inode, struct file *file)
3104 return single_open(file, ep_show, inode->i_private);
3107 static const struct file_operations ep_fops = {
3108 .owner = THIS_MODULE,
3111 .llseek = seq_lseek,
3112 .release = single_release,
3116 * s3c_hsotg_create_debug - create debugfs directory and files
3117 * @hsotg: The driver state
3119 * Create the debugfs files to allow the user to get information
3120 * about the state of the system. The directory name is created
3121 * with the same name as the device itself, in case we end up
3122 * with multiple blocks in future systems.
3124 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3126 struct dentry *root;
3129 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3130 hsotg->debug_root = root;
3132 dev_err(hsotg->dev, "cannot create debug root\n");
3136 /* create general state file */
3138 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3139 hsotg, &state_fops);
3141 if (IS_ERR(hsotg->debug_file))
3142 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3144 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3147 if (IS_ERR(hsotg->debug_fifo))
3148 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3150 /* create one file for each endpoint */
3152 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3153 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3155 ep->debugfs = debugfs_create_file(ep->name, 0444,
3156 root, ep, &ep_fops);
3158 if (IS_ERR(ep->debugfs))
3159 dev_err(hsotg->dev, "failed to create %s debug file\n",
3165 * s3c_hsotg_delete_debug - cleanup debugfs entries
3166 * @hsotg: The driver state
3168 * Cleanup (remove) the debugfs files for use on module exit.
3170 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3174 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3175 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3176 debugfs_remove(ep->debugfs);
3179 debugfs_remove(hsotg->debug_file);
3180 debugfs_remove(hsotg->debug_fifo);
3181 debugfs_remove(hsotg->debug_root);
3185 * s3c_hsotg_gate - set the hardware gate for the block
3186 * @pdev: The device we bound to
3189 * Set the hardware gate setting into the block. If we end up on
3190 * something other than an S3C64XX, then we might need to change this
3191 * to using a platform data callback, or some other mechanism.
3193 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3195 unsigned long flags;
3198 local_irq_save(flags);
3200 others = __raw_readl(S3C64XX_OTHERS);
3202 others |= S3C64XX_OTHERS_USBMASK;
3204 others &= ~S3C64XX_OTHERS_USBMASK;
3205 __raw_writel(others, S3C64XX_OTHERS);
3207 local_irq_restore(flags);
3210 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3212 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3214 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3215 struct device *dev = &pdev->dev;
3216 struct s3c_hsotg *hsotg;
3217 struct resource *res;
3222 plat = &s3c_hsotg_default_pdata;
3224 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3225 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3228 dev_err(dev, "cannot get memory\n");
3235 platform_set_drvdata(pdev, hsotg);
3237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3239 dev_err(dev, "cannot find register resource 0\n");
3244 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3246 if (!hsotg->regs_res) {
3247 dev_err(dev, "cannot reserve registers\n");
3252 hsotg->regs = ioremap(res->start, resource_size(res));
3254 dev_err(dev, "cannot map registers\n");
3259 ret = platform_get_irq(pdev, 0);
3261 dev_err(dev, "cannot find IRQ\n");
3267 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3269 dev_err(dev, "cannot claim IRQ\n");
3273 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3275 device_initialize(&hsotg->gadget.dev);
3277 dev_set_name(&hsotg->gadget.dev, "gadget");
3279 hsotg->gadget.is_dualspeed = 1;
3280 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3281 hsotg->gadget.name = dev_name(dev);
3283 hsotg->gadget.dev.parent = dev;
3284 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3286 /* setup endpoint information */
3288 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3289 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3291 /* allocate EP0 request */
3293 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3295 if (!hsotg->ctrl_req) {
3296 dev_err(dev, "failed to allocate ctrl req\n");
3300 /* reset the system */
3302 s3c_hsotg_gate(pdev, true);
3304 s3c_hsotg_otgreset(hsotg);
3305 s3c_hsotg_corereset(hsotg);
3306 s3c_hsotg_init(hsotg);
3308 /* initialise the endpoints now the core has been initialised */
3309 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3310 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3312 s3c_hsotg_create_debug(hsotg);
3314 s3c_hsotg_dump(hsotg);
3320 iounmap(hsotg->regs);
3323 release_resource(hsotg->regs_res);
3324 kfree(hsotg->regs_res);
3331 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3333 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3335 s3c_hsotg_delete_debug(hsotg);
3337 usb_gadget_unregister_driver(hsotg->driver);
3339 free_irq(hsotg->irq, hsotg);
3340 iounmap(hsotg->regs);
3342 release_resource(hsotg->regs_res);
3343 kfree(hsotg->regs_res);
3345 s3c_hsotg_gate(pdev, false);
3352 #define s3c_hsotg_suspend NULL
3353 #define s3c_hsotg_resume NULL
3356 static struct platform_driver s3c_hsotg_driver = {
3358 .name = "s3c-hsotg",
3359 .owner = THIS_MODULE,
3361 .probe = s3c_hsotg_probe,
3362 .remove = __devexit_p(s3c_hsotg_remove),
3363 .suspend = s3c_hsotg_suspend,
3364 .resume = s3c_hsotg_resume,
3367 static int __init s3c_hsotg_modinit(void)
3369 return platform_driver_register(&s3c_hsotg_driver);
3372 static void __exit s3c_hsotg_modexit(void)
3374 platform_driver_unregister(&s3c_hsotg_driver);
3377 module_init(s3c_hsotg_modinit);
3378 module_exit(s3c_hsotg_modexit);
3380 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3381 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3382 MODULE_LICENSE("GPL");
3383 MODULE_ALIAS("platform:s3c-hsotg");