1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/delay.h>
25 #include <linux/slab.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
32 #include <plat/regs-usb-hsotg-phy.h>
33 #include <plat/regs-usb-hsotg.h>
34 #include <mach/regs-sys.h>
35 #include <plat/udc-hs.h>
37 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
41 * Unfortunately there seems to be a limit of the amount of data that can
42 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
43 * packets (which practially means 1 packet and 63 bytes of data) when the
46 * This means if we are wanting to move >127 bytes of data, we need to
47 * split the transactions up, but just doing one packet at a time does
48 * not work (this may be an implicit DATA0 PID on first packet of the
49 * transaction) and doing 2 packets is outside the controller's limits.
51 * If we try to lower the MPS size for EP0, then no transfers work properly
52 * for EP0, and the system will fail basic enumeration. As no cause for this
53 * has currently been found, we cannot support any large IN transfers for
56 #define EP0_MPS_LIMIT 64
62 * struct s3c_hsotg_ep - driver endpoint definition.
63 * @ep: The gadget layer representation of the endpoint.
64 * @name: The driver generated name for the endpoint.
65 * @queue: Queue of requests for this endpoint.
66 * @parent: Reference back to the parent device structure.
67 * @req: The current request that the endpoint is processing. This is
68 * used to indicate an request has been loaded onto the endpoint
69 * and has yet to be completed (maybe due to data move, or simply
70 * awaiting an ack from the core all the data has been completed).
71 * @debugfs: File entry for debugfs file for this endpoint.
72 * @lock: State lock to protect contents of endpoint.
73 * @dir_in: Set to true if this endpoint is of the IN direction, which
74 * means that it is sending data to the Host.
75 * @index: The index for the endpoint registers.
76 * @name: The name array passed to the USB core.
77 * @halted: Set if the endpoint has been halted.
78 * @periodic: Set if this is a periodic ep, such as Interrupt
79 * @sent_zlp: Set if we've sent a zero-length packet.
80 * @total_data: The total number of data bytes done.
81 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
82 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
83 * @last_load: The offset of data for the last start of request.
84 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
86 * This is the driver's state for each registered enpoint, allowing it
87 * to keep track of transactions that need doing. Each endpoint has a
88 * lock to protect the state, to try and avoid using an overall lock
89 * for the host controller as much as possible.
91 * For periodic IN endpoints, we have fifo_size and fifo_load to try
92 * and keep track of the amount of data in the periodic FIFO for each
93 * of these as we don't have a status register that tells us how much
98 struct list_head queue;
99 struct s3c_hsotg *parent;
100 struct s3c_hsotg_req *req;
101 struct dentry *debugfs;
105 unsigned long total_data;
106 unsigned int size_loaded;
107 unsigned int last_load;
108 unsigned int fifo_load;
109 unsigned short fifo_size;
111 unsigned char dir_in;
114 unsigned int halted:1;
115 unsigned int periodic:1;
116 unsigned int sent_zlp:1;
121 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
124 * struct s3c_hsotg - driver state.
125 * @dev: The parent device supplied to the probe function
126 * @driver: USB gadget driver
127 * @plat: The platform specific configuration data.
128 * @regs: The memory area mapped for accessing registers.
129 * @regs_res: The resource that was allocated when claiming register space.
130 * @irq: The IRQ number we are using
131 * @debug_root: root directrory for debugfs.
132 * @debug_file: main status file for debugfs.
133 * @debug_fifo: FIFO status file for debugfs.
134 * @ep0_reply: Request used for ep0 reply.
135 * @ep0_buff: Buffer for EP0 reply data, if needed.
136 * @ctrl_buff: Buffer for EP0 control requests.
137 * @ctrl_req: Request for EP0 control packets.
138 * @eps: The endpoints being supplied to the gadget framework
142 struct usb_gadget_driver *driver;
143 struct s3c_hsotg_plat *plat;
146 struct resource *regs_res;
149 struct dentry *debug_root;
150 struct dentry *debug_file;
151 struct dentry *debug_fifo;
153 struct usb_request *ep0_reply;
154 struct usb_request *ctrl_req;
158 struct usb_gadget gadget;
159 struct s3c_hsotg_ep eps[];
163 * struct s3c_hsotg_req - data transfer request
164 * @req: The USB gadget request
165 * @queue: The list of requests for the endpoint this is queued for.
166 * @in_progress: Has already had size/packets written to core
167 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
169 struct s3c_hsotg_req {
170 struct usb_request req;
171 struct list_head queue;
172 unsigned char in_progress;
173 unsigned char mapped;
176 /* conversion functions */
177 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
179 return container_of(req, struct s3c_hsotg_req, req);
182 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
184 return container_of(ep, struct s3c_hsotg_ep, ep);
187 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
189 return container_of(gadget, struct s3c_hsotg, gadget);
192 static inline void __orr32(void __iomem *ptr, u32 val)
194 writel(readl(ptr) | val, ptr);
197 static inline void __bic32(void __iomem *ptr, u32 val)
199 writel(readl(ptr) & ~val, ptr);
202 /* forward decleration of functions */
203 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
206 * using_dma - return the DMA status of the driver.
207 * @hsotg: The driver state.
209 * Return true if we're using DMA.
211 * Currently, we have the DMA support code worked into everywhere
212 * that needs it, but the AMBA DMA implementation in the hardware can
213 * only DMA from 32bit aligned addresses. This means that gadgets such
214 * as the CDC Ethernet cannot work as they often pass packets which are
217 * Unfortunately the choice to use DMA or not is global to the controller
218 * and seems to be only settable when the controller is being put through
219 * a core reset. This means we either need to fix the gadgets to take
220 * account of DMA alignment, or add bounce buffers (yuerk).
222 * Until this issue is sorted out, we always return 'false'.
224 static inline bool using_dma(struct s3c_hsotg *hsotg)
226 return false; /* support is not complete */
230 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
231 * @hsotg: The device state
232 * @ints: A bitmask of the interrupts to enable
234 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
236 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
239 new_gsintmsk = gsintmsk | ints;
241 if (new_gsintmsk != gsintmsk) {
242 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
243 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
248 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
249 * @hsotg: The device state
250 * @ints: A bitmask of the interrupts to enable
252 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
254 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
257 new_gsintmsk = gsintmsk & ~ints;
259 if (new_gsintmsk != gsintmsk)
260 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
264 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
265 * @hsotg: The device state
266 * @ep: The endpoint index
267 * @dir_in: True if direction is in.
268 * @en: The enable value, true to enable
270 * Set or clear the mask for an individual endpoint's interrupt
273 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
274 unsigned int ep, unsigned int dir_in,
284 local_irq_save(flags);
285 daint = readl(hsotg->regs + S3C_DAINTMSK);
290 writel(daint, hsotg->regs + S3C_DAINTMSK);
291 local_irq_restore(flags);
295 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
296 * @hsotg: The device instance.
298 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
305 /* the ryu 2.6.24 release ahs
306 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
307 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
308 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
309 hsotg->regs + S3C_GNPTXFSIZ);
312 /* set FIFO sizes to 2048/0x1C0 */
314 writel(2048, hsotg->regs + S3C_GRXFSIZ);
315 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
316 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
317 hsotg->regs + S3C_GNPTXFSIZ);
319 /* arange all the rest of the TX FIFOs, as some versions of this
320 * block have overlapping default addresses. This also ensures
321 * that if the settings have been changed, then they are set to
324 /* start at the end of the GNPTXFSIZ, rounded up */
328 /* currently we allocate TX FIFOs for all possible endpoints,
329 * and assume that they are all the same size. */
331 for (ep = 0; ep <= 15; ep++) {
333 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
336 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
341 * @ep: USB endpoint to allocate request for.
342 * @flags: Allocation flags
344 * Allocate a new USB request structure appropriate for the specified endpoint
346 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
349 struct s3c_hsotg_req *req;
351 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
355 INIT_LIST_HEAD(&req->queue);
357 req->req.dma = DMA_ADDR_INVALID;
362 * is_ep_periodic - return true if the endpoint is in periodic mode.
363 * @hs_ep: The endpoint to query.
365 * Returns true if the endpoint is in periodic mode, meaning it is being
366 * used for an Interrupt or ISO transfer.
368 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
370 return hs_ep->periodic;
374 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
375 * @hsotg: The device state.
376 * @hs_ep: The endpoint for the request
377 * @hs_req: The request being processed.
379 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
380 * of a request to ensure the buffer is ready for access by the caller.
382 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
383 struct s3c_hsotg_ep *hs_ep,
384 struct s3c_hsotg_req *hs_req)
386 struct usb_request *req = &hs_req->req;
387 enum dma_data_direction dir;
389 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
391 /* ignore this if we're not moving any data */
392 if (hs_req->req.length == 0)
395 if (hs_req->mapped) {
396 /* we mapped this, so unmap and remove the dma */
398 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
400 req->dma = DMA_ADDR_INVALID;
403 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
408 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
409 * @hsotg: The controller state.
410 * @hs_ep: The endpoint we're going to write for.
411 * @hs_req: The request to write data for.
413 * This is called when the TxFIFO has some space in it to hold a new
414 * transmission and we have something to give it. The actual setup of
415 * the data size is done elsewhere, so all we have to do is to actually
418 * The return value is zero if there is more space (or nothing was done)
419 * otherwise -ENOSPC is returned if the FIFO space was used up.
421 * This routine is only needed for PIO
423 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
424 struct s3c_hsotg_ep *hs_ep,
425 struct s3c_hsotg_req *hs_req)
427 bool periodic = is_ep_periodic(hs_ep);
428 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
429 int buf_pos = hs_req->req.actual;
430 int to_write = hs_ep->size_loaded;
435 to_write -= (buf_pos - hs_ep->last_load);
437 /* if there's nothing to write, get out early */
442 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
446 /* work out how much data was loaded so we can calculate
447 * how much data is left in the fifo. */
449 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
451 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
453 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
455 /* how much of the data has moved */
456 size_done = hs_ep->size_loaded - size_left;
458 /* how much data is left in the fifo */
459 can_write = hs_ep->fifo_load - size_done;
460 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
461 __func__, can_write);
463 can_write = hs_ep->fifo_size - can_write;
464 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
465 __func__, can_write);
467 if (can_write <= 0) {
468 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
472 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
474 "%s: no queue slots available (0x%08x)\n",
477 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
481 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
484 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
485 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
487 /* limit to 512 bytes of data, it seems at least on the non-periodic
488 * FIFO, requests of >512 cause the endpoint to get stuck with a
489 * fragment of the end of the transfer in it.
494 /* see if we can write data */
496 if (to_write > can_write) {
497 to_write = can_write;
498 pkt_round = to_write % hs_ep->ep.maxpacket;
500 /* Not sure, but we probably shouldn't be writing partial
501 * packets into the FIFO, so round the write down to an
502 * exact number of packets.
504 * Note, we do not currently check to see if we can ever
505 * write a full packet or not to the FIFO.
509 to_write -= pkt_round;
511 /* enable correct FIFO interrupt to alert us when there
512 * is more room left. */
514 s3c_hsotg_en_gsint(hsotg,
515 periodic ? S3C_GINTSTS_PTxFEmp :
516 S3C_GINTSTS_NPTxFEmp);
519 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
520 to_write, hs_req->req.length, can_write, buf_pos);
525 hs_req->req.actual = buf_pos + to_write;
526 hs_ep->total_data += to_write;
529 hs_ep->fifo_load += to_write;
531 to_write = DIV_ROUND_UP(to_write, 4);
532 data = hs_req->req.buf + buf_pos;
534 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
536 return (to_write >= can_write) ? -ENOSPC : 0;
540 * get_ep_limit - get the maximum data legnth for this endpoint
541 * @hs_ep: The endpoint
543 * Return the maximum data that can be queued in one go on a given endpoint
544 * so that transfers that are too long can be split.
546 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
548 int index = hs_ep->index;
553 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
554 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
557 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
559 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
566 /* we made the constant loading easier above by using +1 */
570 /* constrain by packet count if maxpkts*pktsize is greater
571 * than the length register size. */
573 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
574 maxsize = maxpkt * hs_ep->ep.maxpacket;
580 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
581 * @hsotg: The controller state.
582 * @hs_ep: The endpoint to process a request for
583 * @hs_req: The request to start.
584 * @continuing: True if we are doing more for the current request.
586 * Start the given request running by setting the endpoint registers
587 * appropriately, and writing any data to the FIFOs.
589 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
590 struct s3c_hsotg_ep *hs_ep,
591 struct s3c_hsotg_req *hs_req,
594 struct usb_request *ureq = &hs_req->req;
595 int index = hs_ep->index;
596 int dir_in = hs_ep->dir_in;
606 if (hs_ep->req && !continuing) {
607 dev_err(hsotg->dev, "%s: active request\n", __func__);
610 } else if (hs_ep->req != hs_req && continuing) {
612 "%s: continue different req\n", __func__);
618 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
619 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
621 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
622 __func__, readl(hsotg->regs + epctrl_reg), index,
623 hs_ep->dir_in ? "in" : "out");
625 length = ureq->length - ureq->actual;
629 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
630 ureq->buf, length, ureq->dma,
631 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
633 maxreq = get_ep_limit(hs_ep);
634 if (length > maxreq) {
635 int round = maxreq % hs_ep->ep.maxpacket;
637 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
638 __func__, length, maxreq, round);
640 /* round down to multiple of packets */
648 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
650 packets = 1; /* send one packet if length is zero. */
652 if (dir_in && index != 0)
653 epsize = S3C_DxEPTSIZ_MC(1);
657 if (index != 0 && ureq->zero) {
658 /* test for the packets being exactly right for the
661 if (length == (packets * hs_ep->ep.maxpacket))
665 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
666 epsize |= S3C_DxEPTSIZ_XferSize(length);
668 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
669 __func__, packets, length, ureq->length, epsize, epsize_reg);
671 /* store the request as the current one we're doing */
674 /* write size / packets */
675 writel(epsize, hsotg->regs + epsize_reg);
677 ctrl = readl(hsotg->regs + epctrl_reg);
679 if (ctrl & S3C_DxEPCTL_Stall) {
680 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
682 /* not sure what we can do here, if it is EP0 then we should
683 * get this cleared once the endpoint has transmitted the
684 * STALL packet, otherwise it needs to be cleared by the
689 if (using_dma(hsotg)) {
690 unsigned int dma_reg;
692 /* write DMA address to control register, buffer already
693 * synced by s3c_hsotg_ep_queue(). */
695 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
696 writel(ureq->dma, hsotg->regs + dma_reg);
698 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
699 __func__, ureq->dma, dma_reg);
702 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
703 ctrl |= S3C_DxEPCTL_USBActEp;
704 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
706 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
707 writel(ctrl, hsotg->regs + epctrl_reg);
709 /* set these, it seems that DMA support increments past the end
710 * of the packet buffer so we need to calculate the length from
711 * this information. */
712 hs_ep->size_loaded = length;
713 hs_ep->last_load = ureq->actual;
715 if (dir_in && !using_dma(hsotg)) {
716 /* set these anyway, we may need them for non-periodic in */
717 hs_ep->fifo_load = 0;
719 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
722 /* clear the INTknTXFEmpMsk when we start request, more as a aide
723 * to debugging to see what is going on. */
725 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
726 hsotg->regs + S3C_DIEPINT(index));
728 /* Note, trying to clear the NAK here causes problems with transmit
729 * on the S3C6400 ending up with the TXFIFO becomming full. */
731 /* check ep is enabled */
732 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
734 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
735 index, readl(hsotg->regs + epctrl_reg));
737 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
738 __func__, readl(hsotg->regs + epctrl_reg));
742 * s3c_hsotg_map_dma - map the DMA memory being used for the request
743 * @hsotg: The device state.
744 * @hs_ep: The endpoint the request is on.
745 * @req: The request being processed.
747 * We've been asked to queue a request, so ensure that the memory buffer
748 * is correctly setup for DMA. If we've been passed an extant DMA address
749 * then ensure the buffer has been synced to memory. If our buffer has no
750 * DMA memory, then we map the memory and mark our request to allow us to
751 * cleanup on completion.
753 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
754 struct s3c_hsotg_ep *hs_ep,
755 struct usb_request *req)
757 enum dma_data_direction dir;
758 struct s3c_hsotg_req *hs_req = our_req(req);
760 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
762 /* if the length is zero, ignore the DMA data */
763 if (hs_req->req.length == 0)
766 if (req->dma == DMA_ADDR_INVALID) {
769 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
771 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
775 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
778 dma_unmap_single(hsotg->dev, dma, req->length, dir);
785 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
792 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
793 __func__, req->buf, req->length);
798 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
801 struct s3c_hsotg_req *hs_req = our_req(req);
802 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
803 struct s3c_hsotg *hs = hs_ep->parent;
804 unsigned long irqflags;
807 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
808 ep->name, req, req->length, req->buf, req->no_interrupt,
809 req->zero, req->short_not_ok);
811 /* initialise status of the request */
812 INIT_LIST_HEAD(&hs_req->queue);
814 req->status = -EINPROGRESS;
816 /* if we're using DMA, sync the buffers as necessary */
818 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
823 spin_lock_irqsave(&hs_ep->lock, irqflags);
825 first = list_empty(&hs_ep->queue);
826 list_add_tail(&hs_req->queue, &hs_ep->queue);
829 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
831 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
836 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
839 struct s3c_hsotg_req *hs_req = our_req(req);
845 * s3c_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
852 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
855 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
856 struct s3c_hsotg *hsotg = hs_ep->parent;
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
860 s3c_hsotg_ep_free_request(ep, req);
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
871 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
874 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
881 if (idx > S3C_HSOTG_EPS)
884 if (idx && ep->dir_in != dir)
891 * s3c_hsotg_send_reply - send reply to control request
892 * @hsotg: The device state
894 * @buff: Buffer for request
895 * @length: Length of reply.
897 * Create a request and queue it on the given endpoint. This is useful as
898 * an internal method of sending replies to certain control requests, etc.
900 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
901 struct s3c_hsotg_ep *ep,
905 struct usb_request *req;
908 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
910 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
911 hsotg->ep0_reply = req;
913 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
917 req->buf = hsotg->ep0_buff;
918 req->length = length;
919 req->zero = 1; /* always do zero-length final transfer */
920 req->complete = s3c_hsotg_complete_oursetup;
923 memcpy(req->buf, buff, length);
927 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
929 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
937 * s3c_hsotg_process_req_status - process request GET_STATUS
938 * @hsotg: The device state
939 * @ctrl: USB control request
941 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
942 struct usb_ctrlrequest *ctrl)
944 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
945 struct s3c_hsotg_ep *ep;
949 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
952 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
956 switch (ctrl->bRequestType & USB_RECIP_MASK) {
957 case USB_RECIP_DEVICE:
958 reply = cpu_to_le16(0); /* bit 0 => self powered,
959 * bit 1 => remote wakeup */
962 case USB_RECIP_INTERFACE:
963 /* currently, the data result should be zero */
964 reply = cpu_to_le16(0);
967 case USB_RECIP_ENDPOINT:
968 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
972 reply = cpu_to_le16(ep->halted ? 1 : 0);
979 if (le16_to_cpu(ctrl->wLength) != 2)
982 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
984 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
991 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
994 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
995 * @hsotg: The device state
996 * @ctrl: USB control request
998 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
999 struct usb_ctrlrequest *ctrl)
1001 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1002 struct s3c_hsotg_ep *ep;
1004 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1005 __func__, set ? "SET" : "CLEAR");
1007 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1008 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1010 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1011 __func__, le16_to_cpu(ctrl->wIndex));
1015 switch (le16_to_cpu(ctrl->wValue)) {
1016 case USB_ENDPOINT_HALT:
1017 s3c_hsotg_ep_sethalt(&ep->ep, set);
1024 return -ENOENT; /* currently only deal with endpoint */
1030 * s3c_hsotg_process_control - process a control request
1031 * @hsotg: The device state
1032 * @ctrl: The control request received
1034 * The controller has received the SETUP phase of a control request, and
1035 * needs to work out what to do next (and whether to pass it on to the
1038 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1039 struct usb_ctrlrequest *ctrl)
1041 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1047 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1048 ctrl->bRequest, ctrl->bRequestType,
1049 ctrl->wValue, ctrl->wLength);
1051 /* record the direction of the request, for later use when enquing
1052 * packets onto EP0. */
1054 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1055 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1057 /* if we've no data with this request, then the last part of the
1058 * transaction is going to implicitly be IN. */
1059 if (ctrl->wLength == 0)
1062 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1063 switch (ctrl->bRequest) {
1064 case USB_REQ_SET_ADDRESS:
1065 dcfg = readl(hsotg->regs + S3C_DCFG);
1066 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1067 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1068 writel(dcfg, hsotg->regs + S3C_DCFG);
1070 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1072 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1075 case USB_REQ_GET_STATUS:
1076 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1079 case USB_REQ_CLEAR_FEATURE:
1080 case USB_REQ_SET_FEATURE:
1081 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1086 /* as a fallback, try delivering it to the driver to deal with */
1088 if (ret == 0 && hsotg->driver) {
1089 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1091 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1096 /* need to generate zlp in reply or take data */
1097 /* todo - deal with any data we might be sent? */
1098 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1102 /* the request is either unhandlable, or is not formatted correctly
1103 * so respond with a STALL for the status stage to indicate failure.
1110 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1111 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1113 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1114 * taken effect, so no need to clear later. */
1116 ctrl = readl(hsotg->regs + reg);
1117 ctrl |= S3C_DxEPCTL_Stall;
1118 ctrl |= S3C_DxEPCTL_CNAK;
1119 writel(ctrl, hsotg->regs + reg);
1122 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1123 ctrl, reg, readl(hsotg->regs + reg));
1125 /* don't belive we need to anything more to get the EP
1126 * to reply with a STALL packet */
1130 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1133 * s3c_hsotg_complete_setup - completion of a setup transfer
1134 * @ep: The endpoint the request was on.
1135 * @req: The request completed.
1137 * Called on completion of any requests the driver itself submitted for
1140 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1141 struct usb_request *req)
1143 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1144 struct s3c_hsotg *hsotg = hs_ep->parent;
1146 if (req->status < 0) {
1147 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1151 if (req->actual == 0)
1152 s3c_hsotg_enqueue_setup(hsotg);
1154 s3c_hsotg_process_control(hsotg, req->buf);
1158 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1159 * @hsotg: The device state.
1161 * Enqueue a request on EP0 if necessary to received any SETUP packets
1162 * received from the host.
1164 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1166 struct usb_request *req = hsotg->ctrl_req;
1167 struct s3c_hsotg_req *hs_req = our_req(req);
1170 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1174 req->buf = hsotg->ctrl_buff;
1175 req->complete = s3c_hsotg_complete_setup;
1177 if (!list_empty(&hs_req->queue)) {
1178 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1182 hsotg->eps[0].dir_in = 0;
1184 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1186 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1187 /* Don't think there's much we can do other than watch the
1193 * get_ep_head - return the first request on the endpoint
1194 * @hs_ep: The controller endpoint to get
1196 * Get the first request on the endpoint.
1198 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1200 if (list_empty(&hs_ep->queue))
1203 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1207 * s3c_hsotg_complete_request - complete a request given to us
1208 * @hsotg: The device state.
1209 * @hs_ep: The endpoint the request was on.
1210 * @hs_req: The request to complete.
1211 * @result: The result code (0 => Ok, otherwise errno)
1213 * The given request has finished, so call the necessary completion
1214 * if it has one and then look to see if we can start a new request
1217 * Note, expects the ep to already be locked as appropriate.
1219 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1220 struct s3c_hsotg_ep *hs_ep,
1221 struct s3c_hsotg_req *hs_req,
1227 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1231 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1232 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1234 /* only replace the status if we've not already set an error
1235 * from a previous transaction */
1237 if (hs_req->req.status == -EINPROGRESS)
1238 hs_req->req.status = result;
1241 list_del_init(&hs_req->queue);
1243 if (using_dma(hsotg))
1244 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1246 /* call the complete request with the locks off, just in case the
1247 * request tries to queue more work for this endpoint. */
1249 if (hs_req->req.complete) {
1250 spin_unlock(&hs_ep->lock);
1251 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1252 spin_lock(&hs_ep->lock);
1255 /* Look to see if there is anything else to do. Note, the completion
1256 * of the previous request may have caused a new request to be started
1257 * so be careful when doing this. */
1259 if (!hs_ep->req && result >= 0) {
1260 restart = !list_empty(&hs_ep->queue);
1262 hs_req = get_ep_head(hs_ep);
1263 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1269 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1270 * @hsotg: The device state.
1271 * @hs_ep: The endpoint the request was on.
1272 * @hs_req: The request to complete.
1273 * @result: The result code (0 => Ok, otherwise errno)
1275 * See s3c_hsotg_complete_request(), but called with the endpoint's
1278 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1279 struct s3c_hsotg_ep *hs_ep,
1280 struct s3c_hsotg_req *hs_req,
1283 unsigned long flags;
1285 spin_lock_irqsave(&hs_ep->lock, flags);
1286 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1287 spin_unlock_irqrestore(&hs_ep->lock, flags);
1291 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1292 * @hsotg: The device state.
1293 * @ep_idx: The endpoint index for the data
1294 * @size: The size of data in the fifo, in bytes
1296 * The FIFO status shows there is data to read from the FIFO for a given
1297 * endpoint, so sort out whether we need to read the data into a request
1298 * that has been made for that endpoint.
1300 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1302 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1303 struct s3c_hsotg_req *hs_req = hs_ep->req;
1304 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1310 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1313 dev_warn(hsotg->dev,
1314 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1315 __func__, size, ep_idx, epctl);
1317 /* dump the data from the FIFO, we've nothing we can do */
1318 for (ptr = 0; ptr < size; ptr += 4)
1324 spin_lock(&hs_ep->lock);
1327 read_ptr = hs_req->req.actual;
1328 max_req = hs_req->req.length - read_ptr;
1330 if (to_read > max_req) {
1331 /* more data appeared than we where willing
1332 * to deal with in this request.
1335 /* currently we don't deal this */
1339 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1340 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1342 hs_ep->total_data += to_read;
1343 hs_req->req.actual += to_read;
1344 to_read = DIV_ROUND_UP(to_read, 4);
1346 /* note, we might over-write the buffer end by 3 bytes depending on
1347 * alignment of the data. */
1348 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1350 spin_unlock(&hs_ep->lock);
1354 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1355 * @hsotg: The device instance
1356 * @req: The request currently on this endpoint
1358 * Generate a zero-length IN packet request for terminating a SETUP
1361 * Note, since we don't write any data to the TxFIFO, then it is
1362 * currently belived that we do not need to wait for any space in
1365 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1366 struct s3c_hsotg_req *req)
1371 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1375 if (req->req.length == 0) {
1376 hsotg->eps[0].sent_zlp = 1;
1377 s3c_hsotg_enqueue_setup(hsotg);
1381 hsotg->eps[0].dir_in = 1;
1382 hsotg->eps[0].sent_zlp = 1;
1384 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1386 /* issue a zero-sized packet to terminate this */
1387 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1388 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1390 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1391 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1392 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1393 ctrl |= S3C_DxEPCTL_USBActEp;
1394 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1398 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1399 * @hsotg: The device instance
1400 * @epnum: The endpoint received from
1401 * @was_setup: Set if processing a SetupDone event.
1403 * The RXFIFO has delivered an OutDone event, which means that the data
1404 * transfer for an OUT endpoint has been completed, either by a short
1405 * packet or by the finish of a transfer.
1407 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1408 int epnum, bool was_setup)
1410 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1411 struct s3c_hsotg_req *hs_req = hs_ep->req;
1412 struct usb_request *req = &hs_req->req;
1416 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1420 if (using_dma(hsotg)) {
1421 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1425 /* Calculate the size of the transfer by checking how much
1426 * is left in the endpoint size register and then working it
1427 * out from the amount we loaded for the transfer.
1429 * We need to do this as DMA pointers are always 32bit aligned
1430 * so may overshoot/undershoot the transfer.
1433 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1435 size_done = hs_ep->size_loaded - size_left;
1436 size_done += hs_ep->last_load;
1438 req->actual = size_done;
1441 if (req->actual < req->length && req->short_not_ok) {
1442 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1443 __func__, req->actual, req->length);
1445 /* todo - what should we return here? there's no one else
1446 * even bothering to check the status. */
1450 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1451 s3c_hsotg_send_zlp(hsotg, hs_req);
1454 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1458 * s3c_hsotg_read_frameno - read current frame number
1459 * @hsotg: The device instance
1461 * Return the current frame number
1463 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1467 dsts = readl(hsotg->regs + S3C_DSTS);
1468 dsts &= S3C_DSTS_SOFFN_MASK;
1469 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1475 * s3c_hsotg_handle_rx - RX FIFO has data
1476 * @hsotg: The device instance
1478 * The IRQ handler has detected that the RX FIFO has some data in it
1479 * that requires processing, so find out what is in there and do the
1482 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1483 * chunks, so if you have x packets received on an endpoint you'll get x
1484 * FIFO events delivered, each with a packet's worth of data in it.
1486 * When using DMA, we should not be processing events from the RXFIFO
1487 * as the actual data should be sent to the memory directly and we turn
1488 * on the completion interrupts to get notifications of transfer completion.
1490 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1492 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1493 u32 epnum, status, size;
1495 WARN_ON(using_dma(hsotg));
1497 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1498 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1500 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1501 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1504 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1505 __func__, grxstsr, size, epnum);
1507 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1509 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1510 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1511 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1514 case __status(S3C_GRXSTS_PktSts_OutDone):
1515 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1516 s3c_hsotg_read_frameno(hsotg));
1518 if (!using_dma(hsotg))
1519 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1522 case __status(S3C_GRXSTS_PktSts_SetupDone):
1524 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1525 s3c_hsotg_read_frameno(hsotg),
1526 readl(hsotg->regs + S3C_DOEPCTL(0)));
1528 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1531 case __status(S3C_GRXSTS_PktSts_OutRX):
1532 s3c_hsotg_rx_data(hsotg, epnum, size);
1535 case __status(S3C_GRXSTS_PktSts_SetupRX):
1537 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1538 s3c_hsotg_read_frameno(hsotg),
1539 readl(hsotg->regs + S3C_DOEPCTL(0)));
1541 s3c_hsotg_rx_data(hsotg, epnum, size);
1545 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1548 s3c_hsotg_dump(hsotg);
1554 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1555 * @mps: The maximum packet size in bytes.
1557 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1561 return S3C_D0EPCTL_MPS_64;
1563 return S3C_D0EPCTL_MPS_32;
1565 return S3C_D0EPCTL_MPS_16;
1567 return S3C_D0EPCTL_MPS_8;
1570 /* bad max packet size, warn and return invalid result */
1576 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1577 * @hsotg: The driver state.
1578 * @ep: The index number of the endpoint
1579 * @mps: The maximum packet size in bytes
1581 * Configure the maximum packet size for the given endpoint, updating
1582 * the hardware control registers to reflect this.
1584 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1585 unsigned int ep, unsigned int mps)
1587 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1588 void __iomem *regs = hsotg->regs;
1593 /* EP0 is a special case */
1594 mpsval = s3c_hsotg_ep0_mps(mps);
1598 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1604 hs_ep->ep.maxpacket = mps;
1606 /* update both the in and out endpoint controldir_ registers, even
1607 * if one of the directions may not be in use. */
1609 reg = readl(regs + S3C_DIEPCTL(ep));
1610 reg &= ~S3C_DxEPCTL_MPS_MASK;
1612 writel(reg, regs + S3C_DIEPCTL(ep));
1614 reg = readl(regs + S3C_DOEPCTL(ep));
1615 reg &= ~S3C_DxEPCTL_MPS_MASK;
1617 writel(reg, regs + S3C_DOEPCTL(ep));
1622 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1627 * s3c_hsotg_trytx - check to see if anything needs transmitting
1628 * @hsotg: The driver state
1629 * @hs_ep: The driver endpoint to check.
1631 * Check to see if there is a request that has data to send, and if so
1632 * make an attempt to write data into the FIFO.
1634 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1635 struct s3c_hsotg_ep *hs_ep)
1637 struct s3c_hsotg_req *hs_req = hs_ep->req;
1639 if (!hs_ep->dir_in || !hs_req)
1642 if (hs_req->req.actual < hs_req->req.length) {
1643 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1645 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1652 * s3c_hsotg_complete_in - complete IN transfer
1653 * @hsotg: The device state.
1654 * @hs_ep: The endpoint that has just completed.
1656 * An IN transfer has been completed, update the transfer's state and then
1657 * call the relevant completion routines.
1659 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1660 struct s3c_hsotg_ep *hs_ep)
1662 struct s3c_hsotg_req *hs_req = hs_ep->req;
1663 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1664 int size_left, size_done;
1667 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1671 /* Calculate the size of the transfer by checking how much is left
1672 * in the endpoint size register and then working it out from
1673 * the amount we loaded for the transfer.
1675 * We do this even for DMA, as the transfer may have incremented
1676 * past the end of the buffer (DMA transfers are always 32bit
1680 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1682 size_done = hs_ep->size_loaded - size_left;
1683 size_done += hs_ep->last_load;
1685 if (hs_req->req.actual != size_done)
1686 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1687 __func__, hs_req->req.actual, size_done);
1689 hs_req->req.actual = size_done;
1691 /* if we did all of the transfer, and there is more data left
1692 * around, then try restarting the rest of the request */
1694 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1695 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1696 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1698 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1702 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1703 * @hsotg: The driver state
1704 * @idx: The index for the endpoint (0..15)
1705 * @dir_in: Set if this is an IN endpoint
1707 * Process and clear any interrupt pending for an individual endpoint
1709 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1712 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1713 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1714 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1715 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1719 ints = readl(hsotg->regs + epint_reg);
1721 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1722 __func__, idx, dir_in ? "in" : "out", ints);
1724 if (ints & S3C_DxEPINT_XferCompl) {
1726 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1727 __func__, readl(hsotg->regs + epctl_reg),
1728 readl(hsotg->regs + epsiz_reg));
1730 /* we get OutDone from the FIFO, so we only need to look
1731 * at completing IN requests here */
1733 s3c_hsotg_complete_in(hsotg, hs_ep);
1736 s3c_hsotg_enqueue_setup(hsotg);
1737 } else if (using_dma(hsotg)) {
1738 /* We're using DMA, we need to fire an OutDone here
1739 * as we ignore the RXFIFO. */
1741 s3c_hsotg_handle_outdone(hsotg, idx, false);
1744 clear |= S3C_DxEPINT_XferCompl;
1747 if (ints & S3C_DxEPINT_EPDisbld) {
1748 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1749 clear |= S3C_DxEPINT_EPDisbld;
1752 if (ints & S3C_DxEPINT_AHBErr) {
1753 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1754 clear |= S3C_DxEPINT_AHBErr;
1757 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1758 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1760 if (using_dma(hsotg) && idx == 0) {
1761 /* this is the notification we've received a
1762 * setup packet. In non-DMA mode we'd get this
1763 * from the RXFIFO, instead we need to process
1764 * the setup here. */
1769 s3c_hsotg_handle_outdone(hsotg, 0, true);
1772 clear |= S3C_DxEPINT_Setup;
1775 if (ints & S3C_DxEPINT_Back2BackSetup) {
1776 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1777 clear |= S3C_DxEPINT_Back2BackSetup;
1781 /* not sure if this is important, but we'll clear it anyway
1783 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1784 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1786 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1789 /* this probably means something bad is happening */
1790 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1791 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1793 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1797 writel(clear, hsotg->regs + epint_reg);
1801 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1802 * @hsotg: The device state.
1804 * Handle updating the device settings after the enumeration phase has
1807 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1809 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1810 int ep0_mps = 0, ep_mps;
1812 /* This should signal the finish of the enumeration phase
1813 * of the USB handshaking, so we should now know what rate
1814 * we connected at. */
1816 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1818 /* note, since we're limited by the size of transfer on EP0, and
1819 * it seems IN transfers must be a even number of packets we do
1820 * not advertise a 64byte MPS on EP0. */
1822 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1823 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1824 case S3C_DSTS_EnumSpd_FS:
1825 case S3C_DSTS_EnumSpd_FS48:
1826 hsotg->gadget.speed = USB_SPEED_FULL;
1827 dev_info(hsotg->dev, "new device is full-speed\n");
1829 ep0_mps = EP0_MPS_LIMIT;
1833 case S3C_DSTS_EnumSpd_HS:
1834 dev_info(hsotg->dev, "new device is high-speed\n");
1835 hsotg->gadget.speed = USB_SPEED_HIGH;
1837 ep0_mps = EP0_MPS_LIMIT;
1841 case S3C_DSTS_EnumSpd_LS:
1842 hsotg->gadget.speed = USB_SPEED_LOW;
1843 dev_info(hsotg->dev, "new device is low-speed\n");
1845 /* note, we don't actually support LS in this driver at the
1846 * moment, and the documentation seems to imply that it isn't
1847 * supported by the PHYs on some of the devices.
1852 /* we should now know the maximum packet size for an
1853 * endpoint, so set the endpoints to a default value. */
1857 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1858 for (i = 1; i < S3C_HSOTG_EPS; i++)
1859 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1862 /* ensure after enumeration our EP0 is active */
1864 s3c_hsotg_enqueue_setup(hsotg);
1866 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1867 readl(hsotg->regs + S3C_DIEPCTL0),
1868 readl(hsotg->regs + S3C_DOEPCTL0));
1872 * kill_all_requests - remove all requests from the endpoint's queue
1873 * @hsotg: The device state.
1874 * @ep: The endpoint the requests may be on.
1875 * @result: The result code to use.
1876 * @force: Force removal of any current requests
1878 * Go through the requests on the given endpoint and mark them
1879 * completed with the given result code.
1881 static void kill_all_requests(struct s3c_hsotg *hsotg,
1882 struct s3c_hsotg_ep *ep,
1883 int result, bool force)
1885 struct s3c_hsotg_req *req, *treq;
1886 unsigned long flags;
1888 spin_lock_irqsave(&ep->lock, flags);
1890 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1891 /* currently, we can't do much about an already
1892 * running request on an in endpoint */
1894 if (ep->req == req && ep->dir_in && !force)
1897 s3c_hsotg_complete_request(hsotg, ep, req,
1901 spin_unlock_irqrestore(&ep->lock, flags);
1904 #define call_gadget(_hs, _entry) \
1905 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1906 (_hs)->driver && (_hs)->driver->_entry) \
1907 (_hs)->driver->_entry(&(_hs)->gadget);
1910 * s3c_hsotg_disconnect_irq - disconnect irq service
1911 * @hsotg: The device state.
1913 * A disconnect IRQ has been received, meaning that the host has
1914 * lost contact with the bus. Remove all current transactions
1915 * and signal the gadget driver that this has happened.
1917 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1921 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1922 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1924 call_gadget(hsotg, disconnect);
1928 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1929 * @hsotg: The device state:
1930 * @periodic: True if this is a periodic FIFO interrupt
1932 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1934 struct s3c_hsotg_ep *ep;
1937 /* look through for any more data to transmit */
1939 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
1940 ep = &hsotg->eps[epno];
1945 if ((periodic && !ep->periodic) ||
1946 (!periodic && ep->periodic))
1949 ret = s3c_hsotg_trytx(hsotg, ep);
1955 static struct s3c_hsotg *our_hsotg;
1957 /* IRQ flags which will trigger a retry around the IRQ loop */
1958 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
1959 S3C_GINTSTS_PTxFEmp | \
1963 * s3c_hsotg_irq - handle device interrupt
1964 * @irq: The IRQ number triggered
1965 * @pw: The pw value when registered the handler.
1967 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
1969 struct s3c_hsotg *hsotg = pw;
1970 int retry_count = 8;
1975 gintsts = readl(hsotg->regs + S3C_GINTSTS);
1976 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
1978 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
1979 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
1983 if (gintsts & S3C_GINTSTS_OTGInt) {
1984 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
1986 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
1988 writel(otgint, hsotg->regs + S3C_GOTGINT);
1989 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
1992 if (gintsts & S3C_GINTSTS_DisconnInt) {
1993 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
1994 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
1996 s3c_hsotg_disconnect_irq(hsotg);
1999 if (gintsts & S3C_GINTSTS_SessReqInt) {
2000 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2001 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2004 if (gintsts & S3C_GINTSTS_EnumDone) {
2005 s3c_hsotg_irq_enumdone(hsotg);
2006 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2009 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2010 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2011 readl(hsotg->regs + S3C_DSTS),
2012 readl(hsotg->regs + S3C_GOTGCTL));
2014 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2017 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2018 u32 daint = readl(hsotg->regs + S3C_DAINT);
2019 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2020 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2023 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2025 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2027 s3c_hsotg_epint(hsotg, ep, 0);
2030 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2032 s3c_hsotg_epint(hsotg, ep, 1);
2035 writel(daint, hsotg->regs + S3C_DAINT);
2036 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2037 hsotg->regs + S3C_GINTSTS);
2040 if (gintsts & S3C_GINTSTS_USBRst) {
2041 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2042 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2043 readl(hsotg->regs + S3C_GNPTXSTS));
2045 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2047 /* it seems after a reset we can end up with a situation
2048 * where the TXFIFO still has data in it... try flushing
2049 * it to remove anything that may still be in it.
2053 writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
2054 hsotg->regs + S3C_GRSTCTL);
2056 dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
2057 readl(hsotg->regs + S3C_GNPTXSTS));
2060 s3c_hsotg_enqueue_setup(hsotg);
2062 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2065 /* check both FIFOs */
2067 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2068 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2070 /* Disable the interrupt to stop it happening again
2071 * unless one of these endpoint routines decides that
2072 * it needs re-enabling */
2074 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2075 s3c_hsotg_irq_fifoempty(hsotg, false);
2077 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2080 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2081 dev_dbg(hsotg->dev, "PTxFEmp\n");
2083 /* See note in S3C_GINTSTS_NPTxFEmp */
2085 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2086 s3c_hsotg_irq_fifoempty(hsotg, true);
2088 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2091 if (gintsts & S3C_GINTSTS_RxFLvl) {
2092 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2093 * we need to retry s3c_hsotg_handle_rx if this is still
2096 s3c_hsotg_handle_rx(hsotg);
2097 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2100 if (gintsts & S3C_GINTSTS_ModeMis) {
2101 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2102 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2105 if (gintsts & S3C_GINTSTS_USBSusp) {
2106 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2107 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2109 call_gadget(hsotg, suspend);
2112 if (gintsts & S3C_GINTSTS_WkUpInt) {
2113 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2114 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2116 call_gadget(hsotg, resume);
2119 if (gintsts & S3C_GINTSTS_ErlySusp) {
2120 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2121 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2124 /* these next two seem to crop-up occasionally causing the core
2125 * to shutdown the USB transfer, so try clearing them and logging
2128 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2129 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2131 s3c_hsotg_dump(hsotg);
2133 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2134 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2137 if (gintsts & S3C_GINTSTS_GINNakEff) {
2138 dev_info(hsotg->dev, "GINNakEff triggered\n");
2140 s3c_hsotg_dump(hsotg);
2142 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2143 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2146 /* if we've had fifo events, we should try and go around the
2147 * loop again to see if there's any point in returning yet. */
2149 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2156 * s3c_hsotg_ep_enable - enable the given endpoint
2157 * @ep: The USB endpint to configure
2158 * @desc: The USB endpoint descriptor to configure with.
2160 * This is called from the USB gadget code's usb_ep_enable().
2162 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2163 const struct usb_endpoint_descriptor *desc)
2165 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2166 struct s3c_hsotg *hsotg = hs_ep->parent;
2167 unsigned long flags;
2168 int index = hs_ep->index;
2176 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2177 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2178 desc->wMaxPacketSize, desc->bInterval);
2180 /* not to be called for EP0 */
2181 WARN_ON(index == 0);
2183 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2184 if (dir_in != hs_ep->dir_in) {
2185 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2189 mps = le16_to_cpu(desc->wMaxPacketSize);
2191 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2193 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2194 epctrl = readl(hsotg->regs + epctrl_reg);
2196 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2197 __func__, epctrl, epctrl_reg);
2199 spin_lock_irqsave(&hs_ep->lock, flags);
2201 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2202 epctrl |= S3C_DxEPCTL_MPS(mps);
2204 /* mark the endpoint as active, otherwise the core may ignore
2205 * transactions entirely for this endpoint */
2206 epctrl |= S3C_DxEPCTL_USBActEp;
2208 /* set the NAK status on the endpoint, otherwise we might try and
2209 * do something with data that we've yet got a request to process
2210 * since the RXFIFO will take data for an endpoint even if the
2211 * size register hasn't been set.
2214 epctrl |= S3C_DxEPCTL_SNAK;
2216 /* update the endpoint state */
2217 hs_ep->ep.maxpacket = mps;
2219 /* default, set to non-periodic */
2220 hs_ep->periodic = 0;
2222 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2223 case USB_ENDPOINT_XFER_ISOC:
2224 dev_err(hsotg->dev, "no current ISOC support\n");
2228 case USB_ENDPOINT_XFER_BULK:
2229 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2232 case USB_ENDPOINT_XFER_INT:
2234 /* Allocate our TxFNum by simply using the index
2235 * of the endpoint for the moment. We could do
2236 * something better if the host indicates how
2237 * many FIFOs we are expecting to use. */
2239 hs_ep->periodic = 1;
2240 epctrl |= S3C_DxEPCTL_TxFNum(index);
2243 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2246 case USB_ENDPOINT_XFER_CONTROL:
2247 epctrl |= S3C_DxEPCTL_EPType_Control;
2251 /* for non control endpoints, set PID to D0 */
2253 epctrl |= S3C_DxEPCTL_SetD0PID;
2255 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2258 writel(epctrl, hsotg->regs + epctrl_reg);
2259 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2260 __func__, readl(hsotg->regs + epctrl_reg));
2262 /* enable the endpoint interrupt */
2263 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2266 spin_unlock_irqrestore(&hs_ep->lock, flags);
2270 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2272 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2273 struct s3c_hsotg *hsotg = hs_ep->parent;
2274 int dir_in = hs_ep->dir_in;
2275 int index = hs_ep->index;
2276 unsigned long flags;
2280 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2282 if (ep == &hsotg->eps[0].ep) {
2283 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2287 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2289 /* terminate all requests with shutdown */
2290 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2292 spin_lock_irqsave(&hs_ep->lock, flags);
2294 ctrl = readl(hsotg->regs + epctrl_reg);
2295 ctrl &= ~S3C_DxEPCTL_EPEna;
2296 ctrl &= ~S3C_DxEPCTL_USBActEp;
2297 ctrl |= S3C_DxEPCTL_SNAK;
2299 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2300 writel(ctrl, hsotg->regs + epctrl_reg);
2302 /* disable endpoint interrupts */
2303 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2305 spin_unlock_irqrestore(&hs_ep->lock, flags);
2310 * on_list - check request is on the given endpoint
2311 * @ep: The endpoint to check.
2312 * @test: The request to test if it is on the endpoint.
2314 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2316 struct s3c_hsotg_req *req, *treq;
2318 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2326 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2328 struct s3c_hsotg_req *hs_req = our_req(req);
2329 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2330 struct s3c_hsotg *hs = hs_ep->parent;
2331 unsigned long flags;
2333 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2335 if (hs_req == hs_ep->req) {
2336 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2337 return -EINPROGRESS;
2340 spin_lock_irqsave(&hs_ep->lock, flags);
2342 if (!on_list(hs_ep, hs_req)) {
2343 spin_unlock_irqrestore(&hs_ep->lock, flags);
2347 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2348 spin_unlock_irqrestore(&hs_ep->lock, flags);
2353 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2355 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2356 struct s3c_hsotg *hs = hs_ep->parent;
2357 int index = hs_ep->index;
2358 unsigned long irqflags;
2362 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2364 spin_lock_irqsave(&hs_ep->lock, irqflags);
2366 /* write both IN and OUT control registers */
2368 epreg = S3C_DIEPCTL(index);
2369 epctl = readl(hs->regs + epreg);
2372 epctl |= S3C_DxEPCTL_Stall;
2374 epctl &= ~S3C_DxEPCTL_Stall;
2376 writel(epctl, hs->regs + epreg);
2378 epreg = S3C_DOEPCTL(index);
2379 epctl = readl(hs->regs + epreg);
2382 epctl |= S3C_DxEPCTL_Stall;
2384 epctl &= ~S3C_DxEPCTL_Stall;
2386 writel(epctl, hs->regs + epreg);
2388 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2393 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2394 .enable = s3c_hsotg_ep_enable,
2395 .disable = s3c_hsotg_ep_disable,
2396 .alloc_request = s3c_hsotg_ep_alloc_request,
2397 .free_request = s3c_hsotg_ep_free_request,
2398 .queue = s3c_hsotg_ep_queue,
2399 .dequeue = s3c_hsotg_ep_dequeue,
2400 .set_halt = s3c_hsotg_ep_sethalt,
2401 /* note, don't belive we have any call for the fifo routines */
2405 * s3c_hsotg_corereset - issue softreset to the core
2406 * @hsotg: The device state
2408 * Issue a soft reset to the core, and await the core finishing it.
2410 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2415 dev_dbg(hsotg->dev, "resetting core\n");
2417 /* issue soft reset */
2418 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2422 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2423 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2425 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2426 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2433 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2435 if (timeout-- < 0) {
2436 dev_info(hsotg->dev,
2437 "%s: reset failed, GRSTCTL=%08x\n",
2442 if (grstctl & S3C_GRSTCTL_CSftRst)
2445 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2448 break; /* reset done */
2451 dev_dbg(hsotg->dev, "reset successful\n");
2455 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2457 struct s3c_hsotg *hsotg = our_hsotg;
2461 printk(KERN_ERR "%s: called with no device\n", __func__);
2466 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2470 if (driver->speed != USB_SPEED_HIGH &&
2471 driver->speed != USB_SPEED_FULL) {
2472 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2475 if (!driver->bind || !driver->setup) {
2476 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2480 WARN_ON(hsotg->driver);
2482 driver->driver.bus = NULL;
2483 hsotg->driver = driver;
2484 hsotg->gadget.dev.driver = &driver->driver;
2485 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2486 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2488 ret = device_add(&hsotg->gadget.dev);
2490 dev_err(hsotg->dev, "failed to register gadget device\n");
2494 ret = driver->bind(&hsotg->gadget);
2496 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2498 hsotg->gadget.dev.driver = NULL;
2499 hsotg->driver = NULL;
2503 /* we must now enable ep0 ready for host detection and then
2504 * set configuration. */
2506 s3c_hsotg_corereset(hsotg);
2508 /* set the PLL on, remove the HNP/SRP and set the PHY */
2509 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2510 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2512 /* looks like soft-reset changes state of FIFOs */
2513 s3c_hsotg_init_fifo(hsotg);
2515 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2517 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2519 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2520 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2521 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2522 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2523 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2524 S3C_GINTSTS_ErlySusp,
2525 hsotg->regs + S3C_GINTMSK);
2527 if (using_dma(hsotg))
2528 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2529 S3C_GAHBCFG_HBstLen_Incr4,
2530 hsotg->regs + S3C_GAHBCFG);
2532 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2534 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2535 * up being flooded with interrupts if the host is polling the
2536 * endpoint to try and read data. */
2538 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2539 S3C_DIEPMSK_INTknEPMisMsk |
2540 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2541 hsotg->regs + S3C_DIEPMSK);
2543 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2544 * DMA mode we may need this. */
2545 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2546 S3C_DOEPMSK_EPDisbldMsk |
2547 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2548 S3C_DIEPMSK_TimeOUTMsk) : 0),
2549 hsotg->regs + S3C_DOEPMSK);
2551 writel(0, hsotg->regs + S3C_DAINTMSK);
2553 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2554 readl(hsotg->regs + S3C_DIEPCTL0),
2555 readl(hsotg->regs + S3C_DOEPCTL0));
2557 /* enable in and out endpoint interrupts */
2558 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2560 /* Enable the RXFIFO when in slave mode, as this is how we collect
2561 * the data. In DMA mode, we get events from the FIFO but also
2562 * things we cannot process, so do not use it. */
2563 if (!using_dma(hsotg))
2564 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2566 /* Enable interrupts for EP0 in and out */
2567 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2568 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2570 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2571 udelay(10); /* see openiboot */
2572 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2574 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2576 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2577 writing to the EPCTL register.. */
2579 /* set to read 1 8byte packet */
2580 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2581 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2583 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2584 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2585 S3C_DxEPCTL_USBActEp,
2586 hsotg->regs + S3C_DOEPCTL0);
2588 /* enable, but don't activate EP0in */
2589 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2590 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2592 s3c_hsotg_enqueue_setup(hsotg);
2594 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2595 readl(hsotg->regs + S3C_DIEPCTL0),
2596 readl(hsotg->regs + S3C_DOEPCTL0));
2598 /* clear global NAKs */
2599 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2600 hsotg->regs + S3C_DCTL);
2602 /* must be at-least 3ms to allow bus to see disconnect */
2605 /* remove the soft-disconnect and let's go */
2606 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2608 /* report to the user, and return */
2610 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2614 hsotg->driver = NULL;
2615 hsotg->gadget.dev.driver = NULL;
2618 EXPORT_SYMBOL(usb_gadget_register_driver);
2620 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2622 struct s3c_hsotg *hsotg = our_hsotg;
2628 if (!driver || driver != hsotg->driver || !driver->unbind)
2631 /* all endpoints should be shutdown */
2632 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2633 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2635 call_gadget(hsotg, disconnect);
2637 driver->unbind(&hsotg->gadget);
2638 hsotg->driver = NULL;
2639 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2641 device_del(&hsotg->gadget.dev);
2643 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2644 driver->driver.name);
2648 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2650 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2652 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2655 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2656 .get_frame = s3c_hsotg_gadget_getframe,
2660 * s3c_hsotg_initep - initialise a single endpoint
2661 * @hsotg: The device state.
2662 * @hs_ep: The endpoint to be initialised.
2663 * @epnum: The endpoint number
2665 * Initialise the given endpoint (as part of the probe and device state
2666 * creation) to give to the gadget driver. Setup the endpoint name, any
2667 * direction information and other state that may be required.
2669 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2670 struct s3c_hsotg_ep *hs_ep,
2678 else if ((epnum % 2) == 0) {
2685 hs_ep->index = epnum;
2687 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2689 INIT_LIST_HEAD(&hs_ep->queue);
2690 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2692 spin_lock_init(&hs_ep->lock);
2694 /* add to the list of endpoints known by the gadget driver */
2696 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2698 hs_ep->parent = hsotg;
2699 hs_ep->ep.name = hs_ep->name;
2700 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2701 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2703 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2704 * an OUT endpoint, we may as well do this if in future the
2705 * code is changed to make each endpoint's direction changeable.
2708 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2709 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
2711 /* if we're using dma, we need to set the next-endpoint pointer
2712 * to be something valid.
2715 if (using_dma(hsotg)) {
2716 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2717 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2718 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2723 * s3c_hsotg_otgreset - reset the OtG phy block
2724 * @hsotg: The host state.
2726 * Power up the phy, set the basic configuration and start the PHY.
2728 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2732 writel(0, S3C_PHYPWR);
2735 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2737 writel(osc | 0x10, S3C_PHYCLK);
2739 /* issue a full set of resets to the otg and core */
2741 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2742 udelay(20); /* at-least 10uS */
2743 writel(0, S3C_RSTCON);
2747 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2749 /* unmask subset of endpoint interrupts */
2751 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2752 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2753 hsotg->regs + S3C_DIEPMSK);
2755 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2756 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2757 hsotg->regs + S3C_DOEPMSK);
2759 writel(0, hsotg->regs + S3C_DAINTMSK);
2761 /* Be in disconnected state until gadget is registered */
2762 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2765 /* post global nak until we're ready */
2766 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2767 hsotg->regs + S3C_DCTL);
2772 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2773 readl(hsotg->regs + S3C_GRXFSIZ),
2774 readl(hsotg->regs + S3C_GNPTXFSIZ));
2776 s3c_hsotg_init_fifo(hsotg);
2778 /* set the PLL on, remove the HNP/SRP and set the PHY */
2779 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2780 hsotg->regs + S3C_GUSBCFG);
2782 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2783 hsotg->regs + S3C_GAHBCFG);
2786 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2788 struct device *dev = hsotg->dev;
2789 void __iomem *regs = hsotg->regs;
2793 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2794 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2795 readl(regs + S3C_DIEPMSK));
2797 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2798 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2800 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2801 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2803 /* show periodic fifo settings */
2805 for (idx = 1; idx <= 15; idx++) {
2806 val = readl(regs + S3C_DPTXFSIZn(idx));
2807 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2808 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2809 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2812 for (idx = 0; idx < 15; idx++) {
2814 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2815 readl(regs + S3C_DIEPCTL(idx)),
2816 readl(regs + S3C_DIEPTSIZ(idx)),
2817 readl(regs + S3C_DIEPDMA(idx)));
2819 val = readl(regs + S3C_DOEPCTL(idx));
2821 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2822 idx, readl(regs + S3C_DOEPCTL(idx)),
2823 readl(regs + S3C_DOEPTSIZ(idx)),
2824 readl(regs + S3C_DOEPDMA(idx)));
2828 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2829 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2834 * state_show - debugfs: show overall driver and device state.
2835 * @seq: The seq file to write to.
2836 * @v: Unused parameter.
2838 * This debugfs entry shows the overall state of the hardware and
2839 * some general information about each of the endpoints available
2842 static int state_show(struct seq_file *seq, void *v)
2844 struct s3c_hsotg *hsotg = seq->private;
2845 void __iomem *regs = hsotg->regs;
2848 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2849 readl(regs + S3C_DCFG),
2850 readl(regs + S3C_DCTL),
2851 readl(regs + S3C_DSTS));
2853 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2854 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2856 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2857 readl(regs + S3C_GINTMSK),
2858 readl(regs + S3C_GINTSTS));
2860 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2861 readl(regs + S3C_DAINTMSK),
2862 readl(regs + S3C_DAINT));
2864 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2865 readl(regs + S3C_GNPTXSTS),
2866 readl(regs + S3C_GRXSTSR));
2868 seq_printf(seq, "\nEndpoint status:\n");
2870 for (idx = 0; idx < 15; idx++) {
2873 in = readl(regs + S3C_DIEPCTL(idx));
2874 out = readl(regs + S3C_DOEPCTL(idx));
2876 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2879 in = readl(regs + S3C_DIEPTSIZ(idx));
2880 out = readl(regs + S3C_DOEPTSIZ(idx));
2882 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2885 seq_printf(seq, "\n");
2891 static int state_open(struct inode *inode, struct file *file)
2893 return single_open(file, state_show, inode->i_private);
2896 static const struct file_operations state_fops = {
2897 .owner = THIS_MODULE,
2900 .llseek = seq_lseek,
2901 .release = single_release,
2905 * fifo_show - debugfs: show the fifo information
2906 * @seq: The seq_file to write data to.
2907 * @v: Unused parameter.
2909 * Show the FIFO information for the overall fifo and all the
2910 * periodic transmission FIFOs.
2912 static int fifo_show(struct seq_file *seq, void *v)
2914 struct s3c_hsotg *hsotg = seq->private;
2915 void __iomem *regs = hsotg->regs;
2919 seq_printf(seq, "Non-periodic FIFOs:\n");
2920 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2922 val = readl(regs + S3C_GNPTXFSIZ);
2923 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2924 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
2925 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
2927 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
2929 for (idx = 1; idx <= 15; idx++) {
2930 val = readl(regs + S3C_DPTXFSIZn(idx));
2932 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2933 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2934 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2940 static int fifo_open(struct inode *inode, struct file *file)
2942 return single_open(file, fifo_show, inode->i_private);
2945 static const struct file_operations fifo_fops = {
2946 .owner = THIS_MODULE,
2949 .llseek = seq_lseek,
2950 .release = single_release,
2954 static const char *decode_direction(int is_in)
2956 return is_in ? "in" : "out";
2960 * ep_show - debugfs: show the state of an endpoint.
2961 * @seq: The seq_file to write data to.
2962 * @v: Unused parameter.
2964 * This debugfs entry shows the state of the given endpoint (one is
2965 * registered for each available).
2967 static int ep_show(struct seq_file *seq, void *v)
2969 struct s3c_hsotg_ep *ep = seq->private;
2970 struct s3c_hsotg *hsotg = ep->parent;
2971 struct s3c_hsotg_req *req;
2972 void __iomem *regs = hsotg->regs;
2973 int index = ep->index;
2974 int show_limit = 15;
2975 unsigned long flags;
2977 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
2978 ep->index, ep->ep.name, decode_direction(ep->dir_in));
2980 /* first show the register state */
2982 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
2983 readl(regs + S3C_DIEPCTL(index)),
2984 readl(regs + S3C_DOEPCTL(index)));
2986 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
2987 readl(regs + S3C_DIEPDMA(index)),
2988 readl(regs + S3C_DOEPDMA(index)));
2990 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
2991 readl(regs + S3C_DIEPINT(index)),
2992 readl(regs + S3C_DOEPINT(index)));
2994 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
2995 readl(regs + S3C_DIEPTSIZ(index)),
2996 readl(regs + S3C_DOEPTSIZ(index)));
2998 seq_printf(seq, "\n");
2999 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3000 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3002 seq_printf(seq, "request list (%p,%p):\n",
3003 ep->queue.next, ep->queue.prev);
3005 spin_lock_irqsave(&ep->lock, flags);
3007 list_for_each_entry(req, &ep->queue, queue) {
3008 if (--show_limit < 0) {
3009 seq_printf(seq, "not showing more requests...\n");
3013 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3014 req == ep->req ? '*' : ' ',
3015 req, req->req.length, req->req.buf);
3016 seq_printf(seq, "%d done, res %d\n",
3017 req->req.actual, req->req.status);
3020 spin_unlock_irqrestore(&ep->lock, flags);
3025 static int ep_open(struct inode *inode, struct file *file)
3027 return single_open(file, ep_show, inode->i_private);
3030 static const struct file_operations ep_fops = {
3031 .owner = THIS_MODULE,
3034 .llseek = seq_lseek,
3035 .release = single_release,
3039 * s3c_hsotg_create_debug - create debugfs directory and files
3040 * @hsotg: The driver state
3042 * Create the debugfs files to allow the user to get information
3043 * about the state of the system. The directory name is created
3044 * with the same name as the device itself, in case we end up
3045 * with multiple blocks in future systems.
3047 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3049 struct dentry *root;
3052 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3053 hsotg->debug_root = root;
3055 dev_err(hsotg->dev, "cannot create debug root\n");
3059 /* create general state file */
3061 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3062 hsotg, &state_fops);
3064 if (IS_ERR(hsotg->debug_file))
3065 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3067 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3070 if (IS_ERR(hsotg->debug_fifo))
3071 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3073 /* create one file for each endpoint */
3075 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3076 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3078 ep->debugfs = debugfs_create_file(ep->name, 0444,
3079 root, ep, &ep_fops);
3081 if (IS_ERR(ep->debugfs))
3082 dev_err(hsotg->dev, "failed to create %s debug file\n",
3088 * s3c_hsotg_delete_debug - cleanup debugfs entries
3089 * @hsotg: The driver state
3091 * Cleanup (remove) the debugfs files for use on module exit.
3093 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3097 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3098 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3099 debugfs_remove(ep->debugfs);
3102 debugfs_remove(hsotg->debug_file);
3103 debugfs_remove(hsotg->debug_fifo);
3104 debugfs_remove(hsotg->debug_root);
3108 * s3c_hsotg_gate - set the hardware gate for the block
3109 * @pdev: The device we bound to
3112 * Set the hardware gate setting into the block. If we end up on
3113 * something other than an S3C64XX, then we might need to change this
3114 * to using a platform data callback, or some other mechanism.
3116 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3118 unsigned long flags;
3121 local_irq_save(flags);
3123 others = __raw_readl(S3C64XX_OTHERS);
3125 others |= S3C64XX_OTHERS_USBMASK;
3127 others &= ~S3C64XX_OTHERS_USBMASK;
3128 __raw_writel(others, S3C64XX_OTHERS);
3130 local_irq_restore(flags);
3133 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3135 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3137 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3138 struct device *dev = &pdev->dev;
3139 struct s3c_hsotg *hsotg;
3140 struct resource *res;
3145 plat = &s3c_hsotg_default_pdata;
3147 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3148 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3151 dev_err(dev, "cannot get memory\n");
3158 platform_set_drvdata(pdev, hsotg);
3160 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3162 dev_err(dev, "cannot find register resource 0\n");
3167 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3169 if (!hsotg->regs_res) {
3170 dev_err(dev, "cannot reserve registers\n");
3175 hsotg->regs = ioremap(res->start, resource_size(res));
3177 dev_err(dev, "cannot map registers\n");
3182 ret = platform_get_irq(pdev, 0);
3184 dev_err(dev, "cannot find IRQ\n");
3190 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3192 dev_err(dev, "cannot claim IRQ\n");
3196 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3198 device_initialize(&hsotg->gadget.dev);
3200 dev_set_name(&hsotg->gadget.dev, "gadget");
3202 hsotg->gadget.is_dualspeed = 1;
3203 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3204 hsotg->gadget.name = dev_name(dev);
3206 hsotg->gadget.dev.parent = dev;
3207 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3209 /* setup endpoint information */
3211 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3212 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3214 /* allocate EP0 request */
3216 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3218 if (!hsotg->ctrl_req) {
3219 dev_err(dev, "failed to allocate ctrl req\n");
3223 /* reset the system */
3225 s3c_hsotg_gate(pdev, true);
3227 s3c_hsotg_otgreset(hsotg);
3228 s3c_hsotg_corereset(hsotg);
3229 s3c_hsotg_init(hsotg);
3231 /* initialise the endpoints now the core has been initialised */
3232 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3233 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3235 s3c_hsotg_create_debug(hsotg);
3237 s3c_hsotg_dump(hsotg);
3243 iounmap(hsotg->regs);
3246 release_resource(hsotg->regs_res);
3247 kfree(hsotg->regs_res);
3254 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3256 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3258 s3c_hsotg_delete_debug(hsotg);
3260 usb_gadget_unregister_driver(hsotg->driver);
3262 free_irq(hsotg->irq, hsotg);
3263 iounmap(hsotg->regs);
3265 release_resource(hsotg->regs_res);
3266 kfree(hsotg->regs_res);
3268 s3c_hsotg_gate(pdev, false);
3275 #define s3c_hsotg_suspend NULL
3276 #define s3c_hsotg_resume NULL
3279 static struct platform_driver s3c_hsotg_driver = {
3281 .name = "s3c-hsotg",
3282 .owner = THIS_MODULE,
3284 .probe = s3c_hsotg_probe,
3285 .remove = __devexit_p(s3c_hsotg_remove),
3286 .suspend = s3c_hsotg_suspend,
3287 .resume = s3c_hsotg_resume,
3290 static int __init s3c_hsotg_modinit(void)
3292 return platform_driver_register(&s3c_hsotg_driver);
3295 static void __exit s3c_hsotg_modexit(void)
3297 platform_driver_unregister(&s3c_hsotg_driver);
3300 module_init(s3c_hsotg_modinit);
3301 module_exit(s3c_hsotg_modexit);
3303 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3304 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3305 MODULE_LICENSE("GPL");
3306 MODULE_ALIAS("platform:s3c-hsotg");