1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
35 #include <plat/regs-usb-hsotg-phy.h>
36 #include <plat/regs-usb-hsotg.h>
37 #include <mach/regs-sys.h>
38 #include <plat/udc-hs.h>
41 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
45 * Unfortunately there seems to be a limit of the amount of data that can
46 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
47 * packets (which practially means 1 packet and 63 bytes of data) when the
50 * This means if we are wanting to move >127 bytes of data, we need to
51 * split the transactions up, but just doing one packet at a time does
52 * not work (this may be an implicit DATA0 PID on first packet of the
53 * transaction) and doing 2 packets is outside the controller's limits.
55 * If we try to lower the MPS size for EP0, then no transfers work properly
56 * for EP0, and the system will fail basic enumeration. As no cause for this
57 * has currently been found, we cannot support any large IN transfers for
60 #define EP0_MPS_LIMIT 64
66 * struct s3c_hsotg_ep - driver endpoint definition.
67 * @ep: The gadget layer representation of the endpoint.
68 * @name: The driver generated name for the endpoint.
69 * @queue: Queue of requests for this endpoint.
70 * @parent: Reference back to the parent device structure.
71 * @req: The current request that the endpoint is processing. This is
72 * used to indicate an request has been loaded onto the endpoint
73 * and has yet to be completed (maybe due to data move, or simply
74 * awaiting an ack from the core all the data has been completed).
75 * @debugfs: File entry for debugfs file for this endpoint.
76 * @lock: State lock to protect contents of endpoint.
77 * @dir_in: Set to true if this endpoint is of the IN direction, which
78 * means that it is sending data to the Host.
79 * @index: The index for the endpoint registers.
80 * @name: The name array passed to the USB core.
81 * @halted: Set if the endpoint has been halted.
82 * @periodic: Set if this is a periodic ep, such as Interrupt
83 * @sent_zlp: Set if we've sent a zero-length packet.
84 * @total_data: The total number of data bytes done.
85 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
86 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
87 * @last_load: The offset of data for the last start of request.
88 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
90 * This is the driver's state for each registered enpoint, allowing it
91 * to keep track of transactions that need doing. Each endpoint has a
92 * lock to protect the state, to try and avoid using an overall lock
93 * for the host controller as much as possible.
95 * For periodic IN endpoints, we have fifo_size and fifo_load to try
96 * and keep track of the amount of data in the periodic FIFO for each
97 * of these as we don't have a status register that tells us how much
98 * is in each of them. (note, this may actually be useless information
99 * as in shared-fifo mode periodic in acts like a single-frame packet
100 * buffer than a fifo)
102 struct s3c_hsotg_ep {
104 struct list_head queue;
105 struct s3c_hsotg *parent;
106 struct s3c_hsotg_req *req;
107 struct dentry *debugfs;
111 unsigned long total_data;
112 unsigned int size_loaded;
113 unsigned int last_load;
114 unsigned int fifo_load;
115 unsigned short fifo_size;
117 unsigned char dir_in;
120 unsigned int halted:1;
121 unsigned int periodic:1;
122 unsigned int sent_zlp:1;
127 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
130 * struct s3c_hsotg - driver state.
131 * @dev: The parent device supplied to the probe function
132 * @driver: USB gadget driver
133 * @plat: The platform specific configuration data.
134 * @regs: The memory area mapped for accessing registers.
135 * @regs_res: The resource that was allocated when claiming register space.
136 * @irq: The IRQ number we are using
137 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
138 * @debug_root: root directrory for debugfs.
139 * @debug_file: main status file for debugfs.
140 * @debug_fifo: FIFO status file for debugfs.
141 * @ep0_reply: Request used for ep0 reply.
142 * @ep0_buff: Buffer for EP0 reply data, if needed.
143 * @ctrl_buff: Buffer for EP0 control requests.
144 * @ctrl_req: Request for EP0 control packets.
145 * @eps: The endpoints being supplied to the gadget framework
149 struct usb_gadget_driver *driver;
150 struct s3c_hsotg_plat *plat;
153 struct resource *regs_res;
156 unsigned int dedicated_fifos:1;
158 struct dentry *debug_root;
159 struct dentry *debug_file;
160 struct dentry *debug_fifo;
162 struct usb_request *ep0_reply;
163 struct usb_request *ctrl_req;
167 struct usb_gadget gadget;
168 struct s3c_hsotg_ep eps[];
172 * struct s3c_hsotg_req - data transfer request
173 * @req: The USB gadget request
174 * @queue: The list of requests for the endpoint this is queued for.
175 * @in_progress: Has already had size/packets written to core
176 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
178 struct s3c_hsotg_req {
179 struct usb_request req;
180 struct list_head queue;
181 unsigned char in_progress;
182 unsigned char mapped;
185 /* conversion functions */
186 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
188 return container_of(req, struct s3c_hsotg_req, req);
191 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
193 return container_of(ep, struct s3c_hsotg_ep, ep);
196 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
198 return container_of(gadget, struct s3c_hsotg, gadget);
201 static inline void __orr32(void __iomem *ptr, u32 val)
203 writel(readl(ptr) | val, ptr);
206 static inline void __bic32(void __iomem *ptr, u32 val)
208 writel(readl(ptr) & ~val, ptr);
211 /* forward decleration of functions */
212 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
215 * using_dma - return the DMA status of the driver.
216 * @hsotg: The driver state.
218 * Return true if we're using DMA.
220 * Currently, we have the DMA support code worked into everywhere
221 * that needs it, but the AMBA DMA implementation in the hardware can
222 * only DMA from 32bit aligned addresses. This means that gadgets such
223 * as the CDC Ethernet cannot work as they often pass packets which are
226 * Unfortunately the choice to use DMA or not is global to the controller
227 * and seems to be only settable when the controller is being put through
228 * a core reset. This means we either need to fix the gadgets to take
229 * account of DMA alignment, or add bounce buffers (yuerk).
231 * Until this issue is sorted out, we always return 'false'.
233 static inline bool using_dma(struct s3c_hsotg *hsotg)
235 return false; /* support is not complete */
239 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
240 * @hsotg: The device state
241 * @ints: A bitmask of the interrupts to enable
243 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
245 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
248 new_gsintmsk = gsintmsk | ints;
250 if (new_gsintmsk != gsintmsk) {
251 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
252 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
257 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
258 * @hsotg: The device state
259 * @ints: A bitmask of the interrupts to enable
261 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
263 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
266 new_gsintmsk = gsintmsk & ~ints;
268 if (new_gsintmsk != gsintmsk)
269 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
273 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
274 * @hsotg: The device state
275 * @ep: The endpoint index
276 * @dir_in: True if direction is in.
277 * @en: The enable value, true to enable
279 * Set or clear the mask for an individual endpoint's interrupt
282 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
283 unsigned int ep, unsigned int dir_in,
293 local_irq_save(flags);
294 daint = readl(hsotg->regs + S3C_DAINTMSK);
299 writel(daint, hsotg->regs + S3C_DAINTMSK);
300 local_irq_restore(flags);
304 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
305 * @hsotg: The device instance.
307 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
315 /* the ryu 2.6.24 release ahs
316 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
317 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
318 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
319 hsotg->regs + S3C_GNPTXFSIZ);
322 /* set FIFO sizes to 2048/1024 */
324 writel(2048, hsotg->regs + S3C_GRXFSIZ);
325 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
326 S3C_GNPTXFSIZ_NPTxFDep(1024),
327 hsotg->regs + S3C_GNPTXFSIZ);
329 /* arange all the rest of the TX FIFOs, as some versions of this
330 * block have overlapping default addresses. This also ensures
331 * that if the settings have been changed, then they are set to
334 /* start at the end of the GNPTXFSIZ, rounded up */
338 /* currently we allocate TX FIFOs for all possible endpoints,
339 * and assume that they are all the same size. */
341 for (ep = 0; ep <= 15; ep++) {
343 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
346 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
349 /* according to p428 of the design guide, we need to ensure that
350 * all fifos are flushed before continuing */
352 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
353 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
355 /* wait until the fifos are both flushed */
358 val = readl(hsotg->regs + S3C_GRSTCTL);
360 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
363 if (--timeout == 0) {
365 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
372 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
376 * @ep: USB endpoint to allocate request for.
377 * @flags: Allocation flags
379 * Allocate a new USB request structure appropriate for the specified endpoint
381 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
384 struct s3c_hsotg_req *req;
386 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
390 INIT_LIST_HEAD(&req->queue);
392 req->req.dma = DMA_ADDR_INVALID;
397 * is_ep_periodic - return true if the endpoint is in periodic mode.
398 * @hs_ep: The endpoint to query.
400 * Returns true if the endpoint is in periodic mode, meaning it is being
401 * used for an Interrupt or ISO transfer.
403 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
405 return hs_ep->periodic;
409 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
410 * @hsotg: The device state.
411 * @hs_ep: The endpoint for the request
412 * @hs_req: The request being processed.
414 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
415 * of a request to ensure the buffer is ready for access by the caller.
417 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
418 struct s3c_hsotg_ep *hs_ep,
419 struct s3c_hsotg_req *hs_req)
421 struct usb_request *req = &hs_req->req;
422 enum dma_data_direction dir;
424 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
426 /* ignore this if we're not moving any data */
427 if (hs_req->req.length == 0)
430 if (hs_req->mapped) {
431 /* we mapped this, so unmap and remove the dma */
433 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
435 req->dma = DMA_ADDR_INVALID;
438 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
443 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
444 * @hsotg: The controller state.
445 * @hs_ep: The endpoint we're going to write for.
446 * @hs_req: The request to write data for.
448 * This is called when the TxFIFO has some space in it to hold a new
449 * transmission and we have something to give it. The actual setup of
450 * the data size is done elsewhere, so all we have to do is to actually
453 * The return value is zero if there is more space (or nothing was done)
454 * otherwise -ENOSPC is returned if the FIFO space was used up.
456 * This routine is only needed for PIO
458 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
459 struct s3c_hsotg_ep *hs_ep,
460 struct s3c_hsotg_req *hs_req)
462 bool periodic = is_ep_periodic(hs_ep);
463 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
464 int buf_pos = hs_req->req.actual;
465 int to_write = hs_ep->size_loaded;
470 to_write -= (buf_pos - hs_ep->last_load);
472 /* if there's nothing to write, get out early */
476 if (periodic && !hsotg->dedicated_fifos) {
477 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
481 /* work out how much data was loaded so we can calculate
482 * how much data is left in the fifo. */
484 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
486 /* if shared fifo, we cannot write anything until the
487 * previous data has been completely sent.
489 if (hs_ep->fifo_load != 0) {
490 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
494 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
496 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
498 /* how much of the data has moved */
499 size_done = hs_ep->size_loaded - size_left;
501 /* how much data is left in the fifo */
502 can_write = hs_ep->fifo_load - size_done;
503 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
504 __func__, can_write);
506 can_write = hs_ep->fifo_size - can_write;
507 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
508 __func__, can_write);
510 if (can_write <= 0) {
511 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
514 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
515 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
520 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
522 "%s: no queue slots available (0x%08x)\n",
525 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
529 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
530 can_write *= 4; /* fifo size is in 32bit quantities. */
533 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
534 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
536 /* limit to 512 bytes of data, it seems at least on the non-periodic
537 * FIFO, requests of >512 cause the endpoint to get stuck with a
538 * fragment of the end of the transfer in it.
543 /* limit the write to one max-packet size worth of data, but allow
544 * the transfer to return that it did not run out of fifo space
546 if (to_write > hs_ep->ep.maxpacket) {
547 to_write = hs_ep->ep.maxpacket;
549 s3c_hsotg_en_gsint(hsotg,
550 periodic ? S3C_GINTSTS_PTxFEmp :
551 S3C_GINTSTS_NPTxFEmp);
554 /* see if we can write data */
556 if (to_write > can_write) {
557 to_write = can_write;
558 pkt_round = to_write % hs_ep->ep.maxpacket;
560 /* Not sure, but we probably shouldn't be writing partial
561 * packets into the FIFO, so round the write down to an
562 * exact number of packets.
564 * Note, we do not currently check to see if we can ever
565 * write a full packet or not to the FIFO.
569 to_write -= pkt_round;
571 /* enable correct FIFO interrupt to alert us when there
572 * is more room left. */
574 s3c_hsotg_en_gsint(hsotg,
575 periodic ? S3C_GINTSTS_PTxFEmp :
576 S3C_GINTSTS_NPTxFEmp);
579 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
580 to_write, hs_req->req.length, can_write, buf_pos);
585 hs_req->req.actual = buf_pos + to_write;
586 hs_ep->total_data += to_write;
589 hs_ep->fifo_load += to_write;
591 to_write = DIV_ROUND_UP(to_write, 4);
592 data = hs_req->req.buf + buf_pos;
594 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
596 return (to_write >= can_write) ? -ENOSPC : 0;
600 * get_ep_limit - get the maximum data legnth for this endpoint
601 * @hs_ep: The endpoint
603 * Return the maximum data that can be queued in one go on a given endpoint
604 * so that transfers that are too long can be split.
606 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
608 int index = hs_ep->index;
613 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
614 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
618 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
624 /* we made the constant loading easier above by using +1 */
628 /* constrain by packet count if maxpkts*pktsize is greater
629 * than the length register size. */
631 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
632 maxsize = maxpkt * hs_ep->ep.maxpacket;
638 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
639 * @hsotg: The controller state.
640 * @hs_ep: The endpoint to process a request for
641 * @hs_req: The request to start.
642 * @continuing: True if we are doing more for the current request.
644 * Start the given request running by setting the endpoint registers
645 * appropriately, and writing any data to the FIFOs.
647 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
648 struct s3c_hsotg_ep *hs_ep,
649 struct s3c_hsotg_req *hs_req,
652 struct usb_request *ureq = &hs_req->req;
653 int index = hs_ep->index;
654 int dir_in = hs_ep->dir_in;
664 if (hs_ep->req && !continuing) {
665 dev_err(hsotg->dev, "%s: active request\n", __func__);
668 } else if (hs_ep->req != hs_req && continuing) {
670 "%s: continue different req\n", __func__);
676 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
677 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
679 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
680 __func__, readl(hsotg->regs + epctrl_reg), index,
681 hs_ep->dir_in ? "in" : "out");
683 length = ureq->length - ureq->actual;
687 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
688 ureq->buf, length, ureq->dma,
689 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
691 maxreq = get_ep_limit(hs_ep);
692 if (length > maxreq) {
693 int round = maxreq % hs_ep->ep.maxpacket;
695 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
696 __func__, length, maxreq, round);
698 /* round down to multiple of packets */
706 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
708 packets = 1; /* send one packet if length is zero. */
710 if (dir_in && index != 0)
711 epsize = S3C_DxEPTSIZ_MC(1);
715 if (index != 0 && ureq->zero) {
716 /* test for the packets being exactly right for the
719 if (length == (packets * hs_ep->ep.maxpacket))
723 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
724 epsize |= S3C_DxEPTSIZ_XferSize(length);
726 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
727 __func__, packets, length, ureq->length, epsize, epsize_reg);
729 /* store the request as the current one we're doing */
732 /* write size / packets */
733 writel(epsize, hsotg->regs + epsize_reg);
735 ctrl = readl(hsotg->regs + epctrl_reg);
737 if (ctrl & S3C_DxEPCTL_Stall) {
738 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
740 /* not sure what we can do here, if it is EP0 then we should
741 * get this cleared once the endpoint has transmitted the
742 * STALL packet, otherwise it needs to be cleared by the
747 if (using_dma(hsotg)) {
748 unsigned int dma_reg;
750 /* write DMA address to control register, buffer already
751 * synced by s3c_hsotg_ep_queue(). */
753 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
754 writel(ureq->dma, hsotg->regs + dma_reg);
756 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
757 __func__, ureq->dma, dma_reg);
760 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
761 ctrl |= S3C_DxEPCTL_USBActEp;
762 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
764 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
765 writel(ctrl, hsotg->regs + epctrl_reg);
767 /* set these, it seems that DMA support increments past the end
768 * of the packet buffer so we need to calculate the length from
769 * this information. */
770 hs_ep->size_loaded = length;
771 hs_ep->last_load = ureq->actual;
773 if (dir_in && !using_dma(hsotg)) {
774 /* set these anyway, we may need them for non-periodic in */
775 hs_ep->fifo_load = 0;
777 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
780 /* clear the INTknTXFEmpMsk when we start request, more as a aide
781 * to debugging to see what is going on. */
783 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
784 hsotg->regs + S3C_DIEPINT(index));
786 /* Note, trying to clear the NAK here causes problems with transmit
787 * on the S3C6400 ending up with the TXFIFO becomming full. */
789 /* check ep is enabled */
790 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
792 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
793 index, readl(hsotg->regs + epctrl_reg));
795 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
796 __func__, readl(hsotg->regs + epctrl_reg));
800 * s3c_hsotg_map_dma - map the DMA memory being used for the request
801 * @hsotg: The device state.
802 * @hs_ep: The endpoint the request is on.
803 * @req: The request being processed.
805 * We've been asked to queue a request, so ensure that the memory buffer
806 * is correctly setup for DMA. If we've been passed an extant DMA address
807 * then ensure the buffer has been synced to memory. If our buffer has no
808 * DMA memory, then we map the memory and mark our request to allow us to
809 * cleanup on completion.
811 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
812 struct s3c_hsotg_ep *hs_ep,
813 struct usb_request *req)
815 enum dma_data_direction dir;
816 struct s3c_hsotg_req *hs_req = our_req(req);
818 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
820 /* if the length is zero, ignore the DMA data */
821 if (hs_req->req.length == 0)
824 if (req->dma == DMA_ADDR_INVALID) {
827 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
829 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
833 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
836 dma_unmap_single(hsotg->dev, dma, req->length, dir);
843 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
850 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
851 __func__, req->buf, req->length);
856 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
859 struct s3c_hsotg_req *hs_req = our_req(req);
860 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
861 struct s3c_hsotg *hs = hs_ep->parent;
862 unsigned long irqflags;
865 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
866 ep->name, req, req->length, req->buf, req->no_interrupt,
867 req->zero, req->short_not_ok);
869 /* initialise status of the request */
870 INIT_LIST_HEAD(&hs_req->queue);
872 req->status = -EINPROGRESS;
874 /* if we're using DMA, sync the buffers as necessary */
876 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
881 spin_lock_irqsave(&hs_ep->lock, irqflags);
883 first = list_empty(&hs_ep->queue);
884 list_add_tail(&hs_req->queue, &hs_ep->queue);
887 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
889 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
894 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
895 struct usb_request *req)
897 struct s3c_hsotg_req *hs_req = our_req(req);
903 * s3c_hsotg_complete_oursetup - setup completion callback
904 * @ep: The endpoint the request was on.
905 * @req: The request completed.
907 * Called on completion of any requests the driver itself
908 * submitted that need cleaning up.
910 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
911 struct usb_request *req)
913 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
914 struct s3c_hsotg *hsotg = hs_ep->parent;
916 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
918 s3c_hsotg_ep_free_request(ep, req);
922 * ep_from_windex - convert control wIndex value to endpoint
923 * @hsotg: The driver state.
924 * @windex: The control request wIndex field (in host order).
926 * Convert the given wIndex into a pointer to an driver endpoint
927 * structure, or return NULL if it is not a valid endpoint.
929 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
932 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
933 int dir = (windex & USB_DIR_IN) ? 1 : 0;
934 int idx = windex & 0x7F;
939 if (idx > S3C_HSOTG_EPS)
942 if (idx && ep->dir_in != dir)
949 * s3c_hsotg_send_reply - send reply to control request
950 * @hsotg: The device state
952 * @buff: Buffer for request
953 * @length: Length of reply.
955 * Create a request and queue it on the given endpoint. This is useful as
956 * an internal method of sending replies to certain control requests, etc.
958 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
959 struct s3c_hsotg_ep *ep,
963 struct usb_request *req;
966 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
968 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
969 hsotg->ep0_reply = req;
971 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
975 req->buf = hsotg->ep0_buff;
976 req->length = length;
977 req->zero = 1; /* always do zero-length final transfer */
978 req->complete = s3c_hsotg_complete_oursetup;
981 memcpy(req->buf, buff, length);
985 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
987 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
995 * s3c_hsotg_process_req_status - process request GET_STATUS
996 * @hsotg: The device state
997 * @ctrl: USB control request
999 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1000 struct usb_ctrlrequest *ctrl)
1002 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1003 struct s3c_hsotg_ep *ep;
1007 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1010 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1014 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1015 case USB_RECIP_DEVICE:
1016 reply = cpu_to_le16(0); /* bit 0 => self powered,
1017 * bit 1 => remote wakeup */
1020 case USB_RECIP_INTERFACE:
1021 /* currently, the data result should be zero */
1022 reply = cpu_to_le16(0);
1025 case USB_RECIP_ENDPOINT:
1026 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1030 reply = cpu_to_le16(ep->halted ? 1 : 0);
1037 if (le16_to_cpu(ctrl->wLength) != 2)
1040 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1042 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1049 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1052 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1053 * @hsotg: The device state
1054 * @ctrl: USB control request
1056 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1057 struct usb_ctrlrequest *ctrl)
1059 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1060 struct s3c_hsotg_ep *ep;
1062 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1063 __func__, set ? "SET" : "CLEAR");
1065 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1066 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1068 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1069 __func__, le16_to_cpu(ctrl->wIndex));
1073 switch (le16_to_cpu(ctrl->wValue)) {
1074 case USB_ENDPOINT_HALT:
1075 s3c_hsotg_ep_sethalt(&ep->ep, set);
1082 return -ENOENT; /* currently only deal with endpoint */
1088 * s3c_hsotg_process_control - process a control request
1089 * @hsotg: The device state
1090 * @ctrl: The control request received
1092 * The controller has received the SETUP phase of a control request, and
1093 * needs to work out what to do next (and whether to pass it on to the
1096 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1097 struct usb_ctrlrequest *ctrl)
1099 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1105 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1106 ctrl->bRequest, ctrl->bRequestType,
1107 ctrl->wValue, ctrl->wLength);
1109 /* record the direction of the request, for later use when enquing
1110 * packets onto EP0. */
1112 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1113 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1115 /* if we've no data with this request, then the last part of the
1116 * transaction is going to implicitly be IN. */
1117 if (ctrl->wLength == 0)
1120 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1121 switch (ctrl->bRequest) {
1122 case USB_REQ_SET_ADDRESS:
1123 dcfg = readl(hsotg->regs + S3C_DCFG);
1124 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1125 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1126 writel(dcfg, hsotg->regs + S3C_DCFG);
1128 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1130 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1133 case USB_REQ_GET_STATUS:
1134 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1137 case USB_REQ_CLEAR_FEATURE:
1138 case USB_REQ_SET_FEATURE:
1139 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1144 /* as a fallback, try delivering it to the driver to deal with */
1146 if (ret == 0 && hsotg->driver) {
1147 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1149 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1154 /* need to generate zlp in reply or take data */
1155 /* todo - deal with any data we might be sent? */
1156 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1160 /* the request is either unhandlable, or is not formatted correctly
1161 * so respond with a STALL for the status stage to indicate failure.
1168 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1169 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1171 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1172 * taken effect, so no need to clear later. */
1174 ctrl = readl(hsotg->regs + reg);
1175 ctrl |= S3C_DxEPCTL_Stall;
1176 ctrl |= S3C_DxEPCTL_CNAK;
1177 writel(ctrl, hsotg->regs + reg);
1180 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1181 ctrl, reg, readl(hsotg->regs + reg));
1183 /* don't belive we need to anything more to get the EP
1184 * to reply with a STALL packet */
1188 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1191 * s3c_hsotg_complete_setup - completion of a setup transfer
1192 * @ep: The endpoint the request was on.
1193 * @req: The request completed.
1195 * Called on completion of any requests the driver itself submitted for
1198 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1199 struct usb_request *req)
1201 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1202 struct s3c_hsotg *hsotg = hs_ep->parent;
1204 if (req->status < 0) {
1205 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1209 if (req->actual == 0)
1210 s3c_hsotg_enqueue_setup(hsotg);
1212 s3c_hsotg_process_control(hsotg, req->buf);
1216 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1217 * @hsotg: The device state.
1219 * Enqueue a request on EP0 if necessary to received any SETUP packets
1220 * received from the host.
1222 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1224 struct usb_request *req = hsotg->ctrl_req;
1225 struct s3c_hsotg_req *hs_req = our_req(req);
1228 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1232 req->buf = hsotg->ctrl_buff;
1233 req->complete = s3c_hsotg_complete_setup;
1235 if (!list_empty(&hs_req->queue)) {
1236 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1240 hsotg->eps[0].dir_in = 0;
1242 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1244 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1245 /* Don't think there's much we can do other than watch the
1251 * get_ep_head - return the first request on the endpoint
1252 * @hs_ep: The controller endpoint to get
1254 * Get the first request on the endpoint.
1256 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1258 if (list_empty(&hs_ep->queue))
1261 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1265 * s3c_hsotg_complete_request - complete a request given to us
1266 * @hsotg: The device state.
1267 * @hs_ep: The endpoint the request was on.
1268 * @hs_req: The request to complete.
1269 * @result: The result code (0 => Ok, otherwise errno)
1271 * The given request has finished, so call the necessary completion
1272 * if it has one and then look to see if we can start a new request
1275 * Note, expects the ep to already be locked as appropriate.
1277 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1278 struct s3c_hsotg_ep *hs_ep,
1279 struct s3c_hsotg_req *hs_req,
1285 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1289 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1290 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1292 /* only replace the status if we've not already set an error
1293 * from a previous transaction */
1295 if (hs_req->req.status == -EINPROGRESS)
1296 hs_req->req.status = result;
1299 list_del_init(&hs_req->queue);
1301 if (using_dma(hsotg))
1302 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1304 /* call the complete request with the locks off, just in case the
1305 * request tries to queue more work for this endpoint. */
1307 if (hs_req->req.complete) {
1308 spin_unlock(&hs_ep->lock);
1309 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1310 spin_lock(&hs_ep->lock);
1313 /* Look to see if there is anything else to do. Note, the completion
1314 * of the previous request may have caused a new request to be started
1315 * so be careful when doing this. */
1317 if (!hs_ep->req && result >= 0) {
1318 restart = !list_empty(&hs_ep->queue);
1320 hs_req = get_ep_head(hs_ep);
1321 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1327 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1328 * @hsotg: The device state.
1329 * @hs_ep: The endpoint the request was on.
1330 * @hs_req: The request to complete.
1331 * @result: The result code (0 => Ok, otherwise errno)
1333 * See s3c_hsotg_complete_request(), but called with the endpoint's
1336 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1337 struct s3c_hsotg_ep *hs_ep,
1338 struct s3c_hsotg_req *hs_req,
1341 unsigned long flags;
1343 spin_lock_irqsave(&hs_ep->lock, flags);
1344 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1345 spin_unlock_irqrestore(&hs_ep->lock, flags);
1349 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1350 * @hsotg: The device state.
1351 * @ep_idx: The endpoint index for the data
1352 * @size: The size of data in the fifo, in bytes
1354 * The FIFO status shows there is data to read from the FIFO for a given
1355 * endpoint, so sort out whether we need to read the data into a request
1356 * that has been made for that endpoint.
1358 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1360 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1361 struct s3c_hsotg_req *hs_req = hs_ep->req;
1362 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1368 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1371 dev_warn(hsotg->dev,
1372 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1373 __func__, size, ep_idx, epctl);
1375 /* dump the data from the FIFO, we've nothing we can do */
1376 for (ptr = 0; ptr < size; ptr += 4)
1382 spin_lock(&hs_ep->lock);
1385 read_ptr = hs_req->req.actual;
1386 max_req = hs_req->req.length - read_ptr;
1388 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1389 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1391 if (to_read > max_req) {
1392 /* more data appeared than we where willing
1393 * to deal with in this request.
1396 /* currently we don't deal this */
1400 hs_ep->total_data += to_read;
1401 hs_req->req.actual += to_read;
1402 to_read = DIV_ROUND_UP(to_read, 4);
1404 /* note, we might over-write the buffer end by 3 bytes depending on
1405 * alignment of the data. */
1406 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1408 spin_unlock(&hs_ep->lock);
1412 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1413 * @hsotg: The device instance
1414 * @req: The request currently on this endpoint
1416 * Generate a zero-length IN packet request for terminating a SETUP
1419 * Note, since we don't write any data to the TxFIFO, then it is
1420 * currently belived that we do not need to wait for any space in
1423 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1424 struct s3c_hsotg_req *req)
1429 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1433 if (req->req.length == 0) {
1434 hsotg->eps[0].sent_zlp = 1;
1435 s3c_hsotg_enqueue_setup(hsotg);
1439 hsotg->eps[0].dir_in = 1;
1440 hsotg->eps[0].sent_zlp = 1;
1442 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1444 /* issue a zero-sized packet to terminate this */
1445 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1446 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1448 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1449 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1450 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1451 ctrl |= S3C_DxEPCTL_USBActEp;
1452 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1456 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1457 * @hsotg: The device instance
1458 * @epnum: The endpoint received from
1459 * @was_setup: Set if processing a SetupDone event.
1461 * The RXFIFO has delivered an OutDone event, which means that the data
1462 * transfer for an OUT endpoint has been completed, either by a short
1463 * packet or by the finish of a transfer.
1465 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1466 int epnum, bool was_setup)
1468 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1469 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1470 struct s3c_hsotg_req *hs_req = hs_ep->req;
1471 struct usb_request *req = &hs_req->req;
1472 unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1476 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1480 if (using_dma(hsotg)) {
1483 /* Calculate the size of the transfer by checking how much
1484 * is left in the endpoint size register and then working it
1485 * out from the amount we loaded for the transfer.
1487 * We need to do this as DMA pointers are always 32bit aligned
1488 * so may overshoot/undershoot the transfer.
1491 size_done = hs_ep->size_loaded - size_left;
1492 size_done += hs_ep->last_load;
1494 req->actual = size_done;
1497 /* if there is more request to do, schedule new transfer */
1498 if (req->actual < req->length && size_left == 0) {
1499 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1503 if (req->actual < req->length && req->short_not_ok) {
1504 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1505 __func__, req->actual, req->length);
1507 /* todo - what should we return here? there's no one else
1508 * even bothering to check the status. */
1512 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1513 s3c_hsotg_send_zlp(hsotg, hs_req);
1516 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1520 * s3c_hsotg_read_frameno - read current frame number
1521 * @hsotg: The device instance
1523 * Return the current frame number
1525 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1529 dsts = readl(hsotg->regs + S3C_DSTS);
1530 dsts &= S3C_DSTS_SOFFN_MASK;
1531 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1537 * s3c_hsotg_handle_rx - RX FIFO has data
1538 * @hsotg: The device instance
1540 * The IRQ handler has detected that the RX FIFO has some data in it
1541 * that requires processing, so find out what is in there and do the
1544 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1545 * chunks, so if you have x packets received on an endpoint you'll get x
1546 * FIFO events delivered, each with a packet's worth of data in it.
1548 * When using DMA, we should not be processing events from the RXFIFO
1549 * as the actual data should be sent to the memory directly and we turn
1550 * on the completion interrupts to get notifications of transfer completion.
1552 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1554 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1555 u32 epnum, status, size;
1557 WARN_ON(using_dma(hsotg));
1559 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1560 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1562 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1563 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1566 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1567 __func__, grxstsr, size, epnum);
1569 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1571 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1572 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1573 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1576 case __status(S3C_GRXSTS_PktSts_OutDone):
1577 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1578 s3c_hsotg_read_frameno(hsotg));
1580 if (!using_dma(hsotg))
1581 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1584 case __status(S3C_GRXSTS_PktSts_SetupDone):
1586 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1587 s3c_hsotg_read_frameno(hsotg),
1588 readl(hsotg->regs + S3C_DOEPCTL(0)));
1590 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1593 case __status(S3C_GRXSTS_PktSts_OutRX):
1594 s3c_hsotg_rx_data(hsotg, epnum, size);
1597 case __status(S3C_GRXSTS_PktSts_SetupRX):
1599 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1600 s3c_hsotg_read_frameno(hsotg),
1601 readl(hsotg->regs + S3C_DOEPCTL(0)));
1603 s3c_hsotg_rx_data(hsotg, epnum, size);
1607 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1610 s3c_hsotg_dump(hsotg);
1616 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1617 * @mps: The maximum packet size in bytes.
1619 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1623 return S3C_D0EPCTL_MPS_64;
1625 return S3C_D0EPCTL_MPS_32;
1627 return S3C_D0EPCTL_MPS_16;
1629 return S3C_D0EPCTL_MPS_8;
1632 /* bad max packet size, warn and return invalid result */
1638 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1639 * @hsotg: The driver state.
1640 * @ep: The index number of the endpoint
1641 * @mps: The maximum packet size in bytes
1643 * Configure the maximum packet size for the given endpoint, updating
1644 * the hardware control registers to reflect this.
1646 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1647 unsigned int ep, unsigned int mps)
1649 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1650 void __iomem *regs = hsotg->regs;
1655 /* EP0 is a special case */
1656 mpsval = s3c_hsotg_ep0_mps(mps);
1660 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1666 hs_ep->ep.maxpacket = mps;
1668 /* update both the in and out endpoint controldir_ registers, even
1669 * if one of the directions may not be in use. */
1671 reg = readl(regs + S3C_DIEPCTL(ep));
1672 reg &= ~S3C_DxEPCTL_MPS_MASK;
1674 writel(reg, regs + S3C_DIEPCTL(ep));
1676 reg = readl(regs + S3C_DOEPCTL(ep));
1677 reg &= ~S3C_DxEPCTL_MPS_MASK;
1679 writel(reg, regs + S3C_DOEPCTL(ep));
1684 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1689 * s3c_hsotg_trytx - check to see if anything needs transmitting
1690 * @hsotg: The driver state
1691 * @hs_ep: The driver endpoint to check.
1693 * Check to see if there is a request that has data to send, and if so
1694 * make an attempt to write data into the FIFO.
1696 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1697 struct s3c_hsotg_ep *hs_ep)
1699 struct s3c_hsotg_req *hs_req = hs_ep->req;
1701 if (!hs_ep->dir_in || !hs_req)
1704 if (hs_req->req.actual < hs_req->req.length) {
1705 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1707 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1714 * s3c_hsotg_complete_in - complete IN transfer
1715 * @hsotg: The device state.
1716 * @hs_ep: The endpoint that has just completed.
1718 * An IN transfer has been completed, update the transfer's state and then
1719 * call the relevant completion routines.
1721 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1722 struct s3c_hsotg_ep *hs_ep)
1724 struct s3c_hsotg_req *hs_req = hs_ep->req;
1725 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1726 int size_left, size_done;
1729 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1733 /* Calculate the size of the transfer by checking how much is left
1734 * in the endpoint size register and then working it out from
1735 * the amount we loaded for the transfer.
1737 * We do this even for DMA, as the transfer may have incremented
1738 * past the end of the buffer (DMA transfers are always 32bit
1742 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1744 size_done = hs_ep->size_loaded - size_left;
1745 size_done += hs_ep->last_load;
1747 if (hs_req->req.actual != size_done)
1748 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1749 __func__, hs_req->req.actual, size_done);
1751 hs_req->req.actual = size_done;
1753 /* if we did all of the transfer, and there is more data left
1754 * around, then try restarting the rest of the request */
1756 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1757 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1758 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1760 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1764 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1765 * @hsotg: The driver state
1766 * @idx: The index for the endpoint (0..15)
1767 * @dir_in: Set if this is an IN endpoint
1769 * Process and clear any interrupt pending for an individual endpoint
1771 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1774 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1775 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1776 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1777 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1781 ints = readl(hsotg->regs + epint_reg);
1783 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1784 __func__, idx, dir_in ? "in" : "out", ints);
1786 if (ints & S3C_DxEPINT_XferCompl) {
1788 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1789 __func__, readl(hsotg->regs + epctl_reg),
1790 readl(hsotg->regs + epsiz_reg));
1792 /* we get OutDone from the FIFO, so we only need to look
1793 * at completing IN requests here */
1795 s3c_hsotg_complete_in(hsotg, hs_ep);
1797 if (idx == 0 && !hs_ep->req)
1798 s3c_hsotg_enqueue_setup(hsotg);
1799 } else if (using_dma(hsotg)) {
1800 /* We're using DMA, we need to fire an OutDone here
1801 * as we ignore the RXFIFO. */
1803 s3c_hsotg_handle_outdone(hsotg, idx, false);
1806 clear |= S3C_DxEPINT_XferCompl;
1809 if (ints & S3C_DxEPINT_EPDisbld) {
1810 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1811 clear |= S3C_DxEPINT_EPDisbld;
1814 if (ints & S3C_DxEPINT_AHBErr) {
1815 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1816 clear |= S3C_DxEPINT_AHBErr;
1819 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1820 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1822 if (using_dma(hsotg) && idx == 0) {
1823 /* this is the notification we've received a
1824 * setup packet. In non-DMA mode we'd get this
1825 * from the RXFIFO, instead we need to process
1826 * the setup here. */
1831 s3c_hsotg_handle_outdone(hsotg, 0, true);
1834 clear |= S3C_DxEPINT_Setup;
1837 if (ints & S3C_DxEPINT_Back2BackSetup) {
1838 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1839 clear |= S3C_DxEPINT_Back2BackSetup;
1843 /* not sure if this is important, but we'll clear it anyway
1845 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1846 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1848 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1851 /* this probably means something bad is happening */
1852 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1853 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1855 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1858 /* FIFO has space or is empty (see GAHBCFG) */
1859 if (hsotg->dedicated_fifos &&
1860 ints & S3C_DIEPMSK_TxFIFOEmpty) {
1861 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1863 s3c_hsotg_trytx(hsotg, hs_ep);
1864 clear |= S3C_DIEPMSK_TxFIFOEmpty;
1868 writel(clear, hsotg->regs + epint_reg);
1872 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1873 * @hsotg: The device state.
1875 * Handle updating the device settings after the enumeration phase has
1878 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1880 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1881 int ep0_mps = 0, ep_mps;
1883 /* This should signal the finish of the enumeration phase
1884 * of the USB handshaking, so we should now know what rate
1885 * we connected at. */
1887 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1889 /* note, since we're limited by the size of transfer on EP0, and
1890 * it seems IN transfers must be a even number of packets we do
1891 * not advertise a 64byte MPS on EP0. */
1893 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1894 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1895 case S3C_DSTS_EnumSpd_FS:
1896 case S3C_DSTS_EnumSpd_FS48:
1897 hsotg->gadget.speed = USB_SPEED_FULL;
1898 dev_info(hsotg->dev, "new device is full-speed\n");
1900 ep0_mps = EP0_MPS_LIMIT;
1904 case S3C_DSTS_EnumSpd_HS:
1905 dev_info(hsotg->dev, "new device is high-speed\n");
1906 hsotg->gadget.speed = USB_SPEED_HIGH;
1908 ep0_mps = EP0_MPS_LIMIT;
1912 case S3C_DSTS_EnumSpd_LS:
1913 hsotg->gadget.speed = USB_SPEED_LOW;
1914 dev_info(hsotg->dev, "new device is low-speed\n");
1916 /* note, we don't actually support LS in this driver at the
1917 * moment, and the documentation seems to imply that it isn't
1918 * supported by the PHYs on some of the devices.
1923 /* we should now know the maximum packet size for an
1924 * endpoint, so set the endpoints to a default value. */
1928 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1929 for (i = 1; i < S3C_HSOTG_EPS; i++)
1930 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1933 /* ensure after enumeration our EP0 is active */
1935 s3c_hsotg_enqueue_setup(hsotg);
1937 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1938 readl(hsotg->regs + S3C_DIEPCTL0),
1939 readl(hsotg->regs + S3C_DOEPCTL0));
1943 * kill_all_requests - remove all requests from the endpoint's queue
1944 * @hsotg: The device state.
1945 * @ep: The endpoint the requests may be on.
1946 * @result: The result code to use.
1947 * @force: Force removal of any current requests
1949 * Go through the requests on the given endpoint and mark them
1950 * completed with the given result code.
1952 static void kill_all_requests(struct s3c_hsotg *hsotg,
1953 struct s3c_hsotg_ep *ep,
1954 int result, bool force)
1956 struct s3c_hsotg_req *req, *treq;
1957 unsigned long flags;
1959 spin_lock_irqsave(&ep->lock, flags);
1961 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1962 /* currently, we can't do much about an already
1963 * running request on an in endpoint */
1965 if (ep->req == req && ep->dir_in && !force)
1968 s3c_hsotg_complete_request(hsotg, ep, req,
1972 spin_unlock_irqrestore(&ep->lock, flags);
1975 #define call_gadget(_hs, _entry) \
1976 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1977 (_hs)->driver && (_hs)->driver->_entry) \
1978 (_hs)->driver->_entry(&(_hs)->gadget);
1981 * s3c_hsotg_disconnect_irq - disconnect irq service
1982 * @hsotg: The device state.
1984 * A disconnect IRQ has been received, meaning that the host has
1985 * lost contact with the bus. Remove all current transactions
1986 * and signal the gadget driver that this has happened.
1988 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1992 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1993 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1995 call_gadget(hsotg, disconnect);
1999 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2000 * @hsotg: The device state:
2001 * @periodic: True if this is a periodic FIFO interrupt
2003 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2005 struct s3c_hsotg_ep *ep;
2008 /* look through for any more data to transmit */
2010 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
2011 ep = &hsotg->eps[epno];
2016 if ((periodic && !ep->periodic) ||
2017 (!periodic && ep->periodic))
2020 ret = s3c_hsotg_trytx(hsotg, ep);
2026 static struct s3c_hsotg *our_hsotg;
2028 /* IRQ flags which will trigger a retry around the IRQ loop */
2029 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2030 S3C_GINTSTS_PTxFEmp | \
2034 * s3c_hsotg_irq - handle device interrupt
2035 * @irq: The IRQ number triggered
2036 * @pw: The pw value when registered the handler.
2038 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2040 struct s3c_hsotg *hsotg = pw;
2041 int retry_count = 8;
2046 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2047 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2049 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2050 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2054 if (gintsts & S3C_GINTSTS_OTGInt) {
2055 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2057 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2059 writel(otgint, hsotg->regs + S3C_GOTGINT);
2060 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
2063 if (gintsts & S3C_GINTSTS_DisconnInt) {
2064 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2065 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2067 s3c_hsotg_disconnect_irq(hsotg);
2070 if (gintsts & S3C_GINTSTS_SessReqInt) {
2071 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2072 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2075 if (gintsts & S3C_GINTSTS_EnumDone) {
2076 s3c_hsotg_irq_enumdone(hsotg);
2077 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2080 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2081 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2082 readl(hsotg->regs + S3C_DSTS),
2083 readl(hsotg->regs + S3C_GOTGCTL));
2085 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2088 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2089 u32 daint = readl(hsotg->regs + S3C_DAINT);
2090 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2091 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2094 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2096 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2098 s3c_hsotg_epint(hsotg, ep, 0);
2101 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2103 s3c_hsotg_epint(hsotg, ep, 1);
2106 writel(daint, hsotg->regs + S3C_DAINT);
2107 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2108 hsotg->regs + S3C_GINTSTS);
2111 if (gintsts & S3C_GINTSTS_USBRst) {
2112 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2113 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2114 readl(hsotg->regs + S3C_GNPTXSTS));
2116 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2118 /* it seems after a reset we can end up with a situation
2119 * where the TXFIFO still has data in it... the docs
2120 * suggest resetting all the fifos, so use the init_fifo
2121 * code to relayout and flush the fifos.
2124 s3c_hsotg_init_fifo(hsotg);
2126 s3c_hsotg_enqueue_setup(hsotg);
2128 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2131 /* check both FIFOs */
2133 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2134 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2136 /* Disable the interrupt to stop it happening again
2137 * unless one of these endpoint routines decides that
2138 * it needs re-enabling */
2140 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2141 s3c_hsotg_irq_fifoempty(hsotg, false);
2143 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2146 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2147 dev_dbg(hsotg->dev, "PTxFEmp\n");
2149 /* See note in S3C_GINTSTS_NPTxFEmp */
2151 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2152 s3c_hsotg_irq_fifoempty(hsotg, true);
2154 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2157 if (gintsts & S3C_GINTSTS_RxFLvl) {
2158 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2159 * we need to retry s3c_hsotg_handle_rx if this is still
2162 s3c_hsotg_handle_rx(hsotg);
2163 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2166 if (gintsts & S3C_GINTSTS_ModeMis) {
2167 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2168 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2171 if (gintsts & S3C_GINTSTS_USBSusp) {
2172 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2173 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2175 call_gadget(hsotg, suspend);
2178 if (gintsts & S3C_GINTSTS_WkUpInt) {
2179 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2180 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2182 call_gadget(hsotg, resume);
2185 if (gintsts & S3C_GINTSTS_ErlySusp) {
2186 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2187 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2190 /* these next two seem to crop-up occasionally causing the core
2191 * to shutdown the USB transfer, so try clearing them and logging
2194 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2195 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2197 s3c_hsotg_dump(hsotg);
2199 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2200 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2203 if (gintsts & S3C_GINTSTS_GINNakEff) {
2204 dev_info(hsotg->dev, "GINNakEff triggered\n");
2206 s3c_hsotg_dump(hsotg);
2208 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2209 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2212 /* if we've had fifo events, we should try and go around the
2213 * loop again to see if there's any point in returning yet. */
2215 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2222 * s3c_hsotg_ep_enable - enable the given endpoint
2223 * @ep: The USB endpint to configure
2224 * @desc: The USB endpoint descriptor to configure with.
2226 * This is called from the USB gadget code's usb_ep_enable().
2228 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2229 const struct usb_endpoint_descriptor *desc)
2231 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2232 struct s3c_hsotg *hsotg = hs_ep->parent;
2233 unsigned long flags;
2234 int index = hs_ep->index;
2242 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2243 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2244 desc->wMaxPacketSize, desc->bInterval);
2246 /* not to be called for EP0 */
2247 WARN_ON(index == 0);
2249 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2250 if (dir_in != hs_ep->dir_in) {
2251 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2255 mps = le16_to_cpu(desc->wMaxPacketSize);
2257 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2259 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2260 epctrl = readl(hsotg->regs + epctrl_reg);
2262 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2263 __func__, epctrl, epctrl_reg);
2265 spin_lock_irqsave(&hs_ep->lock, flags);
2267 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2268 epctrl |= S3C_DxEPCTL_MPS(mps);
2270 /* mark the endpoint as active, otherwise the core may ignore
2271 * transactions entirely for this endpoint */
2272 epctrl |= S3C_DxEPCTL_USBActEp;
2274 /* set the NAK status on the endpoint, otherwise we might try and
2275 * do something with data that we've yet got a request to process
2276 * since the RXFIFO will take data for an endpoint even if the
2277 * size register hasn't been set.
2280 epctrl |= S3C_DxEPCTL_SNAK;
2282 /* update the endpoint state */
2283 hs_ep->ep.maxpacket = mps;
2285 /* default, set to non-periodic */
2286 hs_ep->periodic = 0;
2288 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2289 case USB_ENDPOINT_XFER_ISOC:
2290 dev_err(hsotg->dev, "no current ISOC support\n");
2294 case USB_ENDPOINT_XFER_BULK:
2295 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2298 case USB_ENDPOINT_XFER_INT:
2300 /* Allocate our TxFNum by simply using the index
2301 * of the endpoint for the moment. We could do
2302 * something better if the host indicates how
2303 * many FIFOs we are expecting to use. */
2305 hs_ep->periodic = 1;
2306 epctrl |= S3C_DxEPCTL_TxFNum(index);
2309 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2312 case USB_ENDPOINT_XFER_CONTROL:
2313 epctrl |= S3C_DxEPCTL_EPType_Control;
2317 /* if the hardware has dedicated fifos, we must give each IN EP
2318 * a unique tx-fifo even if it is non-periodic.
2320 if (dir_in && hsotg->dedicated_fifos)
2321 epctrl |= S3C_DxEPCTL_TxFNum(index);
2323 /* for non control endpoints, set PID to D0 */
2325 epctrl |= S3C_DxEPCTL_SetD0PID;
2327 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2330 writel(epctrl, hsotg->regs + epctrl_reg);
2331 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2332 __func__, readl(hsotg->regs + epctrl_reg));
2334 /* enable the endpoint interrupt */
2335 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2338 spin_unlock_irqrestore(&hs_ep->lock, flags);
2342 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2344 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2345 struct s3c_hsotg *hsotg = hs_ep->parent;
2346 int dir_in = hs_ep->dir_in;
2347 int index = hs_ep->index;
2348 unsigned long flags;
2352 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2354 if (ep == &hsotg->eps[0].ep) {
2355 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2359 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2361 /* terminate all requests with shutdown */
2362 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2364 spin_lock_irqsave(&hs_ep->lock, flags);
2366 ctrl = readl(hsotg->regs + epctrl_reg);
2367 ctrl &= ~S3C_DxEPCTL_EPEna;
2368 ctrl &= ~S3C_DxEPCTL_USBActEp;
2369 ctrl |= S3C_DxEPCTL_SNAK;
2371 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2372 writel(ctrl, hsotg->regs + epctrl_reg);
2374 /* disable endpoint interrupts */
2375 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2377 spin_unlock_irqrestore(&hs_ep->lock, flags);
2382 * on_list - check request is on the given endpoint
2383 * @ep: The endpoint to check.
2384 * @test: The request to test if it is on the endpoint.
2386 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2388 struct s3c_hsotg_req *req, *treq;
2390 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2398 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2400 struct s3c_hsotg_req *hs_req = our_req(req);
2401 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2402 struct s3c_hsotg *hs = hs_ep->parent;
2403 unsigned long flags;
2405 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2407 if (hs_req == hs_ep->req) {
2408 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2409 return -EINPROGRESS;
2412 spin_lock_irqsave(&hs_ep->lock, flags);
2414 if (!on_list(hs_ep, hs_req)) {
2415 spin_unlock_irqrestore(&hs_ep->lock, flags);
2419 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2420 spin_unlock_irqrestore(&hs_ep->lock, flags);
2425 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2427 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2428 struct s3c_hsotg *hs = hs_ep->parent;
2429 int index = hs_ep->index;
2430 unsigned long irqflags;
2434 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2436 spin_lock_irqsave(&hs_ep->lock, irqflags);
2438 /* write both IN and OUT control registers */
2440 epreg = S3C_DIEPCTL(index);
2441 epctl = readl(hs->regs + epreg);
2444 epctl |= S3C_DxEPCTL_Stall;
2446 epctl &= ~S3C_DxEPCTL_Stall;
2448 writel(epctl, hs->regs + epreg);
2450 epreg = S3C_DOEPCTL(index);
2451 epctl = readl(hs->regs + epreg);
2454 epctl |= S3C_DxEPCTL_Stall;
2456 epctl &= ~S3C_DxEPCTL_Stall;
2458 writel(epctl, hs->regs + epreg);
2460 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2465 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2466 .enable = s3c_hsotg_ep_enable,
2467 .disable = s3c_hsotg_ep_disable,
2468 .alloc_request = s3c_hsotg_ep_alloc_request,
2469 .free_request = s3c_hsotg_ep_free_request,
2470 .queue = s3c_hsotg_ep_queue,
2471 .dequeue = s3c_hsotg_ep_dequeue,
2472 .set_halt = s3c_hsotg_ep_sethalt,
2473 /* note, don't belive we have any call for the fifo routines */
2477 * s3c_hsotg_corereset - issue softreset to the core
2478 * @hsotg: The device state
2480 * Issue a soft reset to the core, and await the core finishing it.
2482 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2487 dev_dbg(hsotg->dev, "resetting core\n");
2489 /* issue soft reset */
2490 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2494 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2495 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2497 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2498 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2505 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2507 if (timeout-- < 0) {
2508 dev_info(hsotg->dev,
2509 "%s: reset failed, GRSTCTL=%08x\n",
2514 if (grstctl & S3C_GRSTCTL_CSftRst)
2517 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2520 break; /* reset done */
2523 dev_dbg(hsotg->dev, "reset successful\n");
2527 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2529 struct s3c_hsotg *hsotg = our_hsotg;
2533 printk(KERN_ERR "%s: called with no device\n", __func__);
2538 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2542 if (driver->speed != USB_SPEED_HIGH &&
2543 driver->speed != USB_SPEED_FULL) {
2544 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2547 if (!driver->bind || !driver->setup) {
2548 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2552 WARN_ON(hsotg->driver);
2554 driver->driver.bus = NULL;
2555 hsotg->driver = driver;
2556 hsotg->gadget.dev.driver = &driver->driver;
2557 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2558 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2560 ret = device_add(&hsotg->gadget.dev);
2562 dev_err(hsotg->dev, "failed to register gadget device\n");
2566 ret = driver->bind(&hsotg->gadget);
2568 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2570 hsotg->gadget.dev.driver = NULL;
2571 hsotg->driver = NULL;
2575 /* we must now enable ep0 ready for host detection and then
2576 * set configuration. */
2578 s3c_hsotg_corereset(hsotg);
2580 /* set the PLL on, remove the HNP/SRP and set the PHY */
2581 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2582 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2584 /* looks like soft-reset changes state of FIFOs */
2585 s3c_hsotg_init_fifo(hsotg);
2587 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2589 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2591 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2592 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2593 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2594 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2595 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2596 S3C_GINTSTS_ErlySusp,
2597 hsotg->regs + S3C_GINTMSK);
2599 if (using_dma(hsotg))
2600 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2601 S3C_GAHBCFG_HBstLen_Incr4,
2602 hsotg->regs + S3C_GAHBCFG);
2604 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2606 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2607 * up being flooded with interrupts if the host is polling the
2608 * endpoint to try and read data. */
2610 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2611 S3C_DIEPMSK_INTknEPMisMsk |
2612 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2613 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2614 hsotg->regs + S3C_DIEPMSK);
2616 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2617 * DMA mode we may need this. */
2618 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2619 S3C_DOEPMSK_EPDisbldMsk |
2620 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2621 S3C_DIEPMSK_TimeOUTMsk) : 0),
2622 hsotg->regs + S3C_DOEPMSK);
2624 writel(0, hsotg->regs + S3C_DAINTMSK);
2626 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2627 readl(hsotg->regs + S3C_DIEPCTL0),
2628 readl(hsotg->regs + S3C_DOEPCTL0));
2630 /* enable in and out endpoint interrupts */
2631 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2633 /* Enable the RXFIFO when in slave mode, as this is how we collect
2634 * the data. In DMA mode, we get events from the FIFO but also
2635 * things we cannot process, so do not use it. */
2636 if (!using_dma(hsotg))
2637 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2639 /* Enable interrupts for EP0 in and out */
2640 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2641 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2643 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2644 udelay(10); /* see openiboot */
2645 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2647 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2649 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2650 writing to the EPCTL register.. */
2652 /* set to read 1 8byte packet */
2653 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2654 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2656 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2657 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2658 S3C_DxEPCTL_USBActEp,
2659 hsotg->regs + S3C_DOEPCTL0);
2661 /* enable, but don't activate EP0in */
2662 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2663 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2665 s3c_hsotg_enqueue_setup(hsotg);
2667 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2668 readl(hsotg->regs + S3C_DIEPCTL0),
2669 readl(hsotg->regs + S3C_DOEPCTL0));
2671 /* clear global NAKs */
2672 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2673 hsotg->regs + S3C_DCTL);
2675 /* must be at-least 3ms to allow bus to see disconnect */
2678 /* remove the soft-disconnect and let's go */
2679 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2681 /* report to the user, and return */
2683 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2687 hsotg->driver = NULL;
2688 hsotg->gadget.dev.driver = NULL;
2691 EXPORT_SYMBOL(usb_gadget_register_driver);
2693 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2695 struct s3c_hsotg *hsotg = our_hsotg;
2701 if (!driver || driver != hsotg->driver || !driver->unbind)
2704 /* all endpoints should be shutdown */
2705 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2706 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2708 call_gadget(hsotg, disconnect);
2710 driver->unbind(&hsotg->gadget);
2711 hsotg->driver = NULL;
2712 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2714 device_del(&hsotg->gadget.dev);
2716 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2717 driver->driver.name);
2721 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2723 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2725 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2728 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2729 .get_frame = s3c_hsotg_gadget_getframe,
2733 * s3c_hsotg_initep - initialise a single endpoint
2734 * @hsotg: The device state.
2735 * @hs_ep: The endpoint to be initialised.
2736 * @epnum: The endpoint number
2738 * Initialise the given endpoint (as part of the probe and device state
2739 * creation) to give to the gadget driver. Setup the endpoint name, any
2740 * direction information and other state that may be required.
2742 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2743 struct s3c_hsotg_ep *hs_ep,
2751 else if ((epnum % 2) == 0) {
2758 hs_ep->index = epnum;
2760 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2762 INIT_LIST_HEAD(&hs_ep->queue);
2763 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2765 spin_lock_init(&hs_ep->lock);
2767 /* add to the list of endpoints known by the gadget driver */
2769 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2771 hs_ep->parent = hsotg;
2772 hs_ep->ep.name = hs_ep->name;
2773 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2774 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2776 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2777 * an OUT endpoint, we may as well do this if in future the
2778 * code is changed to make each endpoint's direction changeable.
2781 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2782 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2784 /* if we're using dma, we need to set the next-endpoint pointer
2785 * to be something valid.
2788 if (using_dma(hsotg)) {
2789 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2790 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2791 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2796 * s3c_hsotg_otgreset - reset the OtG phy block
2797 * @hsotg: The host state.
2799 * Power up the phy, set the basic configuration and start the PHY.
2801 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2803 struct clk *xusbxti;
2806 pwr = readl(S3C_PHYPWR);
2808 writel(pwr, S3C_PHYPWR);
2811 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2813 xusbxti = clk_get(hsotg->dev, "xusbxti");
2814 if (xusbxti && !IS_ERR(xusbxti)) {
2815 switch (clk_get_rate(xusbxti)) {
2817 osc |= S3C_PHYCLK_CLKSEL_12M;
2820 osc |= S3C_PHYCLK_CLKSEL_24M;
2824 /* default reference clock */
2830 writel(osc | 0x10, S3C_PHYCLK);
2832 /* issue a full set of resets to the otg and core */
2834 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2835 udelay(20); /* at-least 10uS */
2836 writel(0, S3C_RSTCON);
2840 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2844 /* unmask subset of endpoint interrupts */
2846 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2847 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2848 hsotg->regs + S3C_DIEPMSK);
2850 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2851 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2852 hsotg->regs + S3C_DOEPMSK);
2854 writel(0, hsotg->regs + S3C_DAINTMSK);
2856 /* Be in disconnected state until gadget is registered */
2857 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2860 /* post global nak until we're ready */
2861 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2862 hsotg->regs + S3C_DCTL);
2867 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2868 readl(hsotg->regs + S3C_GRXFSIZ),
2869 readl(hsotg->regs + S3C_GNPTXFSIZ));
2871 s3c_hsotg_init_fifo(hsotg);
2873 /* set the PLL on, remove the HNP/SRP and set the PHY */
2874 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2875 hsotg->regs + S3C_GUSBCFG);
2877 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2878 hsotg->regs + S3C_GAHBCFG);
2880 /* check hardware configuration */
2882 cfg4 = readl(hsotg->regs + 0x50);
2883 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2885 dev_info(hsotg->dev, "%s fifos\n",
2886 hsotg->dedicated_fifos ? "dedicated" : "shared");
2889 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2891 struct device *dev = hsotg->dev;
2892 void __iomem *regs = hsotg->regs;
2896 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2897 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2898 readl(regs + S3C_DIEPMSK));
2900 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2901 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2903 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2904 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2906 /* show periodic fifo settings */
2908 for (idx = 1; idx <= 15; idx++) {
2909 val = readl(regs + S3C_DPTXFSIZn(idx));
2910 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2911 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2912 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2915 for (idx = 0; idx < 15; idx++) {
2917 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2918 readl(regs + S3C_DIEPCTL(idx)),
2919 readl(regs + S3C_DIEPTSIZ(idx)),
2920 readl(regs + S3C_DIEPDMA(idx)));
2922 val = readl(regs + S3C_DOEPCTL(idx));
2924 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2925 idx, readl(regs + S3C_DOEPCTL(idx)),
2926 readl(regs + S3C_DOEPTSIZ(idx)),
2927 readl(regs + S3C_DOEPDMA(idx)));
2931 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2932 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2937 * state_show - debugfs: show overall driver and device state.
2938 * @seq: The seq file to write to.
2939 * @v: Unused parameter.
2941 * This debugfs entry shows the overall state of the hardware and
2942 * some general information about each of the endpoints available
2945 static int state_show(struct seq_file *seq, void *v)
2947 struct s3c_hsotg *hsotg = seq->private;
2948 void __iomem *regs = hsotg->regs;
2951 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2952 readl(regs + S3C_DCFG),
2953 readl(regs + S3C_DCTL),
2954 readl(regs + S3C_DSTS));
2956 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2957 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2959 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2960 readl(regs + S3C_GINTMSK),
2961 readl(regs + S3C_GINTSTS));
2963 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2964 readl(regs + S3C_DAINTMSK),
2965 readl(regs + S3C_DAINT));
2967 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2968 readl(regs + S3C_GNPTXSTS),
2969 readl(regs + S3C_GRXSTSR));
2971 seq_printf(seq, "\nEndpoint status:\n");
2973 for (idx = 0; idx < 15; idx++) {
2976 in = readl(regs + S3C_DIEPCTL(idx));
2977 out = readl(regs + S3C_DOEPCTL(idx));
2979 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2982 in = readl(regs + S3C_DIEPTSIZ(idx));
2983 out = readl(regs + S3C_DOEPTSIZ(idx));
2985 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2988 seq_printf(seq, "\n");
2994 static int state_open(struct inode *inode, struct file *file)
2996 return single_open(file, state_show, inode->i_private);
2999 static const struct file_operations state_fops = {
3000 .owner = THIS_MODULE,
3003 .llseek = seq_lseek,
3004 .release = single_release,
3008 * fifo_show - debugfs: show the fifo information
3009 * @seq: The seq_file to write data to.
3010 * @v: Unused parameter.
3012 * Show the FIFO information for the overall fifo and all the
3013 * periodic transmission FIFOs.
3015 static int fifo_show(struct seq_file *seq, void *v)
3017 struct s3c_hsotg *hsotg = seq->private;
3018 void __iomem *regs = hsotg->regs;
3022 seq_printf(seq, "Non-periodic FIFOs:\n");
3023 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
3025 val = readl(regs + S3C_GNPTXFSIZ);
3026 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3027 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
3028 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
3030 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3032 for (idx = 1; idx <= 15; idx++) {
3033 val = readl(regs + S3C_DPTXFSIZn(idx));
3035 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3036 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
3037 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
3043 static int fifo_open(struct inode *inode, struct file *file)
3045 return single_open(file, fifo_show, inode->i_private);
3048 static const struct file_operations fifo_fops = {
3049 .owner = THIS_MODULE,
3052 .llseek = seq_lseek,
3053 .release = single_release,
3057 static const char *decode_direction(int is_in)
3059 return is_in ? "in" : "out";
3063 * ep_show - debugfs: show the state of an endpoint.
3064 * @seq: The seq_file to write data to.
3065 * @v: Unused parameter.
3067 * This debugfs entry shows the state of the given endpoint (one is
3068 * registered for each available).
3070 static int ep_show(struct seq_file *seq, void *v)
3072 struct s3c_hsotg_ep *ep = seq->private;
3073 struct s3c_hsotg *hsotg = ep->parent;
3074 struct s3c_hsotg_req *req;
3075 void __iomem *regs = hsotg->regs;
3076 int index = ep->index;
3077 int show_limit = 15;
3078 unsigned long flags;
3080 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3081 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3083 /* first show the register state */
3085 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3086 readl(regs + S3C_DIEPCTL(index)),
3087 readl(regs + S3C_DOEPCTL(index)));
3089 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3090 readl(regs + S3C_DIEPDMA(index)),
3091 readl(regs + S3C_DOEPDMA(index)));
3093 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3094 readl(regs + S3C_DIEPINT(index)),
3095 readl(regs + S3C_DOEPINT(index)));
3097 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3098 readl(regs + S3C_DIEPTSIZ(index)),
3099 readl(regs + S3C_DOEPTSIZ(index)));
3101 seq_printf(seq, "\n");
3102 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3103 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3105 seq_printf(seq, "request list (%p,%p):\n",
3106 ep->queue.next, ep->queue.prev);
3108 spin_lock_irqsave(&ep->lock, flags);
3110 list_for_each_entry(req, &ep->queue, queue) {
3111 if (--show_limit < 0) {
3112 seq_printf(seq, "not showing more requests...\n");
3116 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3117 req == ep->req ? '*' : ' ',
3118 req, req->req.length, req->req.buf);
3119 seq_printf(seq, "%d done, res %d\n",
3120 req->req.actual, req->req.status);
3123 spin_unlock_irqrestore(&ep->lock, flags);
3128 static int ep_open(struct inode *inode, struct file *file)
3130 return single_open(file, ep_show, inode->i_private);
3133 static const struct file_operations ep_fops = {
3134 .owner = THIS_MODULE,
3137 .llseek = seq_lseek,
3138 .release = single_release,
3142 * s3c_hsotg_create_debug - create debugfs directory and files
3143 * @hsotg: The driver state
3145 * Create the debugfs files to allow the user to get information
3146 * about the state of the system. The directory name is created
3147 * with the same name as the device itself, in case we end up
3148 * with multiple blocks in future systems.
3150 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3152 struct dentry *root;
3155 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3156 hsotg->debug_root = root;
3158 dev_err(hsotg->dev, "cannot create debug root\n");
3162 /* create general state file */
3164 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3165 hsotg, &state_fops);
3167 if (IS_ERR(hsotg->debug_file))
3168 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3170 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3173 if (IS_ERR(hsotg->debug_fifo))
3174 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3176 /* create one file for each endpoint */
3178 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3179 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3181 ep->debugfs = debugfs_create_file(ep->name, 0444,
3182 root, ep, &ep_fops);
3184 if (IS_ERR(ep->debugfs))
3185 dev_err(hsotg->dev, "failed to create %s debug file\n",
3191 * s3c_hsotg_delete_debug - cleanup debugfs entries
3192 * @hsotg: The driver state
3194 * Cleanup (remove) the debugfs files for use on module exit.
3196 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3200 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3201 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3202 debugfs_remove(ep->debugfs);
3205 debugfs_remove(hsotg->debug_file);
3206 debugfs_remove(hsotg->debug_fifo);
3207 debugfs_remove(hsotg->debug_root);
3211 * s3c_hsotg_gate - set the hardware gate for the block
3212 * @pdev: The device we bound to
3215 * Set the hardware gate setting into the block. If we end up on
3216 * something other than an S3C64XX, then we might need to change this
3217 * to using a platform data callback, or some other mechanism.
3219 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3221 unsigned long flags;
3224 local_irq_save(flags);
3226 others = __raw_readl(S3C64XX_OTHERS);
3228 others |= S3C64XX_OTHERS_USBMASK;
3230 others &= ~S3C64XX_OTHERS_USBMASK;
3231 __raw_writel(others, S3C64XX_OTHERS);
3233 local_irq_restore(flags);
3236 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3238 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3240 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3241 struct device *dev = &pdev->dev;
3242 struct s3c_hsotg *hsotg;
3243 struct resource *res;
3248 plat = &s3c_hsotg_default_pdata;
3250 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3251 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3254 dev_err(dev, "cannot get memory\n");
3261 platform_set_drvdata(pdev, hsotg);
3263 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3265 dev_err(dev, "cannot find register resource 0\n");
3270 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3272 if (!hsotg->regs_res) {
3273 dev_err(dev, "cannot reserve registers\n");
3278 hsotg->regs = ioremap(res->start, resource_size(res));
3280 dev_err(dev, "cannot map registers\n");
3285 ret = platform_get_irq(pdev, 0);
3287 dev_err(dev, "cannot find IRQ\n");
3293 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3295 dev_err(dev, "cannot claim IRQ\n");
3299 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3301 device_initialize(&hsotg->gadget.dev);
3303 dev_set_name(&hsotg->gadget.dev, "gadget");
3305 hsotg->gadget.is_dualspeed = 1;
3306 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3307 hsotg->gadget.name = dev_name(dev);
3309 hsotg->gadget.dev.parent = dev;
3310 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3312 /* setup endpoint information */
3314 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3315 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3317 /* allocate EP0 request */
3319 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3321 if (!hsotg->ctrl_req) {
3322 dev_err(dev, "failed to allocate ctrl req\n");
3326 /* reset the system */
3328 s3c_hsotg_gate(pdev, true);
3330 s3c_hsotg_otgreset(hsotg);
3331 s3c_hsotg_corereset(hsotg);
3332 s3c_hsotg_init(hsotg);
3334 /* initialise the endpoints now the core has been initialised */
3335 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3336 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3338 s3c_hsotg_create_debug(hsotg);
3340 s3c_hsotg_dump(hsotg);
3346 iounmap(hsotg->regs);
3349 release_resource(hsotg->regs_res);
3350 kfree(hsotg->regs_res);
3357 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3359 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3361 s3c_hsotg_delete_debug(hsotg);
3363 usb_gadget_unregister_driver(hsotg->driver);
3365 free_irq(hsotg->irq, hsotg);
3366 iounmap(hsotg->regs);
3368 release_resource(hsotg->regs_res);
3369 kfree(hsotg->regs_res);
3371 s3c_hsotg_gate(pdev, false);
3378 #define s3c_hsotg_suspend NULL
3379 #define s3c_hsotg_resume NULL
3382 static struct platform_driver s3c_hsotg_driver = {
3384 .name = "s3c-hsotg",
3385 .owner = THIS_MODULE,
3387 .probe = s3c_hsotg_probe,
3388 .remove = __devexit_p(s3c_hsotg_remove),
3389 .suspend = s3c_hsotg_suspend,
3390 .resume = s3c_hsotg_resume,
3393 static int __init s3c_hsotg_modinit(void)
3395 return platform_driver_register(&s3c_hsotg_driver);
3398 static void __exit s3c_hsotg_modexit(void)
3400 platform_driver_unregister(&s3c_hsotg_driver);
3403 module_init(s3c_hsotg_modinit);
3404 module_exit(s3c_hsotg_modexit);
3406 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3407 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3408 MODULE_LICENSE("GPL");
3409 MODULE_ALIAS("platform:s3c-hsotg");