2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: MAC routines
29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
37 #if !defined(__TTYPE_H__)
40 #if !defined(__TMACRO_H__)
43 #if !defined(__UPC_H__)
47 /*--------------------- Export Definitions -------------------------*/
49 // Registers in the MAC
51 #define MAC_MAX_CONTEXT_SIZE_PAGE0 256
52 #define MAC_MAX_CONTEXT_SIZE_PAGE1 128
53 #define MAC_MAX_CONTEXT_SIZE MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1
55 // Registers not related to 802.11b
56 #define MAC_REG_BCFG0 0x00
57 #define MAC_REG_BCFG1 0x01
58 #define MAC_REG_FCR0 0x02
59 #define MAC_REG_FCR1 0x03
60 #define MAC_REG_BISTCMD 0x04
61 #define MAC_REG_BISTSR0 0x05
62 #define MAC_REG_BISTSR1 0x06
63 #define MAC_REG_BISTSR2 0x07
64 #define MAC_REG_I2MCSR 0x08
65 #define MAC_REG_I2MTGID 0x09
66 #define MAC_REG_I2MTGAD 0x0A
67 #define MAC_REG_I2MCFG 0x0B
68 #define MAC_REG_I2MDIPT 0x0C
69 #define MAC_REG_I2MDOPT 0x0E
70 #define MAC_REG_PMC0 0x10
71 #define MAC_REG_PMC1 0x11
72 #define MAC_REG_STICKHW 0x12
73 #define MAC_REG_LOCALID 0x14
74 #define MAC_REG_TESTCFG 0x15
75 #define MAC_REG_JUMPER0 0x16
76 #define MAC_REG_JUMPER1 0x17
77 #define MAC_REG_TMCTL0 0x18
78 #define MAC_REG_TMCTL1 0x19
79 #define MAC_REG_TMDATA0 0x1C
80 // MAC Parameter related
81 #define MAC_REG_LRT 0x20 //
82 #define MAC_REG_SRT 0x21 //
83 #define MAC_REG_SIFS 0x22 //
84 #define MAC_REG_DIFS 0x23 //
85 #define MAC_REG_EIFS 0x24 //
86 #define MAC_REG_SLOT 0x25 //
87 #define MAC_REG_BI 0x26 //
88 #define MAC_REG_CWMAXMIN0 0x28 //
89 #define MAC_REG_LINKOFFTOTM 0x2A
90 #define MAC_REG_SWTMOT 0x2B
91 #define MAC_REG_MIBCNTR 0x2C
92 #define MAC_REG_RTSOKCNT 0x2C
93 #define MAC_REG_RTSFAILCNT 0x2D
94 #define MAC_REG_ACKFAILCNT 0x2E
95 #define MAC_REG_FCSERRCNT 0x2F
97 #define MAC_REG_TSFCNTR 0x30 //
98 #define MAC_REG_NEXTTBTT 0x38 //
99 #define MAC_REG_TSFOFST 0x40 //
100 #define MAC_REG_TFTCTL 0x48 //
101 // WMAC Control/Status Related
102 #define MAC_REG_ENCFG 0x4C //
103 #define MAC_REG_PAGE1SEL 0x4F //
104 #define MAC_REG_CFG 0x50 //
105 #define MAC_REG_TEST 0x52 //
106 #define MAC_REG_HOSTCR 0x54 //
107 #define MAC_REG_MACCR 0x55 //
108 #define MAC_REG_RCR 0x56 //
109 #define MAC_REG_TCR 0x57 //
110 #define MAC_REG_IMR 0x58 //
111 #define MAC_REG_ISR 0x5C
112 // Power Saving Related
113 #define MAC_REG_PSCFG 0x60 //
114 #define MAC_REG_PSCTL 0x61 //
115 #define MAC_REG_PSPWRSIG 0x62 //
116 #define MAC_REG_BBCR13 0x63
117 #define MAC_REG_AIDATIM 0x64
118 #define MAC_REG_PWBT 0x66
119 #define MAC_REG_WAKEOKTMR 0x68
120 #define MAC_REG_CALTMR 0x69
121 #define MAC_REG_SYNSPACCNT 0x6A
122 #define MAC_REG_WAKSYNOPT 0x6B
123 // Baseband/IF Control Group
124 #define MAC_REG_BBREGCTL 0x6C //
125 #define MAC_REG_CHANNEL 0x6D
126 #define MAC_REG_BBREGADR 0x6E
127 #define MAC_REG_BBREGDATA 0x6F
128 #define MAC_REG_IFREGCTL 0x70 //
129 #define MAC_REG_IFDATA 0x71 //
130 #define MAC_REG_ITRTMSET 0x74 //
131 #define MAC_REG_PAPEDELAY 0x77
132 #define MAC_REG_SOFTPWRCTL 0x78 //
133 #define MAC_REG_GPIOCTL0 0x7A //
134 #define MAC_REG_GPIOCTL1 0x7B //
136 // MAC DMA Related Group
137 #define MAC_REG_TXDMACTL0 0x7C //
138 #define MAC_REG_TXDMAPTR0 0x80 //
139 #define MAC_REG_AC0DMACTL 0x84 //
140 #define MAC_REG_AC0DMAPTR 0x88 //
141 #define MAC_REG_BCNDMACTL 0x8C //
142 #define MAC_REG_BCNDMAPTR 0x90 //
143 #define MAC_REG_RXDMACTL0 0x94 //
144 #define MAC_REG_RXDMAPTR0 0x98 //
145 #define MAC_REG_RXDMACTL1 0x9C //
146 #define MAC_REG_RXDMAPTR1 0xA0 //
147 #define MAC_REG_SYNCDMACTL 0xA4 //
148 #define MAC_REG_SYNCDMAPTR 0xA8
149 #define MAC_REG_ATIMDMACTL 0xAC
150 #define MAC_REG_ATIMDMAPTR 0xB0
151 // MiscFF PIO related
152 #define MAC_REG_MISCFFNDEX 0xB4
153 #define MAC_REG_MISCFFCTL 0xB6
154 #define MAC_REG_MISCFFDATA 0xB8
156 #define MAC_REG_TMDATA1 0xBC
158 #define MAC_REG_WAKEUPEN0 0xC0
159 #define MAC_REG_WAKEUPEN1 0xC1
160 #define MAC_REG_WAKEUPSR0 0xC2
161 #define MAC_REG_WAKEUPSR1 0xC3
162 #define MAC_REG_WAKE128_0 0xC4
163 #define MAC_REG_WAKE128_1 0xD4
164 #define MAC_REG_WAKE128_2 0xE4
165 #define MAC_REG_WAKE128_3 0xF4
167 /////////////// Page 1 ///////////////////
168 #define MAC_REG_CRC_128_0 0x04
169 #define MAC_REG_CRC_128_1 0x06
170 #define MAC_REG_CRC_128_2 0x08
171 #define MAC_REG_CRC_128_3 0x0A
172 // MAC Configuration Group
173 #define MAC_REG_PAR0 0x0C
174 #define MAC_REG_PAR4 0x10
175 #define MAC_REG_BSSID0 0x14
176 #define MAC_REG_BSSID4 0x18
177 #define MAC_REG_MAR0 0x1C
178 #define MAC_REG_MAR4 0x20
179 // MAC RSPPKT INFO Group
180 #define MAC_REG_RSPINF_B_1 0x24
181 #define MAC_REG_RSPINF_B_2 0x28
182 #define MAC_REG_RSPINF_B_5 0x2C
183 #define MAC_REG_RSPINF_B_11 0x30
184 #define MAC_REG_RSPINF_A_6 0x34
185 #define MAC_REG_RSPINF_A_9 0x36
186 #define MAC_REG_RSPINF_A_12 0x38
187 #define MAC_REG_RSPINF_A_18 0x3A
188 #define MAC_REG_RSPINF_A_24 0x3C
189 #define MAC_REG_RSPINF_A_36 0x3E
190 #define MAC_REG_RSPINF_A_48 0x40
191 #define MAC_REG_RSPINF_A_54 0x42
192 #define MAC_REG_RSPINF_A_72 0x44
195 #define MAC_REG_QUIETINIT 0x60
196 #define MAC_REG_QUIETGAP 0x62
197 #define MAC_REG_QUIETDUR 0x64
198 #define MAC_REG_MSRCTL 0x66
199 #define MAC_REG_MSRBBSTS 0x67
200 #define MAC_REG_MSRSTART 0x68
201 #define MAC_REG_MSRDURATION 0x70
202 #define MAC_REG_CCAFRACTION 0x72
203 #define MAC_REG_PWRCCK 0x73
204 #define MAC_REG_PWROFDM 0x7C
208 // Bits in the BCFG0 register
210 #define BCFG0_PERROFF 0x40
211 #define BCFG0_MRDMDIS 0x20
212 #define BCFG0_MRDLDIS 0x10
213 #define BCFG0_MWMEN 0x08
214 #define BCFG0_VSERREN 0x02
215 #define BCFG0_LATMEN 0x01
218 // Bits in the BCFG1 register
220 #define BCFG1_CFUNOPT 0x80
221 #define BCFG1_CREQOPT 0x40
222 #define BCFG1_DMA8 0x10
223 #define BCFG1_ARBITOPT 0x08
224 #define BCFG1_PCIMEN 0x04
225 #define BCFG1_MIOEN 0x02
226 #define BCFG1_CISDLYEN 0x01
228 // Bits in RAMBIST registers
229 #define BISTCMD_TSTPAT5 0x00 //
230 #define BISTCMD_TSTPATA 0x80 //
231 #define BISTCMD_TSTERR 0x20 //
232 #define BISTCMD_TSTPATF 0x18 //
233 #define BISTCMD_TSTPAT0 0x10 //
234 #define BISTCMD_TSTMODE 0x04 //
235 #define BISTCMD_TSTITTX 0x03 //
236 #define BISTCMD_TSTATRX 0x02 //
237 #define BISTCMD_TSTATTX 0x01 //
238 #define BISTCMD_TSTRX 0x00 //
239 #define BISTSR0_BISTGO 0x01 //
240 #define BISTSR1_TSTSR 0x01 //
241 #define BISTSR2_CMDPRTEN 0x02 //
242 #define BISTSR2_RAMTSTEN 0x01 //
245 // Bits in the I2MCFG EEPROM register
247 #define I2MCFG_BOUNDCTL 0x80
248 #define I2MCFG_WAITCTL 0x20
249 #define I2MCFG_SCLOECTL 0x10
250 #define I2MCFG_WBUSYCTL 0x08
251 #define I2MCFG_NORETRY 0x04
252 #define I2MCFG_I2MLDSEQ 0x02
253 #define I2MCFG_I2CMFAST 0x01
256 // Bits in the I2MCSR EEPROM register
258 #define I2MCSR_EEMW 0x80
259 #define I2MCSR_EEMR 0x40
260 #define I2MCSR_AUTOLD 0x08
261 #define I2MCSR_NACK 0x02
262 #define I2MCSR_DONE 0x01
265 // Bits in the PMC1 register
268 #define PCISTIKY 0x40
272 // Bits in the STICKYHW register
274 #define STICKHW_DS1_SHADOW 0x02
275 #define STICKHW_DS0_SHADOW 0x01
278 // Bits in the TMCTL register
280 #define TMCTL_TSUSP 0x04
281 #define TMCTL_TMD 0x02
282 #define TMCTL_TE 0x01
285 // Bits in the TFTCTL register
287 #define TFTCTL_HWUTSF 0x80 //
288 #define TFTCTL_TBTTSYNC 0x40
289 #define TFTCTL_HWUTSFEN 0x20
290 #define TFTCTL_TSFCNTRRD 0x10 //
291 #define TFTCTL_TBTTSYNCEN 0x08 //
292 #define TFTCTL_TSFSYNCEN 0x04 //
293 #define TFTCTL_TSFCNTRST 0x02 //
294 #define TFTCTL_TSFCNTREN 0x01 //
297 // Bits in the EnhanceCFG register
299 #define EnCFG_BarkerPream 0x00020000
300 #define EnCFG_NXTBTTCFPSTR 0x00010000
301 //#define EnCFG_TXLMT3UPDATE 0x00008000
302 //#define EnCFG_TXLMT2UPDATE 0x00004000
303 //#define EnCFG_TXLMT1UPDATE 0x00002000
304 //#define EnCFG_TXLMT3EN 0x00001000
305 //#define EnCFG_TXLMT2EN 0x00000800
306 //#define EnCFG_TXLMT1EN 0x00000400
307 #define EnCFG_BcnSusClr 0x00000200
308 #define EnCFG_BcnSusInd 0x00000100
309 //#define EnCFG_CWOFF1 0x00000080
310 #define EnCFG_CFP_ProtectEn 0x00000040
311 #define EnCFG_ProtectMd 0x00000020
312 #define EnCFG_HwParCFP 0x00000010
313 //#define EnCFG_QOS 0x00000008
314 #define EnCFG_CFNULRSP 0x00000004
315 #define EnCFG_BBType_MASK 0x00000003
316 #define EnCFG_BBType_g 0x00000002
317 #define EnCFG_BBType_b 0x00000001
318 #define EnCFG_BBType_a 0x00000000
321 // Bits in the Page1Sel register
323 #define PAGE1_SEL 0x01
326 // Bits in the CFG register
328 #define CFG_TKIPOPT 0x80
329 #define CFG_RXDMAOPT 0x40
330 #define CFG_TMOT_SW 0x20
331 #define CFG_TMOT_HWLONG 0x10
332 #define CFG_TMOT_HW 0x00
333 #define CFG_CFPENDOPT 0x08
334 #define CFG_BCNSUSEN 0x04
335 #define CFG_NOTXTIMEOUT 0x02
336 #define CFG_NOBUFOPT 0x01
339 // Bits in the TEST register
341 #define TEST_LBEXT 0x80 //
342 #define TEST_LBINT 0x40 //
343 #define TEST_LBNONE 0x00 //
344 #define TEST_SOFTINT 0x20 //
345 #define TEST_CONTTX 0x10 //
346 #define TEST_TXPE 0x08 //
347 #define TEST_NAVDIS 0x04 //
348 #define TEST_NOCTS 0x02 //
349 #define TEST_NOACK 0x01 //
352 // Bits in the HOSTCR register
354 #define HOSTCR_TXONST 0x80 //
355 #define HOSTCR_RXONST 0x40 //
356 #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
357 #define HOSTCR_AP 0x10 // Port Type 1 = AP
358 #define HOSTCR_TXON 0x08 //0000 1000
359 #define HOSTCR_RXON 0x04 //0000 0100
360 #define HOSTCR_MACEN 0x02 //0000 0010
361 #define HOSTCR_SOFTRST 0x01 //0000 0001
364 // Bits in the MACCR register
366 #define MACCR_SYNCFLUSHOK 0x04 //
367 #define MACCR_SYNCFLUSH 0x02 //
368 #define MACCR_CLRNAV 0x01 //
370 // Bits in the MAC_REG_GPIOCTL0 register
372 #define LED_ACTSET 0x01 //
373 #define LED_RFOFF 0x02 //
374 #define LED_NOCONNECT 0x04 //
376 // Bits in the RCR register
378 #define RCR_SSID 0x80
379 #define RCR_RXALLTYPE 0x40 //
380 #define RCR_UNICAST 0x20 //
381 #define RCR_BROADCAST 0x10 //
382 #define RCR_MULTICAST 0x08 //
383 #define RCR_WPAERR 0x04 //
384 #define RCR_ERRCRC 0x02 //
385 #define RCR_BSSID 0x01 //
388 // Bits in the TCR register
390 #define TCR_SYNCDCFOPT 0x02 //
391 #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
394 // Bits in the IMR register
396 #define IMR_MEASURESTART 0x80000000 //
397 #define IMR_QUIETSTART 0x20000000 //
398 #define IMR_RADARDETECT 0x10000000 //
399 #define IMR_MEASUREEND 0x08000000 //
400 #define IMR_SOFTTIMER1 0x00200000 //
401 //#define IMR_SYNCFLUSHOK 0x00100000 //
402 //#define IMR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
403 //#define IMR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
404 //#define IMR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
405 //#define IMR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
406 //#define IMR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
407 //#define IMR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
408 //#define IMR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
409 #define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
410 #define IMR_RXNOBUF 0x00000800 //
411 #define IMR_MIBNEARFULL 0x00000400 //
412 #define IMR_SOFTINT 0x00000200 //
413 #define IMR_FETALERR 0x00000100 //
414 #define IMR_WATCHDOG 0x00000080 //
415 #define IMR_SOFTTIMER 0x00000040 //
416 #define IMR_GPIO 0x00000020 //
417 #define IMR_TBTT 0x00000010 //
418 #define IMR_RXDMA0 0x00000008 //
419 #define IMR_BNTX 0x00000004 //
420 #define IMR_AC0DMA 0x00000002 //
421 #define IMR_TXDMA0 0x00000001 //
425 // Bits in the ISR register
428 #define ISR_MEASURESTART 0x80000000 //
429 #define ISR_QUIETSTART 0x20000000 //
430 #define ISR_RADARDETECT 0x10000000 //
431 #define ISR_MEASUREEND 0x08000000 //
432 #define ISR_SOFTTIMER1 0x00200000 //
433 //#define ISR_SYNCFLUSHOK 0x00100000 //0001 0000 0000 0000 0000 0000
434 //#define ISR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
435 //#define ISR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
436 //#define ISR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
437 //#define ISR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
438 //#define ISR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
439 //#define ISR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
440 //#define ISR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
441 #define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
442 #define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000
443 #define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000
444 #define ISR_SOFTINT 0x00000200 //
445 #define ISR_FETALERR 0x00000100 //
446 #define ISR_WATCHDOG 0x00000080 //
447 #define ISR_SOFTTIMER 0x00000040 //
448 #define ISR_GPIO 0x00000020 //
449 #define ISR_TBTT 0x00000010 //
450 #define ISR_RXDMA0 0x00000008 //
451 #define ISR_BNTX 0x00000004 //
452 #define ISR_AC0DMA 0x00000002 //
453 #define ISR_TXDMA0 0x00000001 //
457 // Bits in the PSCFG register
459 #define PSCFG_PHILIPMD 0x40 //
460 #define PSCFG_WAKECALEN 0x20 //
461 #define PSCFG_WAKETMREN 0x10 //
462 #define PSCFG_BBPSPROG 0x08 //
463 #define PSCFG_WAKESYN 0x04 //
464 #define PSCFG_SLEEPSYN 0x02 //
465 #define PSCFG_AUTOSLEEP 0x01 //
468 // Bits in the PSCTL register
470 #define PSCTL_WAKEDONE 0x20 //
471 #define PSCTL_PS 0x10 //
472 #define PSCTL_GO2DOZE 0x08 //
473 #define PSCTL_LNBCN 0x04 //
474 #define PSCTL_ALBCN 0x02 //
475 #define PSCTL_PSEN 0x01 //
478 // Bits in the PSPWSIG register
480 #define PSSIG_WPE3 0x80 //
481 #define PSSIG_WPE2 0x40 //
482 #define PSSIG_WPE1 0x20 //
483 #define PSSIG_WRADIOPE 0x10 //
484 #define PSSIG_SPE3 0x08 //
485 #define PSSIG_SPE2 0x04 //
486 #define PSSIG_SPE1 0x02 //
487 #define PSSIG_SRADIOPE 0x01 //
490 // Bits in the BBREGCTL register
492 #define BBREGCTL_DONE 0x04 //
493 #define BBREGCTL_REGR 0x02 //
494 #define BBREGCTL_REGW 0x01 //
497 // Bits in the IFREGCTL register
499 #define IFREGCTL_DONE 0x04 //
500 #define IFREGCTL_IFRF 0x02 //
501 #define IFREGCTL_REGW 0x01 //
504 // Bits in the SOFTPWRCTL register
506 #define SOFTPWRCTL_RFLEOPT 0x0800 //
507 #define SOFTPWRCTL_TXPEINV 0x0200 //
508 #define SOFTPWRCTL_SWPECTI 0x0100 //
509 #define SOFTPWRCTL_SWPAPE 0x0020 //
510 #define SOFTPWRCTL_SWCALEN 0x0010 //
511 #define SOFTPWRCTL_SWRADIO_PE 0x0008 //
512 #define SOFTPWRCTL_SWPE2 0x0004 //
513 #define SOFTPWRCTL_SWPE1 0x0002 //
514 #define SOFTPWRCTL_SWPE3 0x0001 //
517 // Bits in the GPIOCTL1 register
519 #define GPIO1_DATA1 0x20 //
520 #define GPIO1_MD1 0x10 //
521 #define GPIO1_DATA0 0x02 //
522 #define GPIO1_MD0 0x01 //
525 // Bits in the DMACTL register
527 #define DMACTL_CLRRUN 0x00080000 //
528 #define DMACTL_RUN 0x00000008 //
529 #define DMACTL_WAKE 0x00000004 //
530 #define DMACTL_DEAD 0x00000002 //
531 #define DMACTL_ACTIVE 0x00000001 //
533 // Bits in the RXDMACTL0 register
535 #define RX_PERPKT 0x00000100 //
536 #define RX_PERPKTCLR 0x01000000 //
538 // Bits in the BCNDMACTL register
540 #define BEACON_READY 0x01 //
542 // Bits in the MISCFFCTL register
544 #define MISCFFCTL_WRITE 0x0001 //
550 #define WAKEUPEN0_DIRPKT 0x10
551 #define WAKEUPEN0_LINKOFF 0x08
552 #define WAKEUPEN0_ATIMEN 0x04
553 #define WAKEUPEN0_TIMEN 0x02
554 #define WAKEUPEN0_MAGICEN 0x01
559 #define WAKEUPEN1_128_3 0x08
560 #define WAKEUPEN1_128_2 0x04
561 #define WAKEUPEN1_128_1 0x02
562 #define WAKEUPEN1_128_0 0x01
567 #define WAKEUPSR0_DIRPKT 0x10
568 #define WAKEUPSR0_LINKOFF 0x08
569 #define WAKEUPSR0_ATIMEN 0x04
570 #define WAKEUPSR0_TIMEN 0x02
571 #define WAKEUPSR0_MAGICEN 0x01
576 #define WAKEUPSR1_128_3 0x08
577 #define WAKEUPSR1_128_2 0x04
578 #define WAKEUPSR1_128_1 0x02
579 #define WAKEUPSR1_128_0 0x01
582 // Bits in the MAC_REG_GPIOCTL register
584 #define GPIO0_MD 0x01 //
585 #define GPIO0_DATA 0x02 //
586 #define GPIO0_INTMD 0x04 //
587 #define GPIO1_MD 0x10 //
588 #define GPIO1_DATA 0x20 //
592 // Bits in the MSRCTL register
594 #define MSRCTL_FINISH 0x80
595 #define MSRCTL_READY 0x40
596 #define MSRCTL_RADARDETECT 0x20
597 #define MSRCTL_EN 0x10
598 #define MSRCTL_QUIETTXCHK 0x08
599 #define MSRCTL_QUIETRPT 0x04
600 #define MSRCTL_QUIETINT 0x02
601 #define MSRCTL_QUIETEN 0x01
603 // Bits in the MSRCTL1 register
605 #define MSRCTL1_TXPWR 0x08
606 #define MSRCTL1_CSAPAREN 0x04
607 #define MSRCTL1_TXPAUSE 0x01
611 #define MAC_LB_EXT 0x02 //
612 #define MAC_LB_INTERNAL 0x01 //
613 #define MAC_LB_NONE 0x00 //
615 // Ethernet address filter type
616 #define PKT_TYPE_NONE 0x00 // turn off receiver
617 #define PKT_TYPE_ALL_MULTICAST 0x80
618 #define PKT_TYPE_PROMISCUOUS 0x40
619 #define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
620 #define PKT_TYPE_BROADCAST 0x10
621 #define PKT_TYPE_MULTICAST 0x08
622 #define PKT_TYPE_ERROR_WPA 0x04
623 #define PKT_TYPE_ERROR_CRC 0x02
624 #define PKT_TYPE_BSSID 0x01
626 #define Default_BI 0x200
630 #define MISCFIFO_KEYETRY0 32
631 #define MISCFIFO_KEYENTRYSIZE 22
632 #define MISCFIFO_SYNINFO_IDX 10
633 #define MISCFIFO_SYNDATA_IDX 11
634 #define MISCFIFO_SYNDATASIZE 21
636 // enabled mask value of irq
637 #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
652 // max time out delay time
653 #define W_MAX_TIMEOUT 0xFFF0U //
655 // wait time within loop
656 #define CB_DELAY_LOOP_WAIT 10 // 10ms
661 #define REV_ID_VT3253_A0 0x00
662 #define REV_ID_VT3253_A1 0x01
663 #define REV_ID_VT3253_B0 0x08
664 #define REV_ID_VT3253_B1 0x09
666 /*--------------------- Export Types ------------------------------*/
668 /*--------------------- Export Macros ------------------------------*/
670 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
673 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
674 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
677 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
680 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
681 VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
684 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
687 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
688 VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
691 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
694 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
696 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
699 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
702 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
703 VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
706 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
709 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
710 VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
713 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
716 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
717 VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
720 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
722 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
723 (PDWORD)pdwCurrDescAddr); \
726 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
728 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
729 (PDWORD)pdwCurrDescAddr); \
732 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
734 VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
735 (PDWORD)pdwCurrDescAddr); \
738 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
740 VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
741 (PDWORD)pdwCurrDescAddr); \
744 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
746 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
747 (PDWORD)pdwCurrDescAddr); \
750 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
752 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
753 (PDWORD)pdwCurrDescAddr); \
756 // set the chip with current BCN tx descriptor address
757 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
759 VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
763 // set the chip with current BCN length
764 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
766 VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
770 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
772 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
773 VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
774 (PBYTE)pbyEtherAddr); \
775 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
777 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
779 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
781 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
783 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
785 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
788 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \
790 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
791 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
793 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
794 *(pbyEtherAddr + 1)); \
795 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
796 *(pbyEtherAddr + 2)); \
797 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
798 *(pbyEtherAddr + 3)); \
799 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
800 *(pbyEtherAddr + 4)); \
801 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
802 *(pbyEtherAddr + 5)); \
803 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
806 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \
808 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
809 VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
810 (PBYTE)pbyEtherAddr); \
811 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
813 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
815 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
817 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
819 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
821 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
825 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \
827 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
828 VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
830 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
831 *(pbyEtherAddr + 1)); \
832 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
833 *(pbyEtherAddr + 2)); \
834 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
835 *(pbyEtherAddr + 3)); \
836 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
837 *(pbyEtherAddr + 4)); \
838 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
839 *(pbyEtherAddr + 5)); \
840 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
844 #define MACvClearISR(dwIoBase) \
846 VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE); \
849 #define MACvStart(dwIoBase) \
851 VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
852 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)); \
855 #define MACvRx0PerPktMode(dwIoBase) \
857 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT); \
860 #define MACvRx0BufferFillMode(dwIoBase) \
862 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR); \
865 #define MACvRx1PerPktMode(dwIoBase) \
867 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT); \
870 #define MACvRx1BufferFillMode(dwIoBase) \
872 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR); \
875 #define MACvRxOn(dwIoBase) \
877 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON); \
880 #define MACvReceive0(dwIoBase) \
883 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
884 if (dwData & DMACTL_RUN) { \
885 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE);\
888 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
892 #define MACvReceive1(dwIoBase) \
895 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
896 if (dwData & DMACTL_RUN) { \
897 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE);\
900 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
904 #define MACvTxOn(dwIoBase) \
906 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON); \
909 #define MACvTransmit0(dwIoBase) \
912 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
913 if (dwData & DMACTL_RUN) { \
914 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE);\
917 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
921 #define MACvTransmitAC0(dwIoBase) \
924 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
925 if (dwData & DMACTL_RUN) { \
926 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE);\
929 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
933 #define MACvTransmitSYNC(dwIoBase) \
936 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
937 if (dwData & DMACTL_RUN) { \
938 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE);\
941 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
945 #define MACvTransmitATIM(dwIoBase) \
948 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
949 if (dwData & DMACTL_RUN) { \
950 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE);\
953 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
957 #define MACvTransmitBCN(dwIoBase) \
959 VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY); \
962 #define MACvClearStckDS(dwIoBase) \
965 VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
966 byOrgValue = byOrgValue & 0xFC; \
967 VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
970 #define MACvReadISR(dwIoBase, pdwValue) \
972 VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue); \
975 #define MACvWriteISR(dwIoBase, dwValue) \
977 VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue); \
980 #define MACvIntEnable(dwIoBase, dwMask) \
982 VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask); \
985 #define MACvIntDisable(dwIoBase) \
987 VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0); \
990 #define MACvSelectPage0(dwIoBase) \
992 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
994 #define MACvSelectPage1(dwIoBase) \
996 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
999 #define MACvReadMIBCounter(dwIoBase, pdwCounter) \
1001 VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter); \
1004 #define MACvPwrEvntDisable(dwIoBase) \
1006 VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000); \
1009 #define MACvEnableProtectMD(dwIoBase) \
1012 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1013 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
1014 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1017 #define MACvDisableProtectMD(dwIoBase) \
1020 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1021 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
1022 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1025 #define MACvEnableBarkerPreambleMd(dwIoBase) \
1028 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1029 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
1030 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1033 #define MACvDisableBarkerPreambleMd(dwIoBase) \
1036 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1037 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
1038 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1041 #define MACvSetBBType(dwIoBase, byTyp) \
1044 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
1045 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
1046 dwOrgValue = dwOrgValue | (DWORD) byTyp; \
1047 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
1050 #define MACvReadATIMW(dwIoBase, pwCounter) \
1052 VNSvInPortW(dwIoBase + MAC_REG_AIDATIM , pwCounter); \
1055 #define MACvWriteATIMW(dwIoBase, wCounter) \
1057 VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM , wCounter); \
1060 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \
1062 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
1063 VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
1064 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
1067 #define MACvGPIOIn(dwIoBase, pbyValue) \
1069 VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue); \
1072 #define MACvSetRFLE_LatchBase(dwIoBase) \
1074 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT); \
1077 /*--------------------- Export Classes ----------------------------*/
1079 /*--------------------- Export Variables --------------------------*/
1081 /*--------------------- Export Functions --------------------------*/
1083 extern "C" { /* Assume C declarations for C++ */
1084 #endif /* __cplusplus */
1086 extern WORD TxRate_iwconfig;//2008-5-8 <add> by chester
1087 VOID MACvReadAllRegs(DWORD_PTR dwIoBase, PBYTE pbyMacRegs);
1089 BOOL MACbIsRegBitsOn(DWORD_PTR dwIoBase, BYTE byRegOfs, BYTE byTestBits);
1090 BOOL MACbIsRegBitsOff(DWORD_PTR dwIoBase, BYTE byRegOfs, BYTE byTestBits);
1092 BOOL MACbIsIntDisable(DWORD_PTR dwIoBase);
1094 BYTE MACbyReadMultiAddr(DWORD_PTR dwIoBase, UINT uByteIdx);
1095 VOID MACvWriteMultiAddr(DWORD_PTR dwIoBase, UINT uByteIdx, BYTE byData);
1096 VOID MACvSetMultiAddrByHash(DWORD_PTR dwIoBase, BYTE byHashIdx);
1097 VOID MACvResetMultiAddrByHash(DWORD_PTR dwIoBase, BYTE byHashIdx);
1099 VOID MACvSetRxThreshold(DWORD_PTR dwIoBase, BYTE byThreshold);
1100 VOID MACvGetRxThreshold(DWORD_PTR dwIoBase, PBYTE pbyThreshold);
1102 VOID MACvSetTxThreshold(DWORD_PTR dwIoBase, BYTE byThreshold);
1103 VOID MACvGetTxThreshold(DWORD_PTR dwIoBase, PBYTE pbyThreshold);
1105 VOID MACvSetDmaLength(DWORD_PTR dwIoBase, BYTE byDmaLength);
1106 VOID MACvGetDmaLength(DWORD_PTR dwIoBase, PBYTE pbyDmaLength);
1108 VOID MACvSetShortRetryLimit(DWORD_PTR dwIoBase, BYTE byRetryLimit);
1109 VOID MACvGetShortRetryLimit(DWORD_PTR dwIoBase, PBYTE pbyRetryLimit);
1111 VOID MACvSetLongRetryLimit(DWORD_PTR dwIoBase, BYTE byRetryLimit);
1112 VOID MACvGetLongRetryLimit(DWORD_PTR dwIoBase, PBYTE pbyRetryLimit);
1114 VOID MACvSetLoopbackMode(DWORD_PTR dwIoBase, BYTE byLoopbackMode);
1115 BOOL MACbIsInLoopbackMode(DWORD_PTR dwIoBase);
1117 VOID MACvSetPacketFilter(DWORD_PTR dwIoBase, WORD wFilterType);
1119 VOID MACvSaveContext(DWORD_PTR dwIoBase, PBYTE pbyCxtBuf);
1120 VOID MACvRestoreContext(DWORD_PTR dwIoBase, PBYTE pbyCxtBuf);
1121 BOOL MACbCompareContext(DWORD_PTR dwIoBase, PBYTE pbyCxtBuf);
1123 BOOL MACbSoftwareReset(DWORD_PTR dwIoBase);
1124 BOOL MACbSafeSoftwareReset(DWORD_PTR dwIoBase);
1125 BOOL MACbSafeRxOff(DWORD_PTR dwIoBase);
1126 BOOL MACbSafeTxOff(DWORD_PTR dwIoBase);
1127 BOOL MACbSafeStop(DWORD_PTR dwIoBase);
1128 BOOL MACbShutdown(DWORD_PTR dwIoBase);
1129 VOID MACvInitialize(DWORD_PTR dwIoBase);
1130 VOID MACvSetCurrRx0DescAddr(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1131 VOID MACvSetCurrRx1DescAddr(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1132 VOID MACvSetCurrTXDescAddr(int iTxType, DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1133 VOID MACvSetCurrTx0DescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1134 VOID MACvSetCurrAC0DescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1135 VOID MACvSetCurrSyncDescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1136 VOID MACvSetCurrATIMDescAddrEx(DWORD_PTR dwIoBase, DWORD dwCurrDescAddr);
1137 void MACvTimer0MicroSDelay(DWORD_PTR dwIoBase, UINT uDelay);
1138 void MACvOneShotTimer0MicroSec(DWORD_PTR dwIoBase, UINT uDelayTime);
1139 void MACvOneShotTimer1MicroSec(DWORD_PTR dwIoBase, UINT uDelayTime);
1141 void MACvSetMISCFifo(DWORD_PTR dwIoBase, WORD wOffset, DWORD dwData);
1143 BOOL MACbTxDMAOff (DWORD_PTR dwIoBase, UINT idx);
1145 void MACvClearBusSusInd(DWORD_PTR dwIoBase);
1146 void MACvEnableBusSusEn(DWORD_PTR dwIoBase);
1148 BOOL MACbFlushSYNCFifo(DWORD_PTR dwIoBase);
1149 BOOL MACbPSWakeup(DWORD_PTR dwIoBase);
1151 void MACvSetKeyEntry(DWORD_PTR dwIoBase, WORD wKeyCtl, UINT uEntryIdx, UINT uKeyIdx, PBYTE pbyAddr, PDWORD pdwKey, BYTE byLocalID);
1152 void MACvDisableKeyEntry(DWORD_PTR dwIoBase, UINT uEntryIdx);
1153 void MACvSetDefaultKeyEntry(DWORD_PTR dwIoBase, UINT uKeyLen, UINT uKeyIdx, PDWORD pdwKey, BYTE byLocalID);
1154 //void MACvEnableDefaultKey(DWORD_PTR dwIoBase, BYTE byLocalID);
1155 void MACvDisableDefaultKey(DWORD_PTR dwIoBase);
1156 void MACvSetDefaultTKIPKeyEntry(DWORD_PTR dwIoBase, UINT uKeyLen, UINT uKeyIdx, PDWORD pdwKey, BYTE byLocalID);
1157 void MACvSetDefaultKeyCtl(DWORD_PTR dwIoBase, WORD wKeyCtl, UINT uEntryIdx, BYTE byLocalID);
1160 } /* End of extern "C" { */
1161 #endif /* __cplusplus */