drivers/staging/rtl8187se/r8180_rtl8225z2.c

   1 /*
   2   This is part of the rtl8180-sa2400 driver
   3   released under the GPL (See file COPYING for details).
   4   Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
   5
   6   This files contains programming code for the rtl8225
   7   radio frontend.
   8
   9   *Many* thanks to Realtek Corp. for their great support!
  10
  11 */
  12
  13 #include "r8180_hw.h"
  14 #include "r8180_rtl8225.h"
  15 #include "r8180_93cx6.h"
  16
  17 #include "ieee80211/dot11d.h"
  18
  19
  20 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
  21 {
  22         int i;
  23         u16 out, select;
  24         u8 bit;
  25         u32 bangdata = (data << 4) | (adr & 0xf);
  26         struct r8180_priv *priv = ieee80211_priv(dev);
  27
  28         out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
  29
  30         write_nic_word(dev, RFPinsEnable,
  31                 (read_nic_word(dev, RFPinsEnable) | 0x7));
  32
  33         select = read_nic_word(dev, RFPinsSelect);
  34
  35         write_nic_word(dev, RFPinsSelect, select | 0x7 |
  36                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
  37
  38         force_pci_posting(dev);
  39         udelay(10);
  40
  41         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  42
  43         force_pci_posting(dev);
  44         udelay(2);
  45
  46         write_nic_word(dev, RFPinsOutput, out);
  47
  48         force_pci_posting(dev);
  49         udelay(10);
  50
  51         for (i = 15; i >= 0; i--) {
  52                 bit = (bangdata & (1 << i)) >> i;
  53
  54                 write_nic_word(dev, RFPinsOutput, bit | out);
  55
  56                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  57                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  58
  59                 i--;
  60                 bit = (bangdata & (1 << i)) >> i;
  61
  62                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  63                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  64
  65                 write_nic_word(dev, RFPinsOutput, bit | out);
  66
  67         }
  68
  69         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  70
  71         force_pci_posting(dev);
  72         udelay(10);
  73
  74         write_nic_word(dev, RFPinsOutput, out |
  75                 ((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
  76
  77         write_nic_word(dev, RFPinsSelect, select |
  78                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
  79
  80         if (priv->card_type == USB)
  81                 mdelay(2);
  82         else
  83                 rtl8185_rf_pins_enable(dev);
  84 }
  85
  86 static const u16 rtl8225bcd_rxgain[] = {
  87         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
  88         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
  89         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
  90         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
  91         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
  92         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
  93         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
  94         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
  95         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
  96         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
  97         0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
  98         0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
  99
 100 };
 101
 102 static const u8 rtl8225_agc[] = {
 103         0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
 104         0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
 105         0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
 106         0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
 107         0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
 108         0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
 109         0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
 110         0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
 111         0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
 112         0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
 113         0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
 114         0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
 115         0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
 116         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 117         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 118         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 119 };
 120
 121 static const u8 rtl8225_gain[] = {
 122         0x23, 0x88, 0x7c, 0xa5, /* -82dBm */
 123         0x23, 0x88, 0x7c, 0xb5, /* -82dBm */
 124         0x23, 0x88, 0x7c, 0xc5, /* -82dBm */
 125         0x33, 0x80, 0x79, 0xc5, /* -78dBm */
 126         0x43, 0x78, 0x76, 0xc5, /* -74dBm */
 127         0x53, 0x60, 0x73, 0xc5, /* -70dBm */
 128         0x63, 0x58, 0x70, 0xc5, /* -66dBm */
 129 };
 130
 131 static const u8 rtl8225_tx_gain_cck_ofdm[] = {
 132         0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
 133 };
 134
 135 static const u8 rtl8225_tx_power_cck[] = {
 136         0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
 137         0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
 138         0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
 139         0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
 140         0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
 141         0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
 142 };
 143
 144 static const u8 rtl8225_tx_power_cck_ch14[] = {
 145         0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
 146         0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
 147         0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
 148         0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
 149         0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
 150         0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
 151 };
 152
 153 static const u8 rtl8225_tx_power_ofdm[] = {
 154         0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
 155 };
 156
 157 static const u32 rtl8225_chan[] = {
 158         0,
 159         0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
 160         0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
 161 };
 162
 163 static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
 164 {
 165         struct r8180_priv *priv = ieee80211_priv(dev);
 166         int GainIdx;
 167         int GainSetting;
 168         int i;
 169         u8 power;
 170         const u8 *cck_power_table;
 171         u8 max_cck_power_level;
 172         u8 max_ofdm_power_level;
 173         u8 min_ofdm_power_level;
 174         u8 cck_power_level = 0xff & priv->chtxpwr[ch];
 175         u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
 176
 177         if (priv->card_type == USB) {
 178                 max_cck_power_level = 11;
 179                 max_ofdm_power_level = 25;
 180                 min_ofdm_power_level = 10;
 181         } else {
 182                 max_cck_power_level = 35;
 183                 max_ofdm_power_level = 35;
 184                 min_ofdm_power_level = 0;
 185         }
 186
 187         if (cck_power_level > max_cck_power_level)
 188                 cck_power_level = max_cck_power_level;
 189
 190         GainIdx = cck_power_level % 6;
 191         GainSetting = cck_power_level / 6;
 192
 193         if (ch == 14)
 194                 cck_power_table = rtl8225_tx_power_cck_ch14;
 195         else
 196                 cck_power_table = rtl8225_tx_power_cck;
 197
 198         write_nic_byte(dev, TX_GAIN_CCK,
 199                        rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
 200
 201         for (i = 0; i < 8; i++) {
 202                 power = cck_power_table[GainIdx * 8 + i];
 203                 write_phy_cck(dev, 0x44 + i, power);
 204         }
 205
 206         /* FIXME Is this delay really needeed ? */
 207         force_pci_posting(dev);
 208         mdelay(1);
 209
 210         if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
 211                 ofdm_power_level = max_ofdm_power_level;
 212         else
 213                 ofdm_power_level += min_ofdm_power_level;
 214
 215         if (ofdm_power_level > 35)
 216                 ofdm_power_level = 35;
 217
 218         GainIdx = ofdm_power_level % 6;
 219         GainSetting = ofdm_power_level / 6;
 220
 221         rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
 222
 223         write_phy_ofdm(dev, 2, 0x42);
 224         write_phy_ofdm(dev, 6, 0x00);
 225         write_phy_ofdm(dev, 8, 0x00);
 226
 227         write_nic_byte(dev, TX_GAIN_OFDM,
 228                        rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
 229
 230         power = rtl8225_tx_power_ofdm[GainIdx];
 231
 232         write_phy_ofdm(dev, 5, power);
 233         write_phy_ofdm(dev, 7, power);
 234
 235         force_pci_posting(dev);
 236         mdelay(1);
 237 }
 238
 239 static const u8 rtl8225z2_threshold[] = {
 240         0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
 241 };
 242
 243 static const u8 rtl8225z2_gain_bg[] = {
 244         0x23, 0x15, 0xa5, /* -82-1dBm */
 245         0x23, 0x15, 0xb5, /* -82-2dBm */
 246         0x23, 0x15, 0xc5, /* -82-3dBm */
 247         0x33, 0x15, 0xc5, /* -78dBm */
 248         0x43, 0x15, 0xc5, /* -74dBm */
 249         0x53, 0x15, 0xc5, /* -70dBm */
 250         0x63, 0x15, 0xc5, /* -66dBm */
 251 };
 252
 253 static const u8 rtl8225z2_gain_a[] = {
 254         0x13, 0x27, 0x5a, /* -82dBm */
 255         0x23, 0x23, 0x58, /* -82dBm */
 256         0x33, 0x1f, 0x56, /* -82dBm */
 257         0x43, 0x1b, 0x54, /* -78dBm */
 258         0x53, 0x17, 0x51, /* -74dBm */
 259         0x63, 0x24, 0x4f, /* -70dBm */
 260         0x73, 0x0f, 0x4c, /* -66dBm */
 261 };
 262
 263 static const u16 rtl8225z2_rxgain[] = {
 264         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
 265         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
 266         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
 267         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
 268         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
 269         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
 270         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
 271         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
 272         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
 273         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
 274         0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
 275         0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
 276
 277 };
 278
 279 static const u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[] = {
 280         0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
 281         0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
 282         0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
 283         0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
 284         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
 285         0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
 286 };
 287
 288 static const u8 rtl8225z2_tx_power_ofdm[] = {
 289         0x42, 0x00, 0x40, 0x00, 0x40
 290 };
 291
 292 static const u8 rtl8225z2_tx_power_cck_ch14[] = {
 293         0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
 294 };
 295
 296 static const u8 rtl8225z2_tx_power_cck[] = {
 297         0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
 298 };
 299
 300 void rtl8225z2_set_gain(struct net_device *dev, short gain)
 301 {
 302         const u8 *rtl8225_gain;
 303         struct r8180_priv *priv = ieee80211_priv(dev);
 304         u8 mode = priv->ieee80211->mode;
 305
 306         if (mode == IEEE_B || mode == IEEE_G)
 307                 rtl8225_gain = rtl8225z2_gain_bg;
 308         else
 309                 rtl8225_gain = rtl8225z2_gain_a;
 310
 311         write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
 312         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
 313         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
 314         write_phy_ofdm(dev, 0x21, 0x37);
 315 }
 316
 317 static u32 read_rtl8225(struct net_device *dev, u8 adr)
 318 {
 319         u32 data2Write = ((u32)(adr & 0x1f)) << 27;
 320         u32 dataRead;
 321         u32 mask;
 322         u16 oval,oval2,oval3,tmp;
 323         int i;
 324         short bit, rw;
 325         u8 wLength = 6;
 326         u8 rLength = 12;
 327         u8 low2high = 0;
 328
 329         oval = read_nic_word(dev, RFPinsOutput);
 330         oval2 = read_nic_word(dev, RFPinsEnable);
 331         oval3 = read_nic_word(dev, RFPinsSelect);
 332
 333         write_nic_word(dev, RFPinsEnable, (oval2|0xf));
 334         write_nic_word(dev, RFPinsSelect, (oval3|0xf));
 335
 336         dataRead = 0;
 337
 338         oval &= ~0xf;
 339
 340         write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
 341
 342         write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
 343
 344         rw = 0;
 345
 346         mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
 347
 348         for (i = 0; i < wLength/2; i++) {
 349                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 350                 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
 351
 352                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 353                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 354
 355                 mask = (low2high) ? (mask<<1): (mask>>1);
 356
 357                 if (i == 2) {
 358                         rw = BB_HOST_BANG_RW;
 359                         write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 360                         write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
 361                         break;
 362                 }
 363
 364                 bit = ((data2Write&mask) != 0) ? 1: 0;
 365
 366                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 367                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 368
 369                 write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
 370
 371                 mask = (low2high) ? (mask<<1) : (mask>>1);
 372         }
 373
 374         write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
 375         mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
 376
 377         /*
 378          * We must set data pin to HW controled, otherwise RF can't driver it
 379          * and value RF register won't be able to read back properly.
 380          */
 381         write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
 382
 383         for (i = 0; i < rLength; i++) {
 384                 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
 385
 386                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 387                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 388                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 389                 tmp = read_nic_word(dev, RFPinsInput);
 390
 391                 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
 392
 393                 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
 394
 395                 mask = (low2high) ? (mask<<1) : (mask>>1);
 396         }
 397
 398         write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
 399
 400         write_nic_word(dev, RFPinsEnable, oval2);
 401         write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
 402         write_nic_word(dev, RFPinsOutput, 0x3a0);
 403
 404         return dataRead;
 405 }
 406
 407 short rtl8225_is_V_z2(struct net_device *dev)
 408 {
 409         short vz2 = 1;
 410
 411         if (read_rtl8225(dev, 8) != 0x588)
 412                 vz2 = 0;
 413         else    /* reg 9 pg 1 = 24 */
 414                 if (read_rtl8225(dev, 9) != 0x700)
 415                         vz2 = 0;
 416
 417         /* sw back to pg 0 */
 418         write_rtl8225(dev, 0, 0xb7);
 419
 420         return vz2;
 421 }
 422
 423 void rtl8225z2_rf_close(struct net_device *dev)
 424 {
 425         RF_WriteReg(dev, 0x4, 0x1f);
 426
 427         force_pci_posting(dev);
 428         mdelay(1);
 429
 430         rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
 431         rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
 432 }
 433
 434 /*
 435  * Map dBm into Tx power index according to current HW model, for example,
 436  * RF and PA, and current wireless mode.
 437  */
 438 s8 DbmToTxPwrIdx(struct r8180_priv *priv, WIRELESS_MODE WirelessMode,
 439                  s32 PowerInDbm)
 440 {
 441         bool bUseDefault = true;
 442         s8 TxPwrIdx = 0;
 443
 444         /*
 445          * OFDM Power in dBm = Index * 0.5 + 0
 446          * CCK Power in dBm = Index * 0.25 + 13
 447          */
 448         s32 tmp = 0;
 449
 450         if (WirelessMode == WIRELESS_MODE_G) {
 451                 bUseDefault = false;
 452                 tmp = (2 * PowerInDbm);
 453
 454                 if (tmp < 0)
 455                         TxPwrIdx = 0;
 456                 else if (tmp > 40) /* 40 means 20 dBm. */
 457                         TxPwrIdx = 40;
 458                 else
 459                         TxPwrIdx = (s8)tmp;
 460         } else if (WirelessMode == WIRELESS_MODE_B) {
 461                 bUseDefault = false;
 462                 tmp = (4 * PowerInDbm) - 52;
 463
 464                 if (tmp < 0)
 465                         TxPwrIdx = 0;
 466                 else if (tmp > 28) /* 28 means 20 dBm. */
 467                         TxPwrIdx = 28;
 468                 else
 469                         TxPwrIdx = (s8)tmp;
 470         }
 471
 472         /*
 473          * TRUE if we want to use a default implementation.
 474          * We shall set it to FALSE when we have exact translation formular
 475          * for target IC. 070622, by rcnjko.
 476          */
 477         if (bUseDefault) {
 478                 if (PowerInDbm < 0)
 479                         TxPwrIdx = 0;
 480                 else if (PowerInDbm > 35)
 481                         TxPwrIdx = 35;
 482                 else
 483                         TxPwrIdx = (u8)PowerInDbm;
 484         }
 485
 486         return TxPwrIdx;
 487 }
 488
 489 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
 490 {
 491         struct r8180_priv *priv = ieee80211_priv(dev);
 492         u8 max_cck_power_level;
 493         u8 max_ofdm_power_level;
 494         u8 min_ofdm_power_level;
 495         char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
 496         char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
 497
 498         if (IS_DOT11D_ENABLE(priv->ieee80211) &&
 499             IS_DOT11D_STATE_DONE(priv->ieee80211)) {
 500                 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
 501                 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
 502                 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
 503
 504                 if (cck_power_level > CckMaxPwrIdx)
 505                         cck_power_level = CckMaxPwrIdx;
 506                 if (ofdm_power_level > OfdmMaxPwrIdx)
 507                         ofdm_power_level = OfdmMaxPwrIdx;
 508         }
 509
 510         max_cck_power_level = 15;
 511         max_ofdm_power_level = 25;
 512         min_ofdm_power_level = 10;
 513
 514         if (cck_power_level > 35)
 515                 cck_power_level = 35;
 516
 517         write_nic_byte(dev, CCK_TXAGC,
 518                        (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]));
 519         force_pci_posting(dev);
 520         mdelay(1);
 521
 522         if (ofdm_power_level > 35)
 523                 ofdm_power_level = 35;
 524
 525         if (priv->up == 0) {
 526                 write_phy_ofdm(dev, 2, 0x42);
 527                 write_phy_ofdm(dev, 5, 0x00);
 528                 write_phy_ofdm(dev, 6, 0x40);
 529                 write_phy_ofdm(dev, 7, 0x00);
 530                 write_phy_ofdm(dev, 8, 0x40);
 531         }
 532
 533         write_nic_byte(dev, OFDM_TXAGC,
 534                        ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
 535
 536         if (ofdm_power_level <= 11) {
 537                 write_phy_ofdm(dev, 0x07, 0x5c);
 538                 write_phy_ofdm(dev, 0x09, 0x5c);
 539         }
 540
 541         if (ofdm_power_level <= 17) {
 542                 write_phy_ofdm(dev, 0x07, 0x54);
 543                 write_phy_ofdm(dev, 0x09, 0x54);
 544         } else {
 545                 write_phy_ofdm(dev, 0x07, 0x50);
 546                 write_phy_ofdm(dev, 0x09, 0x50);
 547         }
 548
 549         force_pci_posting(dev);
 550         mdelay(1);
 551 }
 552
 553 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
 554 {
 555         rtl8225z2_SetTXPowerLevel(dev, ch);
 556
 557         RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 558
 559         if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
 560                 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 561
 562         mdelay(1);
 563
 564         force_pci_posting(dev);
 565         mdelay(10);
 566 }
 567
 568 static void rtl8225_host_pci_init(struct net_device *dev)
 569 {
 570         write_nic_word(dev, RFPinsOutput, 0x480);
 571
 572         rtl8185_rf_pins_enable(dev);
 573
 574         write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
 575
 576         write_nic_byte(dev, GP_ENABLE, 0);
 577
 578         force_pci_posting(dev);
 579         mdelay(200);
 580
 581         /* bit 6 is for RF on/off detection */
 582         write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
 583 }
 584
 585 static void rtl8225_rf_set_chan(struct net_device *dev, short ch)
 586 {
 587         struct r8180_priv *priv = ieee80211_priv(dev);
 588         short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
 589                 ieee80211_is_54g(priv->ieee80211->current_network)) ||
 590                 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
 591
 592         rtl8225_SetTXPowerLevel(dev, ch);
 593
 594         write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
 595
 596         force_pci_posting(dev);
 597         mdelay(10);
 598
 599         if (gset) {
 600                 write_nic_byte(dev, SIFS, 0x22);
 601                 write_nic_byte(dev, DIFS, 0x14);
 602         } else {
 603                 write_nic_byte(dev, SIFS, 0x44);
 604                 write_nic_byte(dev, DIFS, 0x24);
 605         }
 606
 607         if (priv->ieee80211->state == IEEE80211_LINKED &&
 608             ieee80211_is_shortslot(priv->ieee80211->current_network))
 609                 write_nic_byte(dev, SLOT, 0x9);
 610         else
 611                 write_nic_byte(dev, SLOT, 0x14);
 612
 613         if (gset) {
 614                 write_nic_byte(dev, EIFS, 81);
 615                 write_nic_byte(dev, CW_VAL, 0x73);
 616         } else {
 617                 write_nic_byte(dev, EIFS, 81);
 618                 write_nic_byte(dev, CW_VAL, 0xa5);
 619         }
 620 }
 621
 622 void rtl8225z2_rf_init(struct net_device *dev)
 623 {
 624         struct r8180_priv *priv = ieee80211_priv(dev);
 625         int i;
 626         short channel = 1;
 627         u16     brsr;
 628         u32     data,addr;
 629
 630         priv->chan = channel;
 631
 632         if (priv->card_type != USB)
 633                 rtl8225_host_pci_init(dev);
 634
 635         write_nic_dword(dev, RF_TIMING, 0x000a8008);
 636
 637         brsr = read_nic_word(dev, BRSR);
 638
 639         write_nic_word(dev, BRSR, 0xffff);
 640
 641         write_nic_dword(dev, RF_PARA, 0x100044);
 642
 643         rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
 644         write_nic_byte(dev, CONFIG3, 0x44);
 645         rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
 646
 647         rtl8185_rf_pins_enable(dev);
 648
 649         write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
 650         write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
 651         write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
 652         write_rtl8225(dev, 0x3, 0x441); mdelay(1);
 653         write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
 654         write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
 655         write_rtl8225(dev, 0x6, 0xe6);  mdelay(1);
 656         write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel]));  mdelay(1);
 657         write_rtl8225(dev, 0x8, 0x3f);  mdelay(1);
 658         write_rtl8225(dev, 0x9, 0x335); mdelay(1);
 659         write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
 660         write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
 661         write_rtl8225(dev, 0xc, 0x850); mdelay(1);
 662         write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
 663         write_rtl8225(dev, 0xe, 0x2b);  mdelay(1);
 664         write_rtl8225(dev, 0xf, 0x114);
 665
 666         mdelay(100);
 667
 668         write_rtl8225(dev, 0x0, 0x1b7);
 669
 670         for (i = 0; i < 95; i++) {
 671                 write_rtl8225(dev, 0x1, (u8)(i + 1));
 672                 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
 673         }
 674
 675         write_rtl8225(dev, 0x3, 0x80);
 676         write_rtl8225(dev, 0x5, 0x4);
 677
 678         write_rtl8225(dev, 0x0, 0xb7);
 679
 680         write_rtl8225(dev, 0x2, 0xc4d);
 681
 682         if (priv->card_type == USB) {
 683                 mdelay(200);
 684
 685                 write_rtl8225(dev, 0x2, 0x44d);
 686                 mdelay(100);
 687         }
 688
 689         /* FIXME!! rtl8187 we have to check if calibrarion
 690          * is successful and eventually cal. again (repeat
 691          * the two write on reg 2)
 692          */
 693         data = read_rtl8225(dev, 6);
 694         if (!(data & 0x00000080)) {
 695                 write_rtl8225(dev, 0x02, 0x0c4d);
 696                 force_pci_posting(dev); mdelay(200);
 697                 write_rtl8225(dev, 0x02, 0x044d);
 698                 force_pci_posting(dev); mdelay(100);
 699                 data = read_rtl8225(dev, 6);
 700                 if (!(data & 0x00000080))
 701                         DMESGW("RF Calibration Failed!!!!\n");
 702         }
 703
 704         mdelay(200);
 705
 706         write_rtl8225(dev, 0x0, 0x2bf);
 707
 708         if (priv->card_type != USB)
 709                 rtl8185_rf_pins_enable(dev);
 710
 711         for (i = 0; i < 128; i++) {
 712                 data = rtl8225_agc[i];
 713
 714                 addr = i + 0x80; /* enable writing AGC table */
 715                 write_phy_ofdm(dev, 0xb, data);
 716                 mdelay(1);
 717
 718                 write_phy_ofdm(dev, 0xa, addr);
 719                 mdelay(1);
 720         }
 721
 722         force_pci_posting(dev);
 723         mdelay(1);
 724
 725         write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
 726         write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
 727         write_phy_ofdm(dev, 0x02, ((priv->card_type == USB) ? 0x42 : 0x62)); mdelay(1);
 728         write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
 729         write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
 730         write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
 731         write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
 732         write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
 733         write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
 734         write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
 735         write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
 736         write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
 737         write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
 738         write_phy_ofdm(dev, 0x0d, 0x43);
 739         write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
 740         write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
 741         write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
 742         write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
 743         write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
 744         write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
 745         write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
 746         write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
 747         write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
 748         write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
 749         write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
 750         write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
 751         write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
 752         write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
 753         write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
 754         write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
 755         write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
 756         write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
 757         write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
 758         write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
 759         write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
 760         write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
 761         write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
 762         write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
 763         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
 764         write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
 765
 766         rtl8225z2_set_gain(dev,4);
 767
 768         write_phy_cck(dev, 0x0, 0x98); mdelay(1);
 769         write_phy_cck(dev, 0x3, 0x20); mdelay(1);
 770         write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
 771         write_phy_cck(dev, 0x5, 0x12); mdelay(1);
 772         write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
 773         write_phy_cck(dev, 0x7, 0x78); mdelay(1);
 774         write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
 775         write_phy_cck(dev, 0x10, ((priv->card_type == USB) ? 0x9b: 0x93)); mdelay(1);
 776         write_phy_cck(dev, 0x11, 0x88); mdelay(1);
 777         write_phy_cck(dev, 0x12, 0x47); mdelay(1);
 778         write_phy_cck(dev, 0x13, 0xd0);
 779         write_phy_cck(dev, 0x19, 0x00);
 780         write_phy_cck(dev, 0x1a, 0xa0);
 781         write_phy_cck(dev, 0x1b, 0x08);
 782         write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
 783         write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
 784         write_phy_cck(dev, 0x42, 0x15); mdelay(1);
 785         write_phy_cck(dev, 0x43, 0x18); mdelay(1);
 786         write_phy_cck(dev, 0x44, 0x36); mdelay(1);
 787         write_phy_cck(dev, 0x45, 0x35); mdelay(1);
 788         write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
 789         write_phy_cck(dev, 0x47, 0x25); mdelay(1);
 790         write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
 791         write_phy_cck(dev, 0x49, 0x12); mdelay(1);
 792         write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
 793         write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
 794         write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
 795
 796         write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
 797
 798         rtl8225z2_SetTXPowerLevel(dev, channel);
 799
 800         /* RX antenna default to A */
 801         write_phy_cck(dev, 0x11, 0x9b); mdelay(1);              /* B: 0xDB */
 802         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);             /* B: 0x10 */
 803
 804         rtl8185_tx_antenna(dev, 0x03);                          /* B: 0x00 */
 805
 806         /* switch to high-speed 3-wire
 807          * last digit. 2 for both cck and ofdm
 808          */
 809         if (priv->card_type == USB)
 810                 write_nic_dword(dev, 0x94, 0x3dc00002);
 811         else {
 812                 write_nic_dword(dev, 0x94, 0x15c00002);
 813                 rtl8185_rf_pins_enable(dev);
 814         }
 815
 816         rtl8225_rf_set_chan(dev, priv->chan);
 817 }
 818
 819 void rtl8225z2_rf_set_mode(struct net_device *dev)
 820 {
 821         struct r8180_priv *priv = ieee80211_priv(dev);
 822
 823         if (priv->ieee80211->mode == IEEE_A) {
 824                 write_rtl8225(dev, 0x5, 0x1865);
 825                 write_nic_dword(dev, RF_PARA, 0x10084);
 826                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 827                 write_phy_ofdm(dev, 0x0, 0x0);
 828                 write_phy_ofdm(dev, 0xa, 0x6);
 829                 write_phy_ofdm(dev, 0xb, 0x99);
 830                 write_phy_ofdm(dev, 0xf, 0x20);
 831                 write_phy_ofdm(dev, 0x11, 0x7);
 832
 833                 rtl8225z2_set_gain(dev,4);
 834
 835                 write_phy_ofdm(dev,0x15, 0x40);
 836                 write_phy_ofdm(dev,0x17, 0x40);
 837
 838                 write_nic_dword(dev, 0x94,0x10000000);
 839         } else {
 840                 write_rtl8225(dev, 0x5, 0x1864);
 841                 write_nic_dword(dev, RF_PARA, 0x10044);
 842                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 843                 write_phy_ofdm(dev, 0x0, 0x1);
 844                 write_phy_ofdm(dev, 0xa, 0x6);
 845                 write_phy_ofdm(dev, 0xb, 0x99);
 846                 write_phy_ofdm(dev, 0xf, 0x20);
 847                 write_phy_ofdm(dev, 0x11, 0x7);
 848
 849                 rtl8225z2_set_gain(dev,4);
 850
 851                 write_phy_ofdm(dev,0x15, 0x40);
 852                 write_phy_ofdm(dev,0x17, 0x40);
 853
 854                 write_nic_dword(dev, 0x94,0x04000002);
 855         }
 856 }
 857
 858 #define MAX_DOZE_WAITING_TIMES_85B              20
 859 #define MAX_POLLING_24F_TIMES_87SE              10
 860 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE        5
 861
 862 bool SetZebraRFPowerState8185(struct net_device *dev,
 863                               RT_RF_POWER_STATE eRFPowerState)
 864 {
 865         struct r8180_priv *priv = ieee80211_priv(dev);
 866         u8                      btCR9346, btConfig3;
 867         bool bActionAllowed = true, bTurnOffBB = true;
 868         u8                      u1bTmp;
 869         int                     i;
 870         bool            bResult = true;
 871         u8                      QueueID;
 872
 873         if (priv->SetRFPowerStateInProgress == true)
 874                 return false;
 875
 876         priv->SetRFPowerStateInProgress = true;
 877
 878         btCR9346 = read_nic_byte(dev, CR9346);
 879         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
 880
 881         btConfig3 = read_nic_byte(dev, CONFIG3);
 882         write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En));
 883
 884         switch (priv->rf_chip) {
 885         case RF_ZEBRA2:
 886                 switch (eRFPowerState) {
 887                 case eRfOn:
 888                         RF_WriteReg(dev,0x4,0x9FF);
 889
 890                         write_nic_dword(dev, ANAPARAM, ANAPARM_ON);
 891                         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ON);
 892
 893                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
 894
 895                         /* turn on CCK and OFDM */
 896                         u1bTmp = read_nic_byte(dev, 0x24E);
 897                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
 898                         break;
 899                 case eRfSleep:
 900                         break;
 901                 case eRfOff:
 902                         break;
 903                 default:
 904                         bResult = false;
 905                         break;
 906                 }
 907                 break;
 908         case RF_ZEBRA4:
 909                 switch (eRFPowerState) {
 910                 case eRfOn:
 911                         write_nic_word(dev, 0x37C, 0x00EC);
 912
 913                         /* turn on AFE */
 914                         write_nic_byte(dev, 0x54, 0x00);
 915                         write_nic_byte(dev, 0x62, 0x00);
 916
 917                         /* turn on RF */
 918                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 919                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 920
 921                         /* turn on RF again */
 922                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 923                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 924
 925                         /* turn on BB */
 926                         write_phy_ofdm(dev,0x10,0x40);
 927                         write_phy_ofdm(dev,0x12,0x40);
 928
 929                         /* Avoid power down at init time. */
 930                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
 931
 932                         u1bTmp = read_nic_byte(dev, 0x24E);
 933                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
 934                         break;
 935                 case eRfSleep:
 936                         for (QueueID = 0, i = 0; QueueID < 6;) {
 937                                 if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) {
 938                                         QueueID++;
 939                                         continue;
 940                                 } else {
 941                                         priv->TxPollingTimes ++;
 942                                         if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 943                                                 bActionAllowed = false;
 944                                                 break;
 945                                         } else
 946                                                 udelay(10);
 947                                 }
 948                         }
 949
 950                         if (bActionAllowed) {
 951                                 /* turn off BB RXIQ matrix to cut off rx signal */
 952                                 write_phy_ofdm(dev, 0x10, 0x00);
 953                                 write_phy_ofdm(dev, 0x12, 0x00);
 954
 955                                 /* turn off RF */
 956                                 RF_WriteReg(dev, 0x4, 0x0000);
 957                                 RF_WriteReg(dev, 0x0, 0x0000);
 958
 959                                 /* turn off AFE except PLL */
 960                                 write_nic_byte(dev, 0x62, 0xff);
 961                                 write_nic_byte(dev, 0x54, 0xec);
 962
 963                                 mdelay(1);
 964
 965                                 {
 966                                         int i = 0;
 967                                         while (true) {
 968                                                 u8 tmp24F = read_nic_byte(dev, 0x24f);
 969
 970                                                 if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
 971                                                         bTurnOffBB = true;
 972                                                         break;
 973                                                 } else {
 974                                                         udelay(10);
 975                                                         i++;
 976                                                         priv->TxPollingTimes++;
 977
 978                                                         if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 979                                                                 bTurnOffBB = false;
 980                                                                 break;
 981                                                         } else
 982                                                                 udelay(10);
 983                                                 }
 984                                         }
 985                                 }
 986
 987                                 if (bTurnOffBB) {
 988                                         /* turn off BB */
 989                                         u1bTmp = read_nic_byte(dev, 0x24E);
 990                                         write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
 991
 992                                         /* turn off AFE PLL */
 993                                         write_nic_byte(dev, 0x54, 0xFC);
 994                                         write_nic_word(dev, 0x37C, 0x00FC);
 995                                 }
 996                         }
 997                         break;
 998                 case eRfOff:
 999                         for (QueueID = 0, i = 0; QueueID < 6;) {
1000                                 if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) {
1001                                         QueueID++;
1002                                         continue;
1003                                 } else {
1004                                         udelay(10);
1005                                         i++;
1006                                 }
1007
1008                                 if (i >= MAX_DOZE_WAITING_TIMES_85B)
1009                                         break;
1010                         }
1011
1012                         /* turn off BB RXIQ matrix to cut off rx signal */
1013                         write_phy_ofdm(dev, 0x10, 0x00);
1014                         write_phy_ofdm(dev, 0x12, 0x00);
1015
1016                         /* turn off RF */
1017                         RF_WriteReg(dev, 0x4, 0x0000);
1018                         RF_WriteReg(dev, 0x0, 0x0000);
1019
1020                         /* turn off AFE except PLL */
1021                         write_nic_byte(dev, 0x62, 0xff);
1022                         write_nic_byte(dev, 0x54, 0xec);
1023
1024                         mdelay(1);
1025
1026                         {
1027                                 int i = 0;
1028
1029                                 while (true)
1030                                 {
1031                                         u8 tmp24F = read_nic_byte(dev, 0x24f);
1032
1033                                         if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
1034                                                 bTurnOffBB = true;
1035                                                 break;
1036                                         } else {
1037                                                 bTurnOffBB = false;
1038                                                 udelay(10);
1039                                                 i++;
1040                                         }
1041
1042                                         if (i > MAX_POLLING_24F_TIMES_87SE)
1043                                                 break;
1044                                 }
1045                         }
1046
1047                         if (bTurnOffBB) {
1048                                 /* turn off BB */
1049                                 u1bTmp = read_nic_byte(dev, 0x24E);
1050                                 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
1051
1052                                 /* turn off AFE PLL (80M) */
1053                                 write_nic_byte(dev, 0x54, 0xFC);
1054                                 write_nic_word(dev, 0x37C, 0x00FC);
1055                         }
1056                         break;
1057                 default:
1058                         bResult = false;
1059                         printk("SetZebraRFPowerState8185(): unknown state to set: 0x%X!!!\n", eRFPowerState);
1060                         break;
1061                 }
1062                 break;
1063         }
1064
1065         btConfig3 &= ~(CONFIG3_PARM_En);
1066         write_nic_byte(dev, CONFIG3, btConfig3);
1067
1068         btCR9346 &= ~(0xC0);
1069         write_nic_byte(dev, CR9346, btCR9346);
1070
1071         if (bResult && bActionAllowed)
1072                 priv->eRFPowerState = eRFPowerState;
1073
1074         priv->SetRFPowerStateInProgress = false;
1075
1076         return bResult && bActionAllowed;
1077 }
1078
1079 void rtl8225z4_rf_sleep(struct net_device *dev)
1080 {
1081         MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1082 }
1083
1084 void rtl8225z4_rf_wakeup(struct net_device *dev)
1085 {
1086         MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1087 }