drivers/staging/rt3090/rtmp_mac.h

   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27         Module Name:
  28         rtmp_mac.h
  29
  30         Abstract:
  31         Ralink Wireless Chip MAC related definition & structures
  32
  33         Revision History:
  34         Who                     When              What
  35         --------        ----------        ----------------------------------------------
  36 */
  37
  38 #ifndef __RTMP_MAC_H__
  39 #define __RTMP_MAC_H__
  40
  41
  42
  43 // =================================================================================
  44 // TX / RX ring descriptor format
  45 // =================================================================================
  46
  47 // the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
  48 // MAC block use this TXINFO to control the transmission behavior of this frame.
  49 #define FIFO_MGMT                 0
  50 #define FIFO_HCCA                 1
  51 #define FIFO_EDCA                 2
  52
  53
  54 //
  55 // TXD Wireless Information format for Tx ring and Mgmt Ring
  56 //
  57 //txop : for txop mode
  58 // 0:txop for the MPDU frame will be handles by ASIC by register
  59 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
  60 #ifdef RT_BIG_ENDIAN
  61 typedef struct  PACKED _TXWI_STRUC {
  62         // Word 0
  63         UINT32          PHYMODE:2;
  64         UINT32          TxBF:1; // 3*3
  65         UINT32          rsv2:1;
  66 //      UINT32          rsv2:2;
  67         UINT32          Ifs:1;  //
  68         UINT32          STBC:2; //channel bandwidth 20MHz or 40 MHz
  69         UINT32          ShortGI:1;
  70         UINT32          BW:1;   //channel bandwidth 20MHz or 40 MHz
  71         UINT32          MCS:7;
  72
  73         UINT32          rsv:6;
  74         UINT32          txop:2; //tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
  75         UINT32          MpduDensity:3;
  76         UINT32          AMPDU:1;
  77
  78         UINT32          TS:1;
  79         UINT32          CFACK:1;
  80         UINT32          MIMOps:1;       // the remote peer is in dynamic MIMO-PS mode
  81         UINT32          FRAG:1;         // 1 to inform TKIP engine this is a fragment.
  82         // Word 1
  83         UINT32          PacketId:4;
  84         UINT32          MPDUtotalByteCount:12;
  85         UINT32          WirelessCliID:8;
  86         UINT32          BAWinSize:6;
  87         UINT32          NSEQ:1;
  88         UINT32          ACK:1;
  89         // Word 2
  90         UINT32          IV;
  91         // Word 3
  92         UINT32          EIV;
  93 }       TXWI_STRUC, *PTXWI_STRUC;
  94 #else
  95 typedef struct  PACKED _TXWI_STRUC {
  96         // Word 0
  97         // ex: 00 03 00 40 means txop = 3, PHYMODE = 1
  98         UINT32          FRAG:1;         // 1 to inform TKIP engine this is a fragment.
  99         UINT32          MIMOps:1;       // the remote peer is in dynamic MIMO-PS mode
 100         UINT32          CFACK:1;
 101         UINT32          TS:1;
 102
 103         UINT32          AMPDU:1;
 104         UINT32          MpduDensity:3;
 105         UINT32          txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
 106         UINT32          rsv:6;
 107
 108         UINT32          MCS:7;
 109         UINT32          BW:1;   //channel bandwidth 20MHz or 40 MHz
 110         UINT32          ShortGI:1;
 111         UINT32          STBC:2; // 1: STBC support MCS =0-7,   2,3 : RESERVE
 112         UINT32          Ifs:1;  //
 113 //      UINT32          rsv2:2; //channel bandwidth 20MHz or 40 MHz
 114         UINT32          rsv2:1;
 115         UINT32          TxBF:1; // 3*3
 116         UINT32          PHYMODE:2;
 117         // Word1
 118         // ex:  1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38
 119         UINT32          ACK:1;
 120         UINT32          NSEQ:1;
 121         UINT32          BAWinSize:6;
 122         UINT32          WirelessCliID:8;
 123         UINT32          MPDUtotalByteCount:12;
 124         UINT32          PacketId:4;
 125         //Word2
 126         UINT32          IV;
 127         //Word3
 128         UINT32          EIV;
 129 }       TXWI_STRUC, *PTXWI_STRUC;
 130 #endif
 131
 132
 133 //
 134 // RXWI wireless information format, in PBF. invisible in driver.
 135 //
 136 #ifdef RT_BIG_ENDIAN
 137 typedef struct  PACKED _RXWI_STRUC {
 138         // Word 0
 139         UINT32          TID:4;
 140         UINT32          MPDUtotalByteCount:12;
 141         UINT32          UDF:3;
 142         UINT32          BSSID:3;
 143         UINT32          KeyIndex:2;
 144         UINT32          WirelessCliID:8;
 145         // Word 1
 146         UINT32          PHYMODE:2;              // 1: this RX frame is unicast to me
 147         UINT32          rsv:3;
 148         UINT32          STBC:2;
 149         UINT32          ShortGI:1;
 150         UINT32          BW:1;
 151         UINT32          MCS:7;
 152         UINT32          SEQUENCE:12;
 153         UINT32          FRAG:4;
 154         // Word 2
 155         UINT32          rsv1:8;
 156         UINT32          RSSI2:8;
 157         UINT32          RSSI1:8;
 158         UINT32          RSSI0:8;
 159         // Word 3
 160         /*UINT32                rsv2:16;*/
 161         UINT32          rsv2:8;
 162         UINT32          FOFFSET:8;      // RT35xx
 163         UINT32          SNR1:8;
 164         UINT32          SNR0:8;
 165 }       RXWI_STRUC, *PRXWI_STRUC;
 166 #else
 167 typedef struct  PACKED _RXWI_STRUC {
 168         // Word 0
 169         UINT32          WirelessCliID:8;
 170         UINT32          KeyIndex:2;
 171         UINT32          BSSID:3;
 172         UINT32          UDF:3;
 173         UINT32          MPDUtotalByteCount:12;
 174         UINT32          TID:4;
 175         // Word 1
 176         UINT32          FRAG:4;
 177         UINT32          SEQUENCE:12;
 178         UINT32          MCS:7;
 179         UINT32          BW:1;
 180         UINT32          ShortGI:1;
 181         UINT32          STBC:2;
 182         UINT32          rsv:3;
 183         UINT32          PHYMODE:2;              // 1: this RX frame is unicast to me
 184         //Word2
 185         UINT32          RSSI0:8;
 186         UINT32          RSSI1:8;
 187         UINT32          RSSI2:8;
 188         UINT32          rsv1:8;
 189         //Word3
 190         UINT32          SNR0:8;
 191         UINT32          SNR1:8;
 192         UINT32          FOFFSET:8;      // RT35xx
 193         UINT32          rsv2:8;
 194         /*UINT32                rsv2:16;*/
 195 }       RXWI_STRUC, *PRXWI_STRUC;
 196 #endif
 197
 198
 199 // =================================================================================
 200 // Register format
 201 // =================================================================================
 202
 203
 204 //
 205 // SCH/DMA registers - base address 0x0200
 206 //
 207 // INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
 208 //
 209 #define DMA_CSR0                0x200
 210 #define INT_SOURCE_CSR          0x200
 211 #ifdef RT_BIG_ENDIAN
 212 typedef union   _INT_SOURCE_CSR_STRUC   {
 213         struct  {
 214 #ifdef TONE_RADAR_DETECT_SUPPORT
 215                 UINT32                  :11;
 216                 UINT32                  RadarINT:1;
 217                 UINT32          rsv:2;
 218 #else // original source code
 219                 UINT32          :14;
 220 #endif // TONE_RADAR_DETECT_SUPPORT //
 221                 UINT32          TxCoherent:1;
 222                 UINT32          RxCoherent:1;
 223                 UINT32          GPTimer:1;
 224                 UINT32          AutoWakeup:1;//bit14
 225                 UINT32          TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
 226                 UINT32          PreTBTT:1;
 227                 UINT32          TBTTInt:1;
 228                 UINT32          RxTxCoherent:1;
 229                 UINT32          MCUCommandINT:1;
 230                 UINT32          MgmtDmaDone:1;
 231                 UINT32          HccaDmaDone:1;
 232                 UINT32          Ac3DmaDone:1;
 233                 UINT32          Ac2DmaDone:1;
 234                 UINT32          Ac1DmaDone:1;
 235                 UINT32          Ac0DmaDone:1;
 236                 UINT32          RxDone:1;
 237                 UINT32          TxDelayINT:1;   //delayed interrupt, not interrupt until several int or time limit hit
 238                 UINT32          RxDelayINT:1; //dealyed interrupt
 239         }       field;
 240         UINT32                  word;
 241 }       INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
 242 #else
 243 typedef union   _INT_SOURCE_CSR_STRUC   {
 244         struct  {
 245                 UINT32          RxDelayINT:1;
 246                 UINT32          TxDelayINT:1;
 247                 UINT32          RxDone:1;
 248                 UINT32          Ac0DmaDone:1;//4
 249                 UINT32          Ac1DmaDone:1;
 250                 UINT32          Ac2DmaDone:1;
 251                 UINT32          Ac3DmaDone:1;
 252                 UINT32          HccaDmaDone:1; // bit7
 253                 UINT32          MgmtDmaDone:1;
 254                 UINT32          MCUCommandINT:1;//bit 9
 255                 UINT32          RxTxCoherent:1;
 256                 UINT32          TBTTInt:1;
 257                 UINT32          PreTBTT:1;
 258                 UINT32          TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
 259                 UINT32          AutoWakeup:1;//bit14
 260                 UINT32          GPTimer:1;
 261                 UINT32          RxCoherent:1;//bit16
 262                 UINT32          TxCoherent:1;
 263 #ifdef TONE_RADAR_DETECT_SUPPORT
 264                 UINT32          rsv:2;
 265                 UINT32                  RadarINT:1;
 266                 UINT32                  :11;
 267 #else
 268                 UINT32          :14;
 269 #endif // TONE_RADAR_DETECT_SUPPORT //
 270         }       field;
 271         UINT32                  word;
 272 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
 273 #endif
 274
 275 //
 276 // INT_MASK_CSR:   Interrupt MASK register.   1: the interrupt is mask OFF
 277 //
 278 #define INT_MASK_CSR        0x204
 279 #ifdef RT_BIG_ENDIAN
 280 typedef union   _INT_MASK_CSR_STRUC     {
 281         struct  {
 282                 UINT32          TxCoherent:1;
 283                 UINT32          RxCoherent:1;
 284 #ifdef TONE_RADAR_DETECT_SUPPORT
 285                 UINT32                  :9;
 286                 UINT32                  RadarINT:1;
 287                 UINT32          rsv:10;
 288 #else
 289                 UINT32          :20;
 290 #endif // TONE_RADAR_DETECT_SUPPORT //
 291                 UINT32          MCUCommandINT:1;
 292                 UINT32          MgmtDmaDone:1;
 293                 UINT32          HccaDmaDone:1;
 294                 UINT32          Ac3DmaDone:1;
 295                 UINT32          Ac2DmaDone:1;
 296                 UINT32          Ac1DmaDone:1;
 297                 UINT32          Ac0DmaDone:1;
 298                 UINT32          RxDone:1;
 299                 UINT32          TxDelay:1;
 300                 UINT32          RXDelay_INT_MSK:1;
 301         }       field;
 302         UINT32                  word;
 303 }INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
 304 #else
 305 typedef union   _INT_MASK_CSR_STRUC     {
 306         struct  {
 307                 UINT32          RXDelay_INT_MSK:1;
 308                 UINT32          TxDelay:1;
 309                 UINT32          RxDone:1;
 310                 UINT32          Ac0DmaDone:1;
 311                 UINT32          Ac1DmaDone:1;
 312                 UINT32          Ac2DmaDone:1;
 313                 UINT32          Ac3DmaDone:1;
 314                 UINT32          HccaDmaDone:1;
 315                 UINT32          MgmtDmaDone:1;
 316                 UINT32          MCUCommandINT:1;
 317 #ifdef TONE_RADAR_DETECT_SUPPORT
 318                 UINT32          rsv:10;
 319                 UINT32                  RadarINT:1;
 320                 UINT32                  :9;
 321 #else
 322                 UINT32          :20;
 323 #endif // TONE_RADAR_DETECT_SUPPORT //
 324                 UINT32          RxCoherent:1;
 325                 UINT32          TxCoherent:1;
 326         }       field;
 327         UINT32                  word;
 328 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
 329 #endif
 330
 331 #define WPDMA_GLO_CFG   0x208
 332 #ifdef RT_BIG_ENDIAN
 333 typedef union   _WPDMA_GLO_CFG_STRUC    {
 334         struct  {
 335                 UINT32          HDR_SEG_LEN:16;
 336                 UINT32          RXHdrScater:8;
 337                 UINT32          BigEndian:1;
 338                 UINT32          EnTXWriteBackDDONE:1;
 339                 UINT32          WPDMABurstSIZE:2;
 340                 UINT32          RxDMABusy:1;
 341                 UINT32          EnableRxDMA:1;
 342                 UINT32          TxDMABusy:1;
 343                 UINT32          EnableTxDMA:1;
 344         }       field;
 345         UINT32                  word;
 346 }WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
 347 #else
 348 typedef union   _WPDMA_GLO_CFG_STRUC    {
 349         struct  {
 350                 UINT32          EnableTxDMA:1;
 351                 UINT32          TxDMABusy:1;
 352                 UINT32          EnableRxDMA:1;
 353                 UINT32          RxDMABusy:1;
 354                 UINT32          WPDMABurstSIZE:2;
 355                 UINT32          EnTXWriteBackDDONE:1;
 356                 UINT32          BigEndian:1;
 357                 UINT32          RXHdrScater:8;
 358                 UINT32          HDR_SEG_LEN:16;
 359         }       field;
 360         UINT32                  word;
 361 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
 362 #endif
 363
 364 #define WPDMA_RST_IDX   0x20c
 365 #ifdef RT_BIG_ENDIAN
 366 typedef union   _WPDMA_RST_IDX_STRUC    {
 367         struct  {
 368                 UINT32          :15;
 369                 UINT32          RST_DRX_IDX0:1;
 370                 UINT32          rsv:10;
 371                 UINT32          RST_DTX_IDX5:1;
 372                 UINT32          RST_DTX_IDX4:1;
 373                 UINT32          RST_DTX_IDX3:1;
 374                 UINT32          RST_DTX_IDX2:1;
 375                 UINT32          RST_DTX_IDX1:1;
 376                 UINT32          RST_DTX_IDX0:1;
 377         }       field;
 378         UINT32                  word;
 379 }WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
 380 #else
 381 typedef union   _WPDMA_RST_IDX_STRUC    {
 382         struct  {
 383                 UINT32          RST_DTX_IDX0:1;
 384                 UINT32          RST_DTX_IDX1:1;
 385                 UINT32          RST_DTX_IDX2:1;
 386                 UINT32          RST_DTX_IDX3:1;
 387                 UINT32          RST_DTX_IDX4:1;
 388                 UINT32          RST_DTX_IDX5:1;
 389                 UINT32          rsv:10;
 390                 UINT32          RST_DRX_IDX0:1;
 391                 UINT32          :15;
 392         }       field;
 393         UINT32                  word;
 394 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
 395 #endif
 396 #define DELAY_INT_CFG  0x0210
 397 #ifdef RT_BIG_ENDIAN
 398 typedef union   _DELAY_INT_CFG_STRUC    {
 399         struct  {
 400                 UINT32          TXDLY_INT_EN:1;
 401                 UINT32          TXMAX_PINT:7;
 402                 UINT32          TXMAX_PTIME:8;
 403                 UINT32          RXDLY_INT_EN:1;
 404                 UINT32          RXMAX_PINT:7;
 405                 UINT32          RXMAX_PTIME:8;
 406         }       field;
 407         UINT32                  word;
 408 }DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
 409 #else
 410 typedef union   _DELAY_INT_CFG_STRUC    {
 411         struct  {
 412                 UINT32          RXMAX_PTIME:8;
 413                 UINT32          RXMAX_PINT:7;
 414                 UINT32          RXDLY_INT_EN:1;
 415                 UINT32          TXMAX_PTIME:8;
 416                 UINT32          TXMAX_PINT:7;
 417                 UINT32          TXDLY_INT_EN:1;
 418         }       field;
 419         UINT32                  word;
 420 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
 421 #endif
 422 #define WMM_AIFSN_CFG   0x0214
 423 #ifdef RT_BIG_ENDIAN
 424 typedef union   _AIFSN_CSR_STRUC        {
 425         struct  {
 426             UINT32   Rsv:16;
 427             UINT32   Aifsn3:4;       // for AC_VO
 428             UINT32   Aifsn2:4;       // for AC_VI
 429             UINT32   Aifsn1:4;       // for AC_BK
 430             UINT32   Aifsn0:4;       // for AC_BE
 431         }       field;
 432         UINT32                  word;
 433 }       AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
 434 #else
 435 typedef union   _AIFSN_CSR_STRUC        {
 436         struct  {
 437             UINT32   Aifsn0:4;       // for AC_BE
 438             UINT32   Aifsn1:4;       // for AC_BK
 439             UINT32   Aifsn2:4;       // for AC_VI
 440             UINT32   Aifsn3:4;       // for AC_VO
 441             UINT32   Rsv:16;
 442         }       field;
 443         UINT32                  word;
 444 }       AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
 445 #endif
 446 //
 447 // CWMIN_CSR: CWmin for each EDCA AC
 448 //
 449 #define WMM_CWMIN_CFG   0x0218
 450 #ifdef RT_BIG_ENDIAN
 451 typedef union   _CWMIN_CSR_STRUC        {
 452         struct  {
 453             UINT32   Rsv:16;
 454             UINT32   Cwmin3:4;       // for AC_VO
 455             UINT32   Cwmin2:4;       // for AC_VI
 456             UINT32   Cwmin1:4;       // for AC_BK
 457             UINT32   Cwmin0:4;       // for AC_BE
 458         }       field;
 459         UINT32                  word;
 460 }       CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
 461 #else
 462 typedef union   _CWMIN_CSR_STRUC        {
 463         struct  {
 464             UINT32   Cwmin0:4;       // for AC_BE
 465             UINT32   Cwmin1:4;       // for AC_BK
 466             UINT32   Cwmin2:4;       // for AC_VI
 467             UINT32   Cwmin3:4;       // for AC_VO
 468             UINT32   Rsv:16;
 469         }       field;
 470         UINT32                  word;
 471 }       CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
 472 #endif
 473
 474 //
 475 // CWMAX_CSR: CWmin for each EDCA AC
 476 //
 477 #define WMM_CWMAX_CFG   0x021c
 478 #ifdef RT_BIG_ENDIAN
 479 typedef union   _CWMAX_CSR_STRUC        {
 480         struct  {
 481             UINT32   Rsv:16;
 482             UINT32   Cwmax3:4;       // for AC_VO
 483             UINT32   Cwmax2:4;       // for AC_VI
 484             UINT32   Cwmax1:4;       // for AC_BK
 485             UINT32   Cwmax0:4;       // for AC_BE
 486         }       field;
 487         UINT32                  word;
 488 }       CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
 489 #else
 490 typedef union   _CWMAX_CSR_STRUC        {
 491         struct  {
 492             UINT32   Cwmax0:4;       // for AC_BE
 493             UINT32   Cwmax1:4;       // for AC_BK
 494             UINT32   Cwmax2:4;       // for AC_VI
 495             UINT32   Cwmax3:4;       // for AC_VO
 496             UINT32   Rsv:16;
 497         }       field;
 498         UINT32                  word;
 499 }       CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
 500 #endif
 501
 502
 503 //
 504 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
 505 //
 506 #define WMM_TXOP0_CFG    0x0220
 507 #ifdef RT_BIG_ENDIAN
 508 typedef union   _AC_TXOP_CSR0_STRUC     {
 509         struct  {
 510             USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
 511             USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
 512         }       field;
 513         UINT32                  word;
 514 }       AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
 515 #else
 516 typedef union   _AC_TXOP_CSR0_STRUC     {
 517         struct  {
 518             USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
 519             USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
 520         }       field;
 521         UINT32                  word;
 522 }       AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
 523 #endif
 524
 525 //
 526 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
 527 //
 528 #define WMM_TXOP1_CFG    0x0224
 529 #ifdef RT_BIG_ENDIAN
 530 typedef union   _AC_TXOP_CSR1_STRUC     {
 531         struct  {
 532             USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
 533             USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
 534         }       field;
 535         UINT32                  word;
 536 }       AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
 537 #else
 538 typedef union   _AC_TXOP_CSR1_STRUC     {
 539         struct  {
 540             USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
 541             USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
 542         }       field;
 543         UINT32                  word;
 544 }       AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
 545 #endif
 546
 547
 548 #define RINGREG_DIFF                    0x10
 549 #define GPIO_CTRL_CFG    0x0228 //MAC_CSR13
 550 #define MCU_CMD_CFG    0x022c
 551 #define TX_BASE_PTR0     0x0230 //AC_BK base address
 552 #define TX_MAX_CNT0      0x0234
 553 #define TX_CTX_IDX0       0x0238
 554 #define TX_DTX_IDX0      0x023c
 555 #define TX_BASE_PTR1     0x0240         //AC_BE base address
 556 #define TX_MAX_CNT1      0x0244
 557 #define TX_CTX_IDX1       0x0248
 558 #define TX_DTX_IDX1      0x024c
 559 #define TX_BASE_PTR2     0x0250         //AC_VI base address
 560 #define TX_MAX_CNT2      0x0254
 561 #define TX_CTX_IDX2       0x0258
 562 #define TX_DTX_IDX2      0x025c
 563 #define TX_BASE_PTR3     0x0260         //AC_VO base address
 564 #define TX_MAX_CNT3      0x0264
 565 #define TX_CTX_IDX3       0x0268
 566 #define TX_DTX_IDX3      0x026c
 567 #define TX_BASE_PTR4     0x0270         //HCCA base address
 568 #define TX_MAX_CNT4      0x0274
 569 #define TX_CTX_IDX4       0x0278
 570 #define TX_DTX_IDX4      0x027c
 571 #define TX_BASE_PTR5     0x0280         //MGMT base address
 572 #define  TX_MAX_CNT5     0x0284
 573 #define TX_CTX_IDX5       0x0288
 574 #define TX_DTX_IDX5      0x028c
 575 #define TX_MGMTMAX_CNT      TX_MAX_CNT5
 576 #define TX_MGMTCTX_IDX       TX_CTX_IDX5
 577 #define TX_MGMTDTX_IDX      TX_DTX_IDX5
 578 #define RX_BASE_PTR     0x0290  //RX base address
 579 #define RX_MAX_CNT      0x0294
 580 #define RX_CRX_IDX       0x0298
 581 #define RX_DRX_IDX      0x029c
 582
 583
 584 #define USB_DMA_CFG      0x02a0
 585 #ifdef RT_BIG_ENDIAN
 586 typedef union   _USB_DMA_CFG_STRUC      {
 587         struct  {
 588             UINT32  TxBusy:1;           //USB DMA TX FSM busy . debug only
 589             UINT32  RxBusy:1;        //USB DMA RX FSM busy . debug only
 590             UINT32  EpoutValid:6;        //OUT endpoint data valid. debug only
 591             UINT32  TxBulkEn:1;        //Enable USB DMA Tx
 592             UINT32  RxBulkEn:1;        //Enable USB DMA Rx
 593             UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
 594             UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
 595             UINT32  TxClear:1;        //Clear USB DMA TX path
 596             UINT32  rsv:2;
 597             UINT32  phyclear:1;                 //phy watch dog enable. write 1
 598             UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 1024 bytes
 599             UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
 600         }       field;
 601         UINT32                  word;
 602 }       USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
 603 #else
 604 typedef union   _USB_DMA_CFG_STRUC      {
 605         struct  {
 606             UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
 607             UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 256 bytes
 608             UINT32  phyclear:1;                 //phy watch dog enable. write 1
 609             UINT32  rsv:2;
 610             UINT32  TxClear:1;        //Clear USB DMA TX path
 611             UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
 612             UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
 613             UINT32  RxBulkEn:1;        //Enable USB DMA Rx
 614             UINT32  TxBulkEn:1;        //Enable USB DMA Tx
 615             UINT32  EpoutValid:6;        //OUT endpoint data valid
 616             UINT32  RxBusy:1;        //USB DMA RX FSM busy
 617             UINT32  TxBusy:1;           //USB DMA TX FSM busy
 618         }       field;
 619         UINT32                  word;
 620 }       USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
 621 #endif
 622
 623
 624 //
 625 //  3  PBF  registers
 626 //
 627 //
 628 // Most are for debug. Driver doesn't touch PBF register.
 629 #define PBF_SYS_CTRL     0x0400
 630 #define PBF_CFG                 0x0408
 631 #define PBF_MAX_PCNT     0x040C
 632 #define PBF_CTRL                0x0410
 633 #define PBF_INT_STA      0x0414
 634 #define PBF_INT_ENA      0x0418
 635 #define TXRXQ_PCNT       0x0438
 636 #define PBF_DBG                  0x043c
 637 #define PBF_CAP_CTRL     0x0440
 638
 639 #ifdef RT30xx
 640 #ifdef RTMP_EFUSE_SUPPORT
 641 // eFuse registers
 642 #define EFUSE_CTRL                              0x0580
 643 #define EFUSE_DATA0                             0x0590
 644 #define EFUSE_DATA1                             0x0594
 645 #define EFUSE_DATA2                             0x0598
 646 #define EFUSE_DATA3                             0x059c
 647 #endif // RTMP_EFUSE_SUPPORT //
 648 #endif // RT30xx //
 649
 650 #define OSC_CTRL                0x5a4
 651 #define PCIE_PHY_TX_ATTENUATION_CTRL    0x05C8
 652 #define LDO_CFG0                                0x05d4
 653 #define GPIO_SWITCH                             0x05dc
 654
 655
 656 //
 657 //  4  MAC  registers
 658 //
 659 //
 660 //  4.1 MAC SYSTEM  configuration registers (offset:0x1000)
 661 //
 662 #define MAC_CSR0            0x1000
 663 #ifdef RT_BIG_ENDIAN
 664 typedef union   _ASIC_VER_ID_STRUC      {
 665         struct  {
 666             USHORT  ASICVer;        // version : 2860
 667             USHORT  ASICRev;        // reversion  : 0
 668         }       field;
 669         UINT32                  word;
 670 }       ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
 671 #else
 672 typedef union   _ASIC_VER_ID_STRUC      {
 673         struct  {
 674             USHORT  ASICRev;        // reversion  : 0
 675             USHORT  ASICVer;        // version : 2860
 676         }       field;
 677         UINT32                  word;
 678 }       ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
 679 #endif
 680 #define MAC_SYS_CTRL            0x1004          //MAC_CSR1
 681 #define MAC_ADDR_DW0                            0x1008          // MAC ADDR DW0
 682 #define MAC_ADDR_DW1                     0x100c         // MAC ADDR DW1
 683 //
 684 // MAC_CSR2: STA MAC register 0
 685 //
 686 #ifdef RT_BIG_ENDIAN
 687 typedef union   _MAC_DW0_STRUC  {
 688         struct  {
 689                 UCHAR           Byte3;          // MAC address byte 3
 690                 UCHAR           Byte2;          // MAC address byte 2
 691                 UCHAR           Byte1;          // MAC address byte 1
 692                 UCHAR           Byte0;          // MAC address byte 0
 693         }       field;
 694         UINT32                  word;
 695 }       MAC_DW0_STRUC, *PMAC_DW0_STRUC;
 696 #else
 697 typedef union   _MAC_DW0_STRUC  {
 698         struct  {
 699                 UCHAR           Byte0;          // MAC address byte 0
 700                 UCHAR           Byte1;          // MAC address byte 1
 701                 UCHAR           Byte2;          // MAC address byte 2
 702                 UCHAR           Byte3;          // MAC address byte 3
 703         }       field;
 704         UINT32                  word;
 705 }       MAC_DW0_STRUC, *PMAC_DW0_STRUC;
 706 #endif
 707
 708 //
 709 // MAC_CSR3: STA MAC register 1
 710 //
 711 #ifdef RT_BIG_ENDIAN
 712 typedef union   _MAC_DW1_STRUC  {
 713         struct  {
 714                 UCHAR           Rsvd1;
 715                 UCHAR           U2MeMask;
 716                 UCHAR           Byte5;          // MAC address byte 5
 717                 UCHAR           Byte4;          // MAC address byte 4
 718         }       field;
 719         UINT32                  word;
 720 }       MAC_DW1_STRUC, *PMAC_DW1_STRUC;
 721 #else
 722 typedef union   _MAC_DW1_STRUC  {
 723         struct  {
 724                 UCHAR           Byte4;          // MAC address byte 4
 725                 UCHAR           Byte5;          // MAC address byte 5
 726                 UCHAR           U2MeMask;
 727                 UCHAR           Rsvd1;
 728         }       field;
 729         UINT32                  word;
 730 }       MAC_DW1_STRUC, *PMAC_DW1_STRUC;
 731 #endif
 732
 733 #define MAC_BSSID_DW0                           0x1010          // MAC BSSID DW0
 734 #define MAC_BSSID_DW1                           0x1014          // MAC BSSID DW1
 735
 736 //
 737 // MAC_CSR5: BSSID register 1
 738 //
 739 #ifdef RT_BIG_ENDIAN
 740 typedef union   _MAC_CSR5_STRUC {
 741         struct  {
 742                 USHORT          Rsvd:11;
 743                 USHORT          MBssBcnNum:3;
 744                 USHORT          BssIdMode:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
 745                 UCHAR           Byte5;           // BSSID byte 5
 746                 UCHAR           Byte4;           // BSSID byte 4
 747         }       field;
 748         UINT32                  word;
 749 }       MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
 750 #else
 751 typedef union   _MAC_CSR5_STRUC {
 752         struct  {
 753                 UCHAR           Byte4;           // BSSID byte 4
 754                 UCHAR           Byte5;           // BSSID byte 5
 755                 USHORT          BssIdMask:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
 756                 USHORT          MBssBcnNum:3;
 757                 USHORT          Rsvd:11;
 758         }       field;
 759         UINT32                  word;
 760 }       MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
 761 #endif
 762
 763 #define MAX_LEN_CFG              0x1018         // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 764 #define BBP_CSR_CFG                     0x101c          //
 765 //
 766 // BBP_CSR_CFG: BBP serial control register
 767 //
 768 #ifdef RT_BIG_ENDIAN
 769 typedef union   _BBP_CSR_CFG_STRUC      {
 770         struct  {
 771                 UINT32          :12;
 772                 UINT32          BBP_RW_MODE:1;          // 0: use serial mode  1:parallel
 773                 UINT32          BBP_PAR_DUR:1;              // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
 774                 UINT32          Busy:1;                         // 1: ASIC is busy execute BBP programming.
 775                 UINT32          fRead:1;                    // 0: Write BBP, 1: Read BBP
 776                 UINT32          RegNum:8;                       // Selected     BBP     register
 777                 UINT32          Value:8;                        // Register     value to program into BBP
 778         }       field;
 779         UINT32                  word;
 780 }       BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
 781 #else
 782 typedef union   _BBP_CSR_CFG_STRUC      {
 783         struct  {
 784                 UINT32          Value:8;                        // Register     value to program into BBP
 785                 UINT32          RegNum:8;                       // Selected     BBP     register
 786                 UINT32          fRead:1;                    // 0: Write BBP, 1: Read BBP
 787                 UINT32          Busy:1;                         // 1: ASIC is busy execute BBP programming.
 788                 UINT32          BBP_PAR_DUR:1;               // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
 789                 UINT32          BBP_RW_MODE:1;          // 0: use serial mode  1:parallel
 790                 UINT32          :12;
 791         }       field;
 792         UINT32                  word;
 793 }       BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
 794 #endif
 795 #define RF_CSR_CFG0                     0x1020
 796 //
 797 // RF_CSR_CFG: RF control register
 798 //
 799 #ifdef RT_BIG_ENDIAN
 800 typedef union   _RF_CSR_CFG0_STRUC      {
 801         struct  {
 802                 UINT32          Busy:1;             // 0: idle 1: 8busy
 803                 UINT32          Sel:1;                          // 0:RF_LE0 activate  1:RF_LE1 activate
 804                 UINT32          StandbyMode:1;              // 0: high when stand by 1: low when standby
 805                 UINT32          bitwidth:5;                     // Selected     BBP     register
 806                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 807         }       field;
 808         UINT32                  word;
 809 }       RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
 810 #else
 811 typedef union   _RF_CSR_CFG0_STRUC      {
 812         struct  {
 813                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 814                 UINT32          bitwidth:5;                     // Selected     BBP     register
 815                 UINT32          StandbyMode:1;              // 0: high when stand by 1: low when standby
 816                 UINT32          Sel:1;                          // 0:RF_LE0 activate  1:RF_LE1 activate
 817                 UINT32          Busy:1;             // 0: idle 1: 8busy
 818         }       field;
 819         UINT32                  word;
 820 }       RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
 821 #endif
 822 #define RF_CSR_CFG1                     0x1024
 823 #ifdef RT_BIG_ENDIAN
 824 typedef union   _RF_CSR_CFG1_STRUC      {
 825         struct  {
 826                 UINT32          rsv:7;              // 0: idle 1: 8busy
 827                 UINT32          RFGap:5;                        // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
 828                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 829         }       field;
 830         UINT32                  word;
 831 }       RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
 832 #else
 833 typedef union   _RF_CSR_CFG1_STRUC      {
 834         struct  {
 835                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 836                 UINT32          RFGap:5;                        // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
 837                 UINT32          rsv:7;              // 0: idle 1: 8busy
 838         }       field;
 839         UINT32                  word;
 840 }       RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
 841 #endif
 842 #define RF_CSR_CFG2                     0x1028          //
 843 #ifdef RT_BIG_ENDIAN
 844 typedef union   _RF_CSR_CFG2_STRUC      {
 845         struct  {
 846                 UINT32          rsv:8;              // 0: idle 1: 8busy
 847                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 848         }       field;
 849         UINT32                  word;
 850 }       RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
 851 #else
 852 typedef union   _RF_CSR_CFG2_STRUC      {
 853         struct  {
 854                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 855                 UINT32          rsv:8;              // 0: idle 1: 8busy
 856         }       field;
 857         UINT32                  word;
 858 }       RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
 859 #endif
 860 #define LED_CFG                         0x102c          //  MAC_CSR14
 861 #ifdef RT_BIG_ENDIAN
 862 typedef union   _LED_CFG_STRUC  {
 863         struct  {
 864                 UINT32          :1;
 865                 UINT32          LedPolar:1;                     // Led Polarity.  0: active low1: active high
 866                 UINT32          YLedMode:2;                     // yellow Led Mode
 867                 UINT32          GLedMode:2;                     // green Led Mode
 868                 UINT32          RLedMode:2;                     // red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
 869                 UINT32          rsv:2;
 870                 UINT32          SlowBlinkPeriod:6;                      // slow blinking period. unit:1ms
 871                 UINT32          OffPeriod:8;                    // blinking off period unit 1ms
 872                 UINT32          OnPeriod:8;                     // blinking on period unit 1ms
 873         }       field;
 874         UINT32                  word;
 875 }       LED_CFG_STRUC, *PLED_CFG_STRUC;
 876 #else
 877 typedef union   _LED_CFG_STRUC  {
 878         struct  {
 879                 UINT32          OnPeriod:8;                     // blinking on period unit 1ms
 880                 UINT32          OffPeriod:8;                    // blinking off period unit 1ms
 881                 UINT32          SlowBlinkPeriod:6;                      // slow blinking period. unit:1ms
 882                 UINT32          rsv:2;
 883                 UINT32          RLedMode:2;                     // red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
 884                 UINT32          GLedMode:2;                     // green Led Mode
 885                 UINT32          YLedMode:2;                     // yellow Led Mode
 886                 UINT32          LedPolar:1;                     // Led Polarity.  0: active low1: active high
 887                 UINT32          :1;
 888         }       field;
 889         UINT32                  word;
 890 }       LED_CFG_STRUC, *PLED_CFG_STRUC;
 891 #endif
 892 //
 893 //  4.2 MAC TIMING  configuration registers (offset:0x1100)
 894 //
 895 #define XIFS_TIME_CFG             0x1100                 // MAC_CSR8  MAC_CSR9
 896 #ifdef RT_BIG_ENDIAN
 897 typedef union   _IFS_SLOT_CFG_STRUC     {
 898         struct  {
 899             UINT32  rsv:2;
 900             UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
 901             UINT32  EIFS:9;        //  unit 1us
 902             UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
 903             UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
 904             UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
 905         }       field;
 906         UINT32                  word;
 907 }       IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
 908 #else
 909 typedef union   _IFS_SLOT_CFG_STRUC     {
 910         struct  {
 911             UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
 912             UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
 913             UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
 914             UINT32  EIFS:9;        //  unit 1us
 915             UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
 916             UINT32  rsv:2;
 917         }       field;
 918         UINT32                  word;
 919 }       IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
 920 #endif
 921
 922 #define BKOFF_SLOT_CFG             0x1104                //  mac_csr9 last 8 bits
 923 #define NAV_TIME_CFG             0x1108          // NAV  (MAC_CSR15)
 924 #define CH_TIME_CFG             0x110C                  // Count as channel busy
 925 #define PBF_LIFE_TIMER             0x1110                //TX/RX MPDU timestamp timer (free run)Unit: 1us
 926 #define BCN_TIME_CFG             0x1114          // TXRX_CSR9
 927
 928 #define BCN_OFFSET0                             0x042C
 929 #define BCN_OFFSET1                             0x0430
 930
 931 //
 932 // BCN_TIME_CFG : Synchronization control register
 933 //
 934 #ifdef RT_BIG_ENDIAN
 935 typedef union   _BCN_TIME_CFG_STRUC     {
 936         struct  {
 937                 UINT32          TxTimestampCompensate:8;
 938         UINT32       :3;
 939                 UINT32          bBeaconGen:1;           // Enable beacon generator
 940         UINT32       bTBTTEnable:1;
 941                 UINT32          TsfSyncMode:2;          // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 942                 UINT32          bTsfTicking:1;          // Enable TSF auto counting
 943                 UINT32       BeaconInterval:16;  // in unit of 1/16 TU
 944         }       field;
 945         UINT32                  word;
 946 }       BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
 947 #else
 948 typedef union   _BCN_TIME_CFG_STRUC     {
 949         struct  {
 950                 UINT32       BeaconInterval:16;  // in unit of 1/16 TU
 951                 UINT32          bTsfTicking:1;          // Enable TSF auto counting
 952                 UINT32          TsfSyncMode:2;          // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 953         UINT32       bTBTTEnable:1;
 954                 UINT32          bBeaconGen:1;           // Enable beacon generator
 955         UINT32       :3;
 956                 UINT32          TxTimestampCompensate:8;
 957         }       field;
 958         UINT32                  word;
 959 }       BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
 960 #endif
 961 #define TBTT_SYNC_CFG            0x1118                 // txrx_csr10
 962 #define TSF_TIMER_DW0             0x111C                // Local TSF timer lsb 32 bits. Read-only
 963 #define TSF_TIMER_DW1             0x1120                // msb 32 bits. Read-only.
 964 #define TBTT_TIMER              0x1124                  // TImer remains till next TBTT. Read-only.  TXRX_CSR14
 965 #define INT_TIMER_CFG                   0x1128                  //
 966 #define INT_TIMER_EN                    0x112c                  //  GP-timer and pre-tbtt Int enable
 967 #define CH_IDLE_STA                     0x1130                  //  channel idle time
 968 #define CH_BUSY_STA                     0x1134                  //  channle busy time
 969 //
 970 //  4.2 MAC POWER  configuration registers (offset:0x1200)
 971 //
 972 #define MAC_STATUS_CFG             0x1200                // old MAC_CSR12
 973 #define PWR_PIN_CFG             0x1204           // old MAC_CSR12
 974 #define AUTO_WAKEUP_CFG             0x1208               // old MAC_CSR10
 975 //
 976 // AUTO_WAKEUP_CFG: Manual power control / status register
 977 //
 978 #ifdef RT_BIG_ENDIAN
 979 typedef union   _AUTO_WAKEUP_STRUC      {
 980         struct  {
 981                 UINT32          :16;
 982                 UINT32          EnableAutoWakeup:1;     // 0:sleep, 1:awake
 983                 UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
 984                 UINT32       AutoLeadTime:8;
 985         }       field;
 986         UINT32                  word;
 987 }       AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
 988 #else
 989 typedef union   _AUTO_WAKEUP_STRUC      {
 990         struct  {
 991                 UINT32       AutoLeadTime:8;
 992                 UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
 993                 UINT32          EnableAutoWakeup:1;     // 0:sleep, 1:awake
 994                 UINT32          :16;
 995         }       field;
 996         UINT32                  word;
 997 }       AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
 998 #endif
 999 //
1000 //  4.3 MAC TX  configuration registers (offset:0x1300)
1001 //
1002
1003 #define EDCA_AC0_CFG    0x1300          //AC_TXOP_CSR0 0x3474
1004 #define EDCA_AC1_CFG    0x1304
1005 #define EDCA_AC2_CFG    0x1308
1006 #define EDCA_AC3_CFG    0x130c
1007 #ifdef RT_BIG_ENDIAN
1008 typedef union   _EDCA_AC_CFG_STRUC      {
1009         struct  {
1010             UINT32  :12;        //
1011             UINT32  Cwmax:4;        //unit power of 2
1012             UINT32  Cwmin:4;        //
1013             UINT32  Aifsn:4;        // # of slot time
1014             UINT32  AcTxop:8;        //  in unit of 32us
1015         }       field;
1016         UINT32                  word;
1017 }       EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
1018 #else
1019 typedef union   _EDCA_AC_CFG_STRUC      {
1020         struct  {
1021             UINT32  AcTxop:8;        //  in unit of 32us
1022             UINT32  Aifsn:4;        // # of slot time
1023             UINT32  Cwmin:4;        //
1024             UINT32  Cwmax:4;        //unit power of 2
1025             UINT32  :12;       //
1026         }       field;
1027         UINT32                  word;
1028 }       EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
1029 #endif
1030
1031 #define EDCA_TID_AC_MAP 0x1310
1032 #define TX_PWR_CFG_0    0x1314
1033 #define TX_PWR_CFG_1    0x1318
1034 #define TX_PWR_CFG_2    0x131C
1035 #define TX_PWR_CFG_3    0x1320
1036 #define TX_PWR_CFG_4    0x1324
1037 #define TX_PIN_CFG              0x1328
1038 #define TX_BAND_CFG     0x132c          // 0x1 use upper 20MHz. 0 juse lower 20MHz
1039 #define TX_SW_CFG0              0x1330
1040 #define TX_SW_CFG1              0x1334
1041 #define TX_SW_CFG2              0x1338
1042 #define TXOP_THRES_CFG          0x133c
1043 #define TXOP_CTRL_CFG           0x1340
1044 #define TX_RTS_CFG              0x1344
1045
1046 #ifdef RT_BIG_ENDIAN
1047 typedef union   _TX_RTS_CFG_STRUC       {
1048         struct  {
1049             UINT32       rsv:7;
1050             UINT32       RtsFbkEn:1;    // enable rts rate fallback
1051             UINT32       RtsThres:16;    // unit:byte
1052             UINT32       AutoRtsRetryLimit:8;
1053         }       field;
1054         UINT32                  word;
1055 }       TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
1056 #else
1057 typedef union   _TX_RTS_CFG_STRUC       {
1058         struct  {
1059             UINT32       AutoRtsRetryLimit:8;
1060             UINT32       RtsThres:16;    // unit:byte
1061             UINT32       RtsFbkEn:1;    // enable rts rate fallback
1062             UINT32       rsv:7;     // 1: HT non-STBC control frame enable
1063         }       field;
1064         UINT32                  word;
1065 }       TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
1066 #endif
1067 #define TX_TIMEOUT_CFG  0x1348
1068 #ifdef RT_BIG_ENDIAN
1069 typedef union   _TX_TIMEOUT_CFG_STRUC   {
1070         struct  {
1071             UINT32       rsv2:8;
1072             UINT32       TxopTimeout:8; //TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1073             UINT32       RxAckTimeout:8;        // unit:slot. Used for TX precedure
1074             UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
1075             UINT32       rsv:4;
1076         }       field;
1077         UINT32                  word;
1078 }       TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
1079 #else
1080 typedef union   _TX_TIMEOUT_CFG_STRUC   {
1081         struct  {
1082             UINT32       rsv:4;
1083             UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
1084             UINT32       RxAckTimeout:8;        // unit:slot. Used for TX precedure
1085             UINT32       TxopTimeout:8; //TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1086             UINT32       rsv2:8;     // 1: HT non-STBC control frame enable
1087         }       field;
1088         UINT32                  word;
1089 }       TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
1090 #endif
1091 #define TX_RTY_CFG      0x134c
1092 #ifdef RT_BIG_ENDIAN
1093 typedef union PACKED _TX_RTY_CFG_STRUC  {
1094         struct  {
1095             UINT32       rsv:1;
1096             UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
1097             UINT32       AggRtyMode:1;  // Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
1098             UINT32       NonAggRtyMode:1;       // Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
1099             UINT32       LongRtyThre:12;        // Long retry threshoold
1100             UINT32       LongRtyLimit:8;        //long retry limit
1101             UINT32       ShortRtyLimit:8;       //  short retry limit
1102
1103         }       field;
1104         UINT32                  word;
1105 }       TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
1106 #else
1107 typedef union PACKED _TX_RTY_CFG_STRUC  {
1108         struct  {
1109             UINT32       ShortRtyLimit:8;       //  short retry limit
1110             UINT32       LongRtyLimit:8;        //long retry limit
1111             UINT32       LongRtyThre:12;        // Long retry threshoold
1112             UINT32       NonAggRtyMode:1;       // Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
1113             UINT32       AggRtyMode:1;  // Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
1114             UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
1115             UINT32       rsv:1;     // 1: HT non-STBC control frame enable
1116         }       field;
1117         UINT32                  word;
1118 }       TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
1119 #endif
1120 #define TX_LINK_CFG     0x1350
1121 #ifdef RT_BIG_ENDIAN
1122 typedef union   PACKED _TX_LINK_CFG_STRUC       {
1123         struct PACKED {
1124             UINT32       RemotMFS:8;    //remote MCS feedback sequence number
1125             UINT32       RemotMFB:8;    //  remote MCS feedback
1126             UINT32       rsv:3; //
1127             UINT32       TxCFAckEn:1;   //   Piggyback CF-ACK enable
1128             UINT32       TxRDGEn:1;     // RDG TX enable
1129             UINT32       TxMRQEn:1;     //  MCS request TX enable
1130             UINT32       RemoteUMFSEnable:1;    //  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
1131             UINT32       MFBEnable:1;   //  TX apply remote MFB 1:enable
1132             UINT32       RemoteMFBLifeTime:8;   //remote MFB life time. unit : 32us
1133         }       field;
1134         UINT32                  word;
1135 }       TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
1136 #else
1137 typedef union   PACKED _TX_LINK_CFG_STRUC       {
1138         struct PACKED {
1139             UINT32       RemoteMFBLifeTime:8;   //remote MFB life time. unit : 32us
1140             UINT32       MFBEnable:1;   //  TX apply remote MFB 1:enable
1141             UINT32       RemoteUMFSEnable:1;    //  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
1142             UINT32       TxMRQEn:1;     //  MCS request TX enable
1143             UINT32       TxRDGEn:1;     // RDG TX enable
1144             UINT32       TxCFAckEn:1;   //   Piggyback CF-ACK enable
1145             UINT32       rsv:3; //
1146             UINT32       RemotMFB:8;    //  remote MCS feedback
1147             UINT32       RemotMFS:8;    //remote MCS feedback sequence number
1148         }       field;
1149         UINT32                  word;
1150 }       TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
1151 #endif
1152 #define HT_FBK_CFG0     0x1354
1153 #ifdef RT_BIG_ENDIAN
1154 typedef union PACKED _HT_FBK_CFG0_STRUC {
1155         struct  {
1156             UINT32       HTMCS7FBK:4;
1157             UINT32       HTMCS6FBK:4;
1158             UINT32       HTMCS5FBK:4;
1159             UINT32       HTMCS4FBK:4;
1160             UINT32       HTMCS3FBK:4;
1161             UINT32       HTMCS2FBK:4;
1162             UINT32       HTMCS1FBK:4;
1163             UINT32       HTMCS0FBK:4;
1164         }       field;
1165         UINT32                  word;
1166 }       HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
1167 #else
1168 typedef union PACKED _HT_FBK_CFG0_STRUC {
1169         struct  {
1170             UINT32       HTMCS0FBK:4;
1171             UINT32       HTMCS1FBK:4;
1172             UINT32       HTMCS2FBK:4;
1173             UINT32       HTMCS3FBK:4;
1174             UINT32       HTMCS4FBK:4;
1175             UINT32       HTMCS5FBK:4;
1176             UINT32       HTMCS6FBK:4;
1177             UINT32       HTMCS7FBK:4;
1178         }       field;
1179         UINT32                  word;
1180 }       HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
1181 #endif
1182 #define HT_FBK_CFG1     0x1358
1183 #ifdef RT_BIG_ENDIAN
1184 typedef union   _HT_FBK_CFG1_STRUC      {
1185         struct  {
1186             UINT32       HTMCS15FBK:4;
1187             UINT32       HTMCS14FBK:4;
1188             UINT32       HTMCS13FBK:4;
1189             UINT32       HTMCS12FBK:4;
1190             UINT32       HTMCS11FBK:4;
1191             UINT32       HTMCS10FBK:4;
1192             UINT32       HTMCS9FBK:4;
1193             UINT32       HTMCS8FBK:4;
1194         }       field;
1195         UINT32                  word;
1196 }       HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
1197 #else
1198 typedef union   _HT_FBK_CFG1_STRUC      {
1199         struct  {
1200             UINT32       HTMCS8FBK:4;
1201             UINT32       HTMCS9FBK:4;
1202             UINT32       HTMCS10FBK:4;
1203             UINT32       HTMCS11FBK:4;
1204             UINT32       HTMCS12FBK:4;
1205             UINT32       HTMCS13FBK:4;
1206             UINT32       HTMCS14FBK:4;
1207             UINT32       HTMCS15FBK:4;
1208         }       field;
1209         UINT32                  word;
1210 }       HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
1211 #endif
1212 #define LG_FBK_CFG0     0x135c
1213 #ifdef RT_BIG_ENDIAN
1214 typedef union   _LG_FBK_CFG0_STRUC      {
1215         struct  {
1216             UINT32       OFDMMCS7FBK:4; //initial value is 6
1217             UINT32       OFDMMCS6FBK:4; //initial value is 5
1218             UINT32       OFDMMCS5FBK:4; //initial value is 4
1219             UINT32       OFDMMCS4FBK:4; //initial value is 3
1220             UINT32       OFDMMCS3FBK:4; //initial value is 2
1221             UINT32       OFDMMCS2FBK:4; //initial value is 1
1222             UINT32       OFDMMCS1FBK:4; //initial value is 0
1223             UINT32       OFDMMCS0FBK:4; //initial value is 0
1224         }       field;
1225         UINT32                  word;
1226 }       LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
1227 #else
1228 typedef union   _LG_FBK_CFG0_STRUC      {
1229         struct  {
1230             UINT32       OFDMMCS0FBK:4; //initial value is 0
1231             UINT32       OFDMMCS1FBK:4; //initial value is 0
1232             UINT32       OFDMMCS2FBK:4; //initial value is 1
1233             UINT32       OFDMMCS3FBK:4; //initial value is 2
1234             UINT32       OFDMMCS4FBK:4; //initial value is 3
1235             UINT32       OFDMMCS5FBK:4; //initial value is 4
1236             UINT32       OFDMMCS6FBK:4; //initial value is 5
1237             UINT32       OFDMMCS7FBK:4; //initial value is 6
1238         }       field;
1239         UINT32                  word;
1240 }       LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
1241 #endif
1242 #define LG_FBK_CFG1             0x1360
1243 #ifdef RT_BIG_ENDIAN
1244 typedef union   _LG_FBK_CFG1_STRUC      {
1245         struct  {
1246             UINT32       rsv:16;
1247             UINT32       CCKMCS3FBK:4;  //initial value is 2
1248             UINT32       CCKMCS2FBK:4;  //initial value is 1
1249             UINT32       CCKMCS1FBK:4;  //initial value is 0
1250             UINT32       CCKMCS0FBK:4;  //initial value is 0
1251         }       field;
1252         UINT32                  word;
1253 }       LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
1254 #else
1255 typedef union   _LG_FBK_CFG1_STRUC      {
1256         struct  {
1257             UINT32       CCKMCS0FBK:4;  //initial value is 0
1258             UINT32       CCKMCS1FBK:4;  //initial value is 0
1259             UINT32       CCKMCS2FBK:4;  //initial value is 1
1260             UINT32       CCKMCS3FBK:4;  //initial value is 2
1261             UINT32       rsv:16;
1262         }       field;
1263         UINT32                  word;
1264 }       LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
1265 #endif
1266
1267
1268 //=======================================================
1269 //================ Protection Paramater================================
1270 //=======================================================
1271 #define CCK_PROT_CFG    0x1364          //CCK Protection
1272 #define ASIC_SHORTNAV           1
1273 #define ASIC_LONGNAV            2
1274 #define ASIC_RTS                1
1275 #define ASIC_CTS                2
1276 #ifdef RT_BIG_ENDIAN
1277 typedef union   _PROT_CFG_STRUC {
1278         struct  {
1279             UINT32       rsv:5;
1280             UINT32       RTSThEn:1;     //RTS threshold enable on CCK TX
1281             UINT32       TxopAllowGF40:1;       //CCK TXOP allowance.0:disallow.
1282             UINT32       TxopAllowGF20:1;       //CCK TXOP allowance.0:disallow.
1283             UINT32       TxopAllowMM40:1;       //CCK TXOP allowance.0:disallow.
1284             UINT32       TxopAllowMM20:1;       //CCK TXOP allowance. 0:disallow.
1285             UINT32       TxopAllowOfdm:1;       //CCK TXOP allowance.0:disallow.
1286             UINT32       TxopAllowCck:1;        //CCK TXOP allowance.0:disallow.
1287             UINT32       ProtectNav:2;  //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
1288             UINT32       ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
1289             UINT32       ProtectRate:16;        //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
1290         }       field;
1291         UINT32                  word;
1292 }       PROT_CFG_STRUC, *PPROT_CFG_STRUC;
1293 #else
1294 typedef union   _PROT_CFG_STRUC {
1295         struct  {
1296             UINT32       ProtectRate:16;        //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
1297             UINT32       ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
1298             UINT32       ProtectNav:2;  //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
1299             UINT32       TxopAllowCck:1;        //CCK TXOP allowance.0:disallow.
1300             UINT32       TxopAllowOfdm:1;       //CCK TXOP allowance.0:disallow.
1301             UINT32       TxopAllowMM20:1;       //CCK TXOP allowance. 0:disallow.
1302             UINT32       TxopAllowMM40:1;       //CCK TXOP allowance.0:disallow.
1303             UINT32       TxopAllowGF20:1;       //CCK TXOP allowance.0:disallow.
1304             UINT32       TxopAllowGF40:1;       //CCK TXOP allowance.0:disallow.
1305             UINT32       RTSThEn:1;     //RTS threshold enable on CCK TX
1306             UINT32       rsv:5;
1307         }       field;
1308         UINT32                  word;
1309 }       PROT_CFG_STRUC, *PPROT_CFG_STRUC;
1310 #endif
1311
1312 #define OFDM_PROT_CFG   0x1368          //OFDM Protection
1313 #define MM20_PROT_CFG   0x136C          //MM20 Protection
1314 #define MM40_PROT_CFG   0x1370          //MM40 Protection
1315 #define GF20_PROT_CFG   0x1374          //GF20 Protection
1316 #define GF40_PROT_CFG   0x1378          //GR40 Protection
1317 #define EXP_CTS_TIME    0x137C          //
1318 #define EXP_ACK_TIME    0x1380          //
1319
1320 //
1321 //  4.4 MAC RX configuration registers (offset:0x1400)
1322 //
1323 #define RX_FILTR_CFG    0x1400                  //TXRX_CSR0
1324 #define AUTO_RSP_CFG    0x1404                  //TXRX_CSR4
1325 //
1326 // TXRX_CSR4: Auto-Responder/
1327 //
1328 #ifdef RT_BIG_ENDIAN
1329 typedef union _AUTO_RSP_CFG_STRUC {
1330  struct {
1331      UINT32        :24;
1332      UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
1333      UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
1334      UINT32       rsv:1;   // Power bit value in conrtrol frame
1335      UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
1336      UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
1337      UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
1338      UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
1339      UINT32       AutoResponderEnable:1;
1340  } field;
1341  UINT32   word;
1342 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
1343 #else
1344 typedef union _AUTO_RSP_CFG_STRUC {
1345  struct {
1346      UINT32       AutoResponderEnable:1;
1347      UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
1348      UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
1349      UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
1350      UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
1351      UINT32       rsv:1;   // Power bit value in conrtrol frame
1352      UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
1353      UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
1354      UINT32        :24;
1355  } field;
1356  UINT32   word;
1357 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
1358 #endif
1359
1360 #define LEGACY_BASIC_RATE       0x1408  //  TXRX_CSR5           0x3054
1361 #define HT_BASIC_RATE           0x140c
1362 #define HT_CTRL_CFG             0x1410
1363 #define SIFS_COST_CFG           0x1414
1364 #define RX_PARSER_CFG           0x1418  //Set NAV for all received frames
1365
1366 //
1367 //  4.5 MAC Security configuration (offset:0x1500)
1368 //
1369 #define TX_SEC_CNT0             0x1500          //
1370 #define RX_SEC_CNT0             0x1504          //
1371 #define CCMP_FC_MUTE            0x1508          //
1372 //
1373 //  4.6 HCCA/PSMP (offset:0x1600)
1374 //
1375 #define TXOP_HLDR_ADDR0         0x1600
1376 #define TXOP_HLDR_ADDR1         0x1604
1377 #define TXOP_HLDR_ET            0x1608
1378 #define QOS_CFPOLL_RA_DW0               0x160c
1379 #define QOS_CFPOLL_A1_DW1               0x1610
1380 #define QOS_CFPOLL_QC           0x1614
1381 //
1382 //  4.7 MAC Statistis registers (offset:0x1700)
1383 //
1384 #define RX_STA_CNT0             0x1700          //
1385 #define RX_STA_CNT1             0x1704          //
1386 #define RX_STA_CNT2             0x1708          //
1387
1388 //
1389 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
1390 //
1391 #ifdef RT_BIG_ENDIAN
1392 typedef union   _RX_STA_CNT0_STRUC      {
1393         struct  {
1394             USHORT  PhyErr;
1395             USHORT  CrcErr;
1396         }       field;
1397         UINT32                  word;
1398 }       RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
1399 #else
1400 typedef union   _RX_STA_CNT0_STRUC      {
1401         struct  {
1402             USHORT  CrcErr;
1403             USHORT  PhyErr;
1404         }       field;
1405         UINT32                  word;
1406 }       RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
1407 #endif
1408
1409 //
1410 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
1411 //
1412 #ifdef RT_BIG_ENDIAN
1413 typedef union   _RX_STA_CNT1_STRUC      {
1414         struct  {
1415             USHORT  PlcpErr;
1416             USHORT  FalseCca;
1417         }       field;
1418         UINT32                  word;
1419 }       RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
1420 #else
1421 typedef union   _RX_STA_CNT1_STRUC      {
1422         struct  {
1423             USHORT  FalseCca;
1424             USHORT  PlcpErr;
1425         }       field;
1426         UINT32                  word;
1427 }       RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
1428 #endif
1429
1430 //
1431 // RX_STA_CNT2_STRUC:
1432 //
1433 #ifdef RT_BIG_ENDIAN
1434 typedef union   _RX_STA_CNT2_STRUC      {
1435         struct  {
1436             USHORT  RxFifoOverflowCount;
1437             USHORT  RxDupliCount;
1438         }       field;
1439         UINT32                  word;
1440 }       RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
1441 #else
1442 typedef union   _RX_STA_CNT2_STRUC      {
1443         struct  {
1444             USHORT  RxDupliCount;
1445             USHORT  RxFifoOverflowCount;
1446         }       field;
1447         UINT32                  word;
1448 }       RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
1449 #endif
1450 #define TX_STA_CNT0             0x170C          //
1451 //
1452 // STA_CSR3: TX Beacon count
1453 //
1454 #ifdef RT_BIG_ENDIAN
1455 typedef union   _TX_STA_CNT0_STRUC      {
1456         struct  {
1457             USHORT  TxBeaconCount;
1458             USHORT  TxFailCount;
1459         }       field;
1460         UINT32                  word;
1461 }       TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
1462 #else
1463 typedef union   _TX_STA_CNT0_STRUC      {
1464         struct  {
1465             USHORT  TxFailCount;
1466             USHORT  TxBeaconCount;
1467         }       field;
1468         UINT32                  word;
1469 }       TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
1470 #endif
1471 #define TX_STA_CNT1             0x1710          //
1472 //
1473 // TX_STA_CNT1: TX tx count
1474 //
1475 #ifdef RT_BIG_ENDIAN
1476 typedef union   _TX_STA_CNT1_STRUC      {
1477         struct  {
1478             USHORT  TxRetransmit;
1479             USHORT  TxSuccess;
1480         }       field;
1481         UINT32                  word;
1482 }       TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
1483 #else
1484 typedef union   _TX_STA_CNT1_STRUC      {
1485         struct  {
1486             USHORT  TxSuccess;
1487             USHORT  TxRetransmit;
1488         }       field;
1489         UINT32                  word;
1490 }       TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
1491 #endif
1492 #define TX_STA_CNT2             0x1714          //
1493 //
1494 // TX_STA_CNT2: TX tx count
1495 //
1496 #ifdef RT_BIG_ENDIAN
1497 typedef union   _TX_STA_CNT2_STRUC      {
1498         struct  {
1499             USHORT  TxUnderFlowCount;
1500             USHORT  TxZeroLenCount;
1501         }       field;
1502         UINT32                  word;
1503 }       TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
1504 #else
1505 typedef union   _TX_STA_CNT2_STRUC      {
1506         struct  {
1507             USHORT  TxZeroLenCount;
1508             USHORT  TxUnderFlowCount;
1509         }       field;
1510         UINT32                  word;
1511 }       TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
1512 #endif
1513 #define TX_STA_FIFO             0x1718          //
1514 //
1515 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
1516 //
1517 #ifdef RT_BIG_ENDIAN
1518 typedef union PACKED _TX_STA_FIFO_STRUC {
1519         struct  {
1520                 UINT32          Reserve:2;
1521                 UINT32          TxBF:1; // 3*3
1522                 UINT32          SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1523 //              UINT32          SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1524                 UINT32          wcid:8;         //wireless client index
1525                 UINT32          TxAckRequired:1;    // ack required
1526                 UINT32          TxAggre:1;    // Tx is aggregated
1527                 UINT32          TxSuccess:1;   // Tx success. whether success or not
1528                 UINT32          PidType:4;
1529                 UINT32          bValid:1;   // 1:This register contains a valid TX result
1530         }       field;
1531         UINT32                  word;
1532 }       TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
1533 #else
1534 typedef union PACKED _TX_STA_FIFO_STRUC {
1535         struct  {
1536                 UINT32          bValid:1;   // 1:This register contains a valid TX result
1537                 UINT32          PidType:4;
1538                 UINT32          TxSuccess:1;   // Tx No retry success
1539                 UINT32          TxAggre:1;    // Tx Retry Success
1540                 UINT32          TxAckRequired:1;    // Tx fail
1541                 UINT32          wcid:8;         //wireless client index
1542 //              UINT32          SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1543                 UINT32          SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1544                 UINT32          TxBF:1;
1545                 UINT32          Reserve:2;
1546         }       field;
1547         UINT32                  word;
1548 }       TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
1549 #endif
1550 // Debug counter
1551 #define TX_AGG_CNT      0x171c
1552 #ifdef RT_BIG_ENDIAN
1553 typedef union   _TX_AGG_CNT_STRUC       {
1554         struct  {
1555             USHORT  AggTxCount;
1556             USHORT  NonAggTxCount;
1557         }       field;
1558         UINT32                  word;
1559 }       TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
1560 #else
1561 typedef union   _TX_AGG_CNT_STRUC       {
1562         struct  {
1563             USHORT  NonAggTxCount;
1564             USHORT  AggTxCount;
1565         }       field;
1566         UINT32                  word;
1567 }       TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
1568 #endif
1569 // Debug counter
1570 #define TX_AGG_CNT0     0x1720
1571 #ifdef RT_BIG_ENDIAN
1572 typedef union   _TX_AGG_CNT0_STRUC      {
1573         struct  {
1574             USHORT  AggSize2Count;
1575             USHORT  AggSize1Count;
1576         }       field;
1577         UINT32                  word;
1578 }       TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
1579 #else
1580 typedef union   _TX_AGG_CNT0_STRUC      {
1581         struct  {
1582             USHORT  AggSize1Count;
1583             USHORT  AggSize2Count;
1584         }       field;
1585         UINT32                  word;
1586 }       TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
1587 #endif
1588 // Debug counter
1589 #define TX_AGG_CNT1     0x1724
1590 #ifdef RT_BIG_ENDIAN
1591 typedef union   _TX_AGG_CNT1_STRUC      {
1592         struct  {
1593             USHORT  AggSize4Count;
1594             USHORT  AggSize3Count;
1595         }       field;
1596         UINT32                  word;
1597 }       TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
1598 #else
1599 typedef union   _TX_AGG_CNT1_STRUC      {
1600         struct  {
1601             USHORT  AggSize3Count;
1602             USHORT  AggSize4Count;
1603         }       field;
1604         UINT32                  word;
1605 }       TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
1606 #endif
1607 #define TX_AGG_CNT2     0x1728
1608 #ifdef RT_BIG_ENDIAN
1609 typedef union   _TX_AGG_CNT2_STRUC      {
1610         struct  {
1611             USHORT  AggSize6Count;
1612             USHORT  AggSize5Count;
1613         }       field;
1614         UINT32                  word;
1615 }       TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
1616 #else
1617 typedef union   _TX_AGG_CNT2_STRUC      {
1618         struct  {
1619             USHORT  AggSize5Count;
1620             USHORT  AggSize6Count;
1621         }       field;
1622         UINT32                  word;
1623 }       TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
1624 #endif
1625 // Debug counter
1626 #define TX_AGG_CNT3     0x172c
1627 #ifdef RT_BIG_ENDIAN
1628 typedef union   _TX_AGG_CNT3_STRUC      {
1629         struct  {
1630             USHORT  AggSize8Count;
1631             USHORT  AggSize7Count;
1632         }       field;
1633         UINT32                  word;
1634 }       TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
1635 #else
1636 typedef union   _TX_AGG_CNT3_STRUC      {
1637         struct  {
1638             USHORT  AggSize7Count;
1639             USHORT  AggSize8Count;
1640         }       field;
1641         UINT32                  word;
1642 }       TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
1643 #endif
1644 // Debug counter
1645 #define TX_AGG_CNT4     0x1730
1646 #ifdef RT_BIG_ENDIAN
1647 typedef union   _TX_AGG_CNT4_STRUC      {
1648         struct  {
1649             USHORT  AggSize10Count;
1650             USHORT  AggSize9Count;
1651         }       field;
1652         UINT32                  word;
1653 }       TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
1654 #else
1655 typedef union   _TX_AGG_CNT4_STRUC      {
1656         struct  {
1657             USHORT  AggSize9Count;
1658             USHORT  AggSize10Count;
1659         }       field;
1660         UINT32                  word;
1661 }       TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
1662 #endif
1663 #define TX_AGG_CNT5     0x1734
1664 #ifdef RT_BIG_ENDIAN
1665 typedef union   _TX_AGG_CNT5_STRUC      {
1666         struct  {
1667             USHORT  AggSize12Count;
1668             USHORT  AggSize11Count;
1669         }       field;
1670         UINT32                  word;
1671 }       TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
1672 #else
1673 typedef union   _TX_AGG_CNT5_STRUC      {
1674         struct  {
1675             USHORT  AggSize11Count;
1676             USHORT  AggSize12Count;
1677         }       field;
1678         UINT32                  word;
1679 }       TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
1680 #endif
1681 #define TX_AGG_CNT6             0x1738
1682 #ifdef RT_BIG_ENDIAN
1683 typedef union   _TX_AGG_CNT6_STRUC      {
1684         struct  {
1685             USHORT  AggSize14Count;
1686             USHORT  AggSize13Count;
1687         }       field;
1688         UINT32                  word;
1689 }       TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
1690 #else
1691 typedef union   _TX_AGG_CNT6_STRUC      {
1692         struct  {
1693             USHORT  AggSize13Count;
1694             USHORT  AggSize14Count;
1695         }       field;
1696         UINT32                  word;
1697 }       TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
1698 #endif
1699 #define TX_AGG_CNT7             0x173c
1700 #ifdef RT_BIG_ENDIAN
1701 typedef union   _TX_AGG_CNT7_STRUC      {
1702         struct  {
1703             USHORT  AggSize16Count;
1704             USHORT  AggSize15Count;
1705         }       field;
1706         UINT32                  word;
1707 }       TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
1708 #else
1709 typedef union   _TX_AGG_CNT7_STRUC      {
1710         struct  {
1711             USHORT  AggSize15Count;
1712             USHORT  AggSize16Count;
1713         }       field;
1714         UINT32                  word;
1715 }       TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
1716 #endif
1717 #define MPDU_DENSITY_CNT                0x1740
1718 #ifdef RT_BIG_ENDIAN
1719 typedef union   _MPDU_DEN_CNT_STRUC     {
1720         struct  {
1721             USHORT  RXZeroDelCount;     //RX zero length delimiter count
1722             USHORT  TXZeroDelCount;     //TX zero length delimiter count
1723         }       field;
1724         UINT32                  word;
1725 }       MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
1726 #else
1727 typedef union   _MPDU_DEN_CNT_STRUC     {
1728         struct  {
1729             USHORT  TXZeroDelCount;     //TX zero length delimiter count
1730             USHORT  RXZeroDelCount;     //RX zero length delimiter count
1731         }       field;
1732         UINT32                  word;
1733 }       MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
1734 #endif
1735 //
1736 // TXRX control registers - base address 0x3000
1737 //
1738 // rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1739 #define TXRX_CSR1           0x77d0
1740
1741 //
1742 // Security key table memory, base address = 0x1000
1743 //
1744 #define MAC_WCID_BASE           0x1800 //8-bytes(use only 6-bytes) * 256 entry =
1745 #define HW_WCID_ENTRY_SIZE   8
1746 #define PAIRWISE_KEY_TABLE_BASE     0x4000      // 32-byte * 256-entry =  -byte
1747 #define HW_KEY_ENTRY_SIZE           0x20
1748 #define PAIRWISE_IVEIV_TABLE_BASE     0x6000      // 8-byte * 256-entry =  -byte
1749 #define MAC_IVEIV_TABLE_BASE     0x6000      // 8-byte * 256-entry =  -byte
1750 #define HW_IVEIV_ENTRY_SIZE   8
1751 #define MAC_WCID_ATTRIBUTE_BASE     0x6800      // 4-byte * 256-entry =  -byte
1752 #define HW_WCID_ATTRI_SIZE   4
1753 #define WCID_RESERVED                   0x6bfc
1754 #define SHARED_KEY_TABLE_BASE       0x6c00      // 32-byte * 16-entry = 512-byte
1755 #define SHARED_KEY_MODE_BASE       0x7000      // 32-byte * 16-entry = 512-byte
1756 #define HW_SHARED_KEY_MODE_SIZE   4
1757 #define SHAREDKEYTABLE                  0
1758 #define PAIRWISEKEYTABLE                        1
1759
1760
1761 #ifdef RT_BIG_ENDIAN
1762 typedef union   _SHAREDKEY_MODE_STRUC   {
1763         struct  {
1764                 UINT32       :1;
1765                 UINT32       Bss1Key3CipherAlg:3;
1766                 UINT32       :1;
1767                 UINT32       Bss1Key2CipherAlg:3;
1768                 UINT32       :1;
1769                 UINT32       Bss1Key1CipherAlg:3;
1770                 UINT32       :1;
1771                 UINT32       Bss1Key0CipherAlg:3;
1772                 UINT32       :1;
1773                 UINT32       Bss0Key3CipherAlg:3;
1774                 UINT32       :1;
1775                 UINT32       Bss0Key2CipherAlg:3;
1776                 UINT32       :1;
1777                 UINT32       Bss0Key1CipherAlg:3;
1778                 UINT32       :1;
1779                 UINT32       Bss0Key0CipherAlg:3;
1780         }       field;
1781         UINT32                  word;
1782 }       SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1783 #else
1784 typedef union   _SHAREDKEY_MODE_STRUC   {
1785         struct  {
1786                 UINT32       Bss0Key0CipherAlg:3;
1787                 UINT32       :1;
1788                 UINT32       Bss0Key1CipherAlg:3;
1789                 UINT32       :1;
1790                 UINT32       Bss0Key2CipherAlg:3;
1791                 UINT32       :1;
1792                 UINT32       Bss0Key3CipherAlg:3;
1793                 UINT32       :1;
1794                 UINT32       Bss1Key0CipherAlg:3;
1795                 UINT32       :1;
1796                 UINT32       Bss1Key1CipherAlg:3;
1797                 UINT32       :1;
1798                 UINT32       Bss1Key2CipherAlg:3;
1799                 UINT32       :1;
1800                 UINT32       Bss1Key3CipherAlg:3;
1801                 UINT32       :1;
1802         }       field;
1803         UINT32                  word;
1804 }       SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1805 #endif
1806 // 64-entry for pairwise key table
1807 typedef struct _HW_WCID_ENTRY {  // 8-byte per entry
1808     UCHAR   Address[6];
1809     UCHAR   Rsv[2];
1810 } HW_WCID_ENTRY, PHW_WCID_ENTRY;
1811
1812
1813 // =================================================================================
1814 // WCID  format
1815 // =================================================================================
1816 //7.1   WCID  ENTRY  format  : 8bytes
1817 typedef struct  _WCID_ENTRY_STRUC {
1818         UCHAR           RXBABitmap7;    // bit0 for TID8, bit7 for TID 15
1819         UCHAR           RXBABitmap0;    // bit0 for TID0, bit7 for TID 7
1820         UCHAR           MAC[6]; // 0 for shared key table.  1 for pairwise key table
1821 }       WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1822
1823 //8.1.1 SECURITY  KEY  format  : 8DW
1824 // 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
1825 typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
1826     UCHAR   Key[16];
1827     UCHAR   TxMic[8];
1828     UCHAR   RxMic[8];
1829 } HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1830
1831 //8.1.2 IV/EIV  format  : 2DW
1832
1833 //8.1.3 RX attribute entry format  : 1DW
1834 #ifdef RT_BIG_ENDIAN
1835 typedef struct  _MAC_ATTRIBUTE_STRUC {
1836         UINT32          rsv:22;
1837         UINT32          RXWIUDF:3;
1838         UINT32          BSSIDIdx:3; //multipleBSS index for the WCID
1839         UINT32          PairKeyMode:3;
1840         UINT32          KeyTab:1;       // 0 for shared key table.  1 for pairwise key table
1841 }       MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1842 #else
1843 typedef struct  _MAC_ATTRIBUTE_STRUC {
1844         UINT32          KeyTab:1;       // 0 for shared key table.  1 for pairwise key table
1845         UINT32          PairKeyMode:3;
1846         UINT32          BSSIDIdx:3; //multipleBSS index for the WCID
1847         UINT32          RXWIUDF:3;
1848         UINT32          rsv:22;
1849 }       MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1850 #endif
1851
1852
1853 // =================================================================================
1854 // HOST-MCU communication data structure
1855 // =================================================================================
1856
1857 //
1858 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
1859 //
1860 #ifdef RT_BIG_ENDIAN
1861 typedef union  _H2M_MAILBOX_STRUC {
1862     struct {
1863         UINT32       Owner:8;
1864         UINT32       CmdToken:8;    // 0xff tells MCU not to report CmdDoneInt after excuting the command
1865         UINT32       HighByte:8;
1866         UINT32       LowByte:8;
1867     }   field;
1868     UINT32           word;
1869 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
1870 #else
1871 typedef union  _H2M_MAILBOX_STRUC {
1872     struct {
1873         UINT32       LowByte:8;
1874         UINT32       HighByte:8;
1875         UINT32       CmdToken:8;
1876         UINT32       Owner:8;
1877     }   field;
1878     UINT32           word;
1879 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
1880 #endif
1881
1882 //
1883 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
1884 //
1885 #ifdef RT_BIG_ENDIAN
1886 typedef union _M2H_CMD_DONE_STRUC {
1887     struct  {
1888         UINT32       CmdToken3;
1889         UINT32       CmdToken2;
1890         UINT32       CmdToken1;
1891         UINT32       CmdToken0;
1892     } field;
1893     UINT32           word;
1894 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
1895 #else
1896 typedef union _M2H_CMD_DONE_STRUC {
1897     struct  {
1898         UINT32       CmdToken0;
1899         UINT32       CmdToken1;
1900         UINT32       CmdToken2;
1901         UINT32       CmdToken3;
1902     } field;
1903     UINT32           word;
1904 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
1905 #endif
1906
1907
1908 //NAV_TIME_CFG :NAV
1909 #ifdef RT_BIG_ENDIAN
1910 typedef union   _NAV_TIME_CFG_STRUC     {
1911         struct  {
1912                 USHORT          rsv:6;
1913                 USHORT          ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
1914                 USHORT          Eifs:9;               // in unit of 1-us
1915                 UCHAR       SlotTime;    // in unit of 1-us
1916                 UCHAR           Sifs;               // in unit of 1-us
1917         }       field;
1918         UINT32                  word;
1919 }       NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
1920 #else
1921 typedef union   _NAV_TIME_CFG_STRUC     {
1922         struct  {
1923                 UCHAR           Sifs;               // in unit of 1-us
1924                 UCHAR       SlotTime;    // in unit of 1-us
1925                 USHORT          Eifs:9;               // in unit of 1-us
1926                 USHORT          ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
1927                 USHORT          rsv:6;
1928         }       field;
1929         UINT32                  word;
1930 }       NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
1931 #endif
1932
1933
1934 //
1935 // RX_FILTR_CFG:  /RX configuration register
1936 //
1937 #ifdef RT_BIG_ENDIAN
1938 typedef union   RX_FILTR_CFG_STRUC      {
1939         struct  {
1940                 UINT32          :15;
1941                 UINT32       DropRsvCntlType:1;
1942
1943                 UINT32          DropBAR:1;       //
1944                 UINT32          DropBA:1;               //
1945                 UINT32          DropPsPoll:1;           // Drop Ps-Poll
1946                 UINT32          DropRts:1;              // Drop Ps-Poll
1947
1948                 UINT32          DropCts:1;              // Drop Ps-Poll
1949                 UINT32          DropAck:1;              // Drop Ps-Poll
1950                 UINT32          DropCFEnd:1;            // Drop Ps-Poll
1951                 UINT32          DropCFEndAck:1;         // Drop Ps-Poll
1952
1953                 UINT32          DropDuplicate:1;                // Drop duplicate frame
1954                 UINT32          DropBcast:1;            // Drop broadcast frames
1955                 UINT32          DropMcast:1;            // Drop multicast frames
1956                 UINT32          DropVerErr:1;       // Drop version error frame
1957
1958                 UINT32          DropNotMyBSSID:1;                       // Drop fram ToDs bit is true
1959                 UINT32          DropNotToMe:1;          // Drop not to me unicast frame
1960                 UINT32          DropPhyErr:1;           // Drop physical error
1961                 UINT32          DropCRCErr:1;           // Drop CRC error
1962         }       field;
1963         UINT32                  word;
1964 }       RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
1965 #else
1966 typedef union   _RX_FILTR_CFG_STRUC     {
1967         struct  {
1968                 UINT32          DropCRCErr:1;           // Drop CRC error
1969                 UINT32          DropPhyErr:1;           // Drop physical error
1970                 UINT32          DropNotToMe:1;          // Drop not to me unicast frame
1971                 UINT32          DropNotMyBSSID:1;                       // Drop fram ToDs bit is true
1972
1973                 UINT32          DropVerErr:1;       // Drop version error frame
1974                 UINT32          DropMcast:1;            // Drop multicast frames
1975                 UINT32          DropBcast:1;            // Drop broadcast frames
1976                 UINT32          DropDuplicate:1;                // Drop duplicate frame
1977
1978                 UINT32          DropCFEndAck:1;         // Drop Ps-Poll
1979                 UINT32          DropCFEnd:1;            // Drop Ps-Poll
1980                 UINT32          DropAck:1;              // Drop Ps-Poll
1981                 UINT32          DropCts:1;              // Drop Ps-Poll
1982
1983                 UINT32          DropRts:1;              // Drop Ps-Poll
1984                 UINT32          DropPsPoll:1;           // Drop Ps-Poll
1985                 UINT32          DropBA:1;               //
1986                 UINT32          DropBAR:1;       //
1987
1988                 UINT32          DropRsvCntlType:1;
1989                 UINT32          :15;
1990         }       field;
1991         UINT32                  word;
1992 }       RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
1993 #endif
1994
1995
1996
1997
1998 //
1999 // PHY_CSR4: RF serial control register
2000 //
2001 #ifdef RT_BIG_ENDIAN
2002 typedef union   _PHY_CSR4_STRUC {
2003         struct  {
2004                 UINT32          Busy:1;                         // 1: ASIC is busy execute RF programming.
2005                 UINT32          PLL_LD:1;                       // RF PLL_LD status
2006                 UINT32          IFSelect:1;                     // 1: select IF to program,     0: select RF to program
2007                 UINT32          NumberOfBits:5;         // Number of bits used in RFRegValue (I:20,     RFMD:22)
2008                 UINT32          RFRegValue:24;          // Register     value (include register id)     serial out to RF/IF     chip.
2009         }       field;
2010         UINT32                  word;
2011 }       PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
2012 #else
2013 typedef union   _PHY_CSR4_STRUC {
2014         struct  {
2015                 UINT32          RFRegValue:24;          // Register     value (include register id)     serial out to RF/IF     chip.
2016                 UINT32          NumberOfBits:5;         // Number of bits used in RFRegValue (I:20,     RFMD:22)
2017                 UINT32          IFSelect:1;                     // 1: select IF to program,     0: select RF to program
2018                 UINT32          PLL_LD:1;                       // RF PLL_LD status
2019                 UINT32          Busy:1;                         // 1: ASIC is busy execute RF programming.
2020         }       field;
2021         UINT32                  word;
2022 }       PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
2023 #endif
2024
2025
2026 //
2027 // SEC_CSR5: shared key table security mode register
2028 //
2029 #ifdef RT_BIG_ENDIAN
2030 typedef union   _SEC_CSR5_STRUC {
2031         struct  {
2032         UINT32       :1;
2033         UINT32       Bss3Key3CipherAlg:3;
2034         UINT32       :1;
2035         UINT32       Bss3Key2CipherAlg:3;
2036         UINT32       :1;
2037         UINT32       Bss3Key1CipherAlg:3;
2038         UINT32       :1;
2039         UINT32       Bss3Key0CipherAlg:3;
2040         UINT32       :1;
2041         UINT32       Bss2Key3CipherAlg:3;
2042         UINT32       :1;
2043         UINT32       Bss2Key2CipherAlg:3;
2044         UINT32       :1;
2045         UINT32       Bss2Key1CipherAlg:3;
2046         UINT32       :1;
2047         UINT32       Bss2Key0CipherAlg:3;
2048         }       field;
2049         UINT32                  word;
2050 }       SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
2051 #else
2052 typedef union   _SEC_CSR5_STRUC {
2053         struct  {
2054         UINT32       Bss2Key0CipherAlg:3;
2055         UINT32       :1;
2056         UINT32       Bss2Key1CipherAlg:3;
2057         UINT32       :1;
2058         UINT32       Bss2Key2CipherAlg:3;
2059         UINT32       :1;
2060         UINT32       Bss2Key3CipherAlg:3;
2061         UINT32       :1;
2062         UINT32       Bss3Key0CipherAlg:3;
2063         UINT32       :1;
2064         UINT32       Bss3Key1CipherAlg:3;
2065         UINT32       :1;
2066         UINT32       Bss3Key2CipherAlg:3;
2067         UINT32       :1;
2068         UINT32       Bss3Key3CipherAlg:3;
2069         UINT32       :1;
2070         }       field;
2071         UINT32                  word;
2072 }       SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
2073 #endif
2074
2075
2076 //
2077 // HOST_CMD_CSR: For HOST to interrupt embedded processor
2078 //
2079 #ifdef RT_BIG_ENDIAN
2080 typedef union   _HOST_CMD_CSR_STRUC     {
2081         struct  {
2082             UINT32   Rsv:24;
2083             UINT32   HostCommand:8;
2084         }       field;
2085         UINT32                  word;
2086 }       HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
2087 #else
2088 typedef union   _HOST_CMD_CSR_STRUC     {
2089         struct  {
2090             UINT32   HostCommand:8;
2091             UINT32   Rsv:24;
2092         }       field;
2093         UINT32                  word;
2094 }       HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
2095 #endif
2096
2097
2098 //
2099 // AIFSN_CSR: AIFSN for each EDCA AC
2100 //
2101
2102
2103
2104 //
2105 // E2PROM_CSR: EEPROM control register
2106 //
2107 #ifdef RT_BIG_ENDIAN
2108 typedef union   _E2PROM_CSR_STRUC       {
2109         struct  {
2110                 UINT32          Rsvd:25;
2111                 UINT32       LoadStatus:1;   // 1:loading, 0:done
2112                 UINT32          Type:1;                 // 1: 93C46, 0:93C66
2113                 UINT32          EepromDO:1;
2114                 UINT32          EepromDI:1;
2115                 UINT32          EepromCS:1;
2116                 UINT32          EepromSK:1;
2117                 UINT32          Reload:1;               // Reload EEPROM content, write one to reload, self-cleared.
2118         }       field;
2119         UINT32                  word;
2120 }       E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
2121 #else
2122 typedef union   _E2PROM_CSR_STRUC       {
2123         struct  {
2124                 UINT32          Reload:1;               // Reload EEPROM content, write one to reload, self-cleared.
2125                 UINT32          EepromSK:1;
2126                 UINT32          EepromCS:1;
2127                 UINT32          EepromDI:1;
2128                 UINT32          EepromDO:1;
2129                 UINT32          Type:1;                 // 1: 93C46, 0:93C66
2130                 UINT32       LoadStatus:1;   // 1:loading, 0:done
2131                 UINT32          Rsvd:25;
2132         }       field;
2133         UINT32                  word;
2134 }       E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
2135 #endif
2136
2137 //
2138 // QOS_CSR0: TXOP holder address0 register
2139 //
2140 #ifdef RT_BIG_ENDIAN
2141 typedef union   _QOS_CSR0_STRUC {
2142         struct  {
2143                 UCHAR           Byte3;          // MAC address byte 3
2144                 UCHAR           Byte2;          // MAC address byte 2
2145                 UCHAR           Byte1;          // MAC address byte 1
2146                 UCHAR           Byte0;          // MAC address byte 0
2147         }       field;
2148         UINT32                  word;
2149 }       QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
2150 #else
2151 typedef union   _QOS_CSR0_STRUC {
2152         struct  {
2153                 UCHAR           Byte0;          // MAC address byte 0
2154                 UCHAR           Byte1;          // MAC address byte 1
2155                 UCHAR           Byte2;          // MAC address byte 2
2156                 UCHAR           Byte3;          // MAC address byte 3
2157         }       field;
2158         UINT32                  word;
2159 }       QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
2160 #endif
2161
2162 //
2163 // QOS_CSR1: TXOP holder address1 register
2164 //
2165 #ifdef RT_BIG_ENDIAN
2166 typedef union   _QOS_CSR1_STRUC {
2167         struct  {
2168                 UCHAR           Rsvd1;
2169                 UCHAR           Rsvd0;
2170                 UCHAR           Byte5;          // MAC address byte 5
2171                 UCHAR           Byte4;          // MAC address byte 4
2172         }       field;
2173         UINT32                  word;
2174 }       QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
2175 #else
2176 typedef union   _QOS_CSR1_STRUC {
2177         struct  {
2178                 UCHAR           Byte4;          // MAC address byte 4
2179                 UCHAR           Byte5;          // MAC address byte 5
2180                 UCHAR           Rsvd0;
2181                 UCHAR           Rsvd1;
2182         }       field;
2183         UINT32                  word;
2184 }       QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
2185 #endif
2186
2187 #define RF_CSR_CFG      0x500
2188 #ifdef RT_BIG_ENDIAN
2189 typedef union   _RF_CSR_CFG_STRUC       {
2190         struct  {
2191                 UINT    Rsvd1:14;                               // Reserved
2192                 UINT    RF_CSR_KICK:1;                  // kick RF register read/write
2193                 UINT    RF_CSR_WR:1;                    // 0: read  1: write
2194                 UINT    Rsvd2:3;                                // Reserved
2195                 UINT    TESTCSR_RFACC_REGNUM:5; // RF register ID
2196                 UINT    RF_CSR_DATA:8;                  // DATA
2197         }       field;
2198         UINT    word;
2199 }       RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
2200 #else
2201 typedef union   _RF_CSR_CFG_STRUC       {
2202         struct  {
2203                 UINT    RF_CSR_DATA:8;                  // DATA
2204                 UINT    TESTCSR_RFACC_REGNUM:5; // RF register ID
2205                 UINT    Rsvd2:3;                                // Reserved
2206                 UINT    RF_CSR_WR:1;                    // 0: read  1: write
2207                 UINT    RF_CSR_KICK:1;                  // kick RF register read/write
2208                 UINT    Rsvd1:14;                               // Reserved
2209         }       field;
2210         UINT    word;
2211 }       RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
2212 #endif
2213
2214
2215 //
2216 // Other on-chip shared memory space, base = 0x2000
2217 //
2218
2219 // CIS space - base address = 0x2000
2220 #define HW_CIS_BASE             0x2000
2221
2222 // Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
2223 #define HW_CS_CTS_BASE                  0x7700
2224 // DFS CTS frame base address. It's where mac stores CTS frame for DFS.
2225 #define HW_DFS_CTS_BASE                 0x7780
2226 #define HW_CTS_FRAME_SIZE               0x80
2227
2228 // 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
2229 // to save debugging settings
2230 #define HW_DEBUG_SETTING_BASE   0x77f0  // 0x77f0~0x77ff total 16 bytes
2231 #define HW_DEBUG_SETTING_BASE2   0x7770  // 0x77f0~0x77ff total 16 bytes
2232
2233 // In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
2234 // Three section discontinue memory segments will be used.
2235 // 1. The original region for BCN 0~3
2236 // 2. Extract memory from FCE table for BCN 4~5
2237 // 3. Extract memory from Pair-wise key table for BCN 6~7
2238 //        It occupied those memory of wcid 238~253 for BCN 6
2239 //                                                    and wcid 222~237 for BCN 7
2240 #define HW_BEACON_MAX_SIZE      0x1000 /* unit: byte */
2241 #define HW_BEACON_BASE0         0x7800
2242 #define HW_BEACON_BASE1         0x7A00
2243 #define HW_BEACON_BASE2         0x7C00
2244 #define HW_BEACON_BASE3         0x7E00
2245 #define HW_BEACON_BASE4         0x7200
2246 #define HW_BEACON_BASE5         0x7400
2247 #define HW_BEACON_BASE6         0x5DC0
2248 #define HW_BEACON_BASE7         0x5BC0
2249
2250 #define HW_BEACON_MAX_COUNT     8
2251 #define HW_BEACON_OFFSET                0x0200
2252 #define HW_BEACON_CONTENT_LEN   (HW_BEACON_OFFSET - TXWI_SIZE)
2253
2254 // HOST-MCU shared memory - base address = 0x2100
2255 #define HOST_CMD_CSR            0x404
2256 #define H2M_MAILBOX_CSR         0x7010
2257 #define H2M_MAILBOX_CID         0x7014
2258 #define H2M_MAILBOX_STATUS      0x701c
2259 #define H2M_INT_SRC             0x7024
2260 #define H2M_BBP_AGENT           0x7028
2261 #define M2H_CMD_DONE_CSR        0x000c
2262 #define MCU_TXOP_ARRAY_BASE     0x000c   // TODO: to be provided by Albert
2263 #define MCU_TXOP_ENTRY_SIZE     32       // TODO: to be provided by Albert
2264 #define MAX_NUM_OF_TXOP_ENTRY   16       // TODO: must be same with 8051 firmware
2265 #define MCU_MBOX_VERSION        0x01     // TODO: to be confirmed by Albert
2266 #define MCU_MBOX_VERSION_OFFSET 5        // TODO: to be provided by Albert
2267
2268 //
2269 // Host DMA registers - base address 0x200 .  TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
2270 //
2271 //
2272 //  DMA RING DESCRIPTOR
2273 //
2274 #define E2PROM_CSR          0x0004
2275 #define IO_CNTL_CSR         0x77d0
2276
2277
2278
2279 // ================================================================
2280 // Tx / Rx / Mgmt ring descriptor definition
2281 // ================================================================
2282
2283 // the following PID values are used to mark outgoing frame type in TXD->PID so that
2284 // proper TX statistics can be collected based on these categories
2285 // b3-2 of PID field -
2286 #define PID_MGMT                        0x05
2287 #define PID_BEACON                      0x0c
2288 #define PID_DATA_NORMALUCAST            0x02
2289 #define PID_DATA_AMPDU          0x04
2290 #define PID_DATA_NO_ACK         0x08
2291 #define PID_DATA_NOT_NORM_ACK           0x03
2292 // value domain of pTxD->HostQId (4-bit: 0~15)
2293 #define QID_AC_BK               1   // meet ACI definition in 802.11e
2294 #define QID_AC_BE               0   // meet ACI definition in 802.11e
2295 #define QID_AC_VI               2
2296 #define QID_AC_VO               3
2297 #define QID_HCCA                4
2298 //#define NUM_OF_TX_RING          5
2299 #define NUM_OF_TX_RING          4
2300 #define QID_MGMT                13
2301 #define QID_RX                  14
2302 #define QID_OTHER               15
2303
2304 #endif // __RTMP_MAC_H__ //