drivers/staging/rt3090/rt_ate.c

   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26  */
  27
  28 #include "rt_config.h"
  29
  30 #ifdef RALINK_ATE
  31
  32 #ifdef RT30xx
  33 #define ATE_BBP_REG_NUM 168
  34 UCHAR restore_BBP[ATE_BBP_REG_NUM]={0};
  35 #endif // RT30xx //
  36
  37 // 802.11 MAC Header, Type:Data, Length:24bytes
  38 UCHAR TemplateFrame[24] = {0x08,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
  39                 0x00,0xAA,0xBB,0x12,0x34,0x56,0x00,0x11,0x22,0xAA,0xBB,0xCC,0x00,0x00};
  40
  41 extern RTMP_RF_REGS RF2850RegTable[];
  42 extern UCHAR NUM_OF_2850_CHNL;
  43
  44 extern FREQUENCY_ITEM FreqItems3020[];
  45 extern UCHAR NUM_OF_3020_CHNL;
  46
  47
  48
  49
  50 static CHAR CCKRateTable[] = {0, 1, 2, 3, 8, 9, 10, 11, -1}; /* CCK Mode. */
  51 static CHAR OFDMRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, -1}; /* OFDM Mode. */
  52 static CHAR HTMIXRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}; /* HT Mix Mode. */
  53
  54 static INT TxDmaBusy(
  55         IN PRTMP_ADAPTER pAd);
  56
  57 static INT RxDmaBusy(
  58         IN PRTMP_ADAPTER pAd);
  59
  60 static VOID RtmpDmaEnable(
  61         IN PRTMP_ADAPTER pAd,
  62         IN INT Enable);
  63
  64 static VOID BbpSoftReset(
  65         IN PRTMP_ADAPTER pAd);
  66
  67 static VOID RtmpRfIoWrite(
  68         IN PRTMP_ADAPTER pAd);
  69
  70 static INT ATESetUpFrame(
  71         IN PRTMP_ADAPTER pAd,
  72         IN UINT32 TxIdx);
  73
  74 static INT ATETxPwrHandler(
  75         IN PRTMP_ADAPTER pAd,
  76         IN char index);
  77
  78 static INT ATECmdHandler(
  79         IN      PRTMP_ADAPTER   pAd,
  80         IN      PSTRING                 arg);
  81
  82 #ifndef RT30xx
  83 static int CheckMCSValid(
  84         IN UCHAR Mode,
  85         IN UCHAR Mcs);
  86 #endif // RT30xx //
  87
  88 #ifdef RT30xx
  89 static int CheckMCSValid(
  90         IN UCHAR Mode,
  91         IN UCHAR Mcs,
  92         IN BOOLEAN bRT2070);
  93 #endif // RT30xx //
  94
  95 #ifdef RTMP_MAC_PCI
  96 static VOID ATEWriteTxWI(
  97         IN      PRTMP_ADAPTER   pAd,
  98         IN      PTXWI_STRUC     pOutTxWI,
  99         IN      BOOLEAN                 FRAG,
 100         IN      BOOLEAN                 CFACK,
 101         IN      BOOLEAN                 InsTimestamp,
 102         IN      BOOLEAN                 AMPDU,
 103         IN      BOOLEAN                 Ack,
 104         IN      BOOLEAN                 NSeq,           // HW new a sequence.
 105         IN      UCHAR                   BASize,
 106         IN      UCHAR                   WCID,
 107         IN      ULONG                   Length,
 108         IN      UCHAR                   PID,
 109         IN      UCHAR                   TID,
 110         IN      UCHAR                   TxRate,
 111         IN      UCHAR                   Txopmode,
 112         IN      BOOLEAN                 CfAck,
 113         IN      HTTRANSMIT_SETTING      *pTransmit);
 114 #endif // RTMP_MAC_PCI //
 115
 116
 117 static VOID SetJapanFilter(
 118         IN      PRTMP_ADAPTER   pAd);
 119
 120
 121 #ifdef RALINK_28xx_QA
 122 static inline INT       DO_RACFG_CMD_ATE_START(
 123         IN      PRTMP_ADAPTER   pAdapter,
 124         IN      struct iwreq    *wrq,
 125         IN struct ate_racfghdr *pRaCfg
 126 );
 127
 128 static inline INT DO_RACFG_CMD_ATE_STOP(
 129         IN      PRTMP_ADAPTER   pAdapter,
 130         IN      struct iwreq    *wrq,
 131         IN struct ate_racfghdr *pRaCfg
 132 );
 133
 134 static inline INT DO_RACFG_CMD_RF_WRITE_ALL(
 135         IN      PRTMP_ADAPTER   pAdapter,
 136         IN      struct iwreq    *wrq,
 137         IN struct ate_racfghdr *pRaCfg
 138 );
 139
 140 static inline INT DO_RACFG_CMD_E2PROM_READ16(
 141         IN      PRTMP_ADAPTER   pAdapter,
 142         IN      struct iwreq    *wrq,
 143         IN struct ate_racfghdr *pRaCfg
 144 );
 145
 146 static inline INT DO_RACFG_CMD_E2PROM_WRITE16(
 147         IN      PRTMP_ADAPTER   pAdapter,
 148         IN      struct iwreq    *wrq,
 149         IN struct ate_racfghdr *pRaCfg
 150 );
 151
 152 static inline INT DO_RACFG_CMD_E2PROM_READ_ALL
 153 (
 154         IN      PRTMP_ADAPTER   pAdapter,
 155         IN      struct iwreq    *wrq,
 156         IN struct ate_racfghdr *pRaCfg
 157 );
 158
 159 static inline INT DO_RACFG_CMD_E2PROM_WRITE_ALL(
 160         IN      PRTMP_ADAPTER   pAdapter,
 161         IN      struct iwreq    *wrq,
 162         IN struct ate_racfghdr *pRaCfg
 163 );
 164
 165 static inline INT DO_RACFG_CMD_IO_READ(
 166         IN      PRTMP_ADAPTER   pAdapter,
 167         IN      struct iwreq    *wrq,
 168         IN struct ate_racfghdr *pRaCfg
 169 );
 170
 171 static inline INT DO_RACFG_CMD_IO_WRITE(
 172         IN      PRTMP_ADAPTER   pAdapter,
 173         IN      struct iwreq    *wrq,
 174         IN struct ate_racfghdr *pRaCfg
 175 );
 176
 177 static inline INT DO_RACFG_CMD_IO_READ_BULK(
 178         IN      PRTMP_ADAPTER   pAdapter,
 179         IN      struct iwreq    *wrq,
 180         IN struct ate_racfghdr *pRaCfg
 181 );
 182
 183 static inline INT DO_RACFG_CMD_BBP_READ8(
 184         IN      PRTMP_ADAPTER   pAdapter,
 185         IN      struct iwreq    *wrq,
 186         IN struct ate_racfghdr *pRaCfg
 187 );
 188
 189 static inline INT DO_RACFG_CMD_BBP_WRITE8(
 190         IN      PRTMP_ADAPTER   pAdapter,
 191         IN      struct iwreq    *wrq,
 192         IN struct ate_racfghdr *pRaCfg
 193 );
 194
 195 static inline INT DO_RACFG_CMD_BBP_READ_ALL(
 196         IN      PRTMP_ADAPTER   pAdapter,
 197         IN      struct iwreq    *wrq,
 198         IN struct ate_racfghdr *pRaCfg
 199 );
 200
 201 static inline INT DO_RACFG_CMD_GET_NOISE_LEVEL(
 202         IN      PRTMP_ADAPTER   pAdapter,
 203         IN      struct iwreq    *wrq,
 204         IN struct ate_racfghdr *pRaCfg
 205 );
 206
 207 static inline INT DO_RACFG_CMD_GET_COUNTER(
 208         IN      PRTMP_ADAPTER   pAdapter,
 209         IN      struct iwreq    *wrq,
 210         IN struct ate_racfghdr *pRaCfg
 211 );
 212
 213 static inline INT DO_RACFG_CMD_CLEAR_COUNTER(
 214         IN      PRTMP_ADAPTER   pAdapter,
 215         IN      struct iwreq    *wrq,
 216         IN struct ate_racfghdr *pRaCfg
 217 );
 218
 219 static inline INT DO_RACFG_CMD_TX_START(
 220         IN      PRTMP_ADAPTER   pAdapter,
 221         IN      struct iwreq    *wrq,
 222         IN struct ate_racfghdr *pRaCfg
 223 );
 224
 225 static inline INT DO_RACFG_CMD_GET_TX_STATUS(
 226         IN      PRTMP_ADAPTER   pAdapter,
 227         IN      struct iwreq    *wrq,
 228         IN struct ate_racfghdr *pRaCfg
 229 );
 230
 231 static inline INT DO_RACFG_CMD_TX_STOP(
 232         IN      PRTMP_ADAPTER   pAdapter,
 233         IN      struct iwreq    *wrq,
 234         IN struct ate_racfghdr *pRaCfg
 235 );
 236
 237 static inline INT DO_RACFG_CMD_RX_START(
 238         IN      PRTMP_ADAPTER   pAdapter,
 239         IN      struct iwreq    *wrq,
 240         IN struct ate_racfghdr *pRaCfg
 241 );
 242
 243 static inline INT DO_RACFG_CMD_RX_STOP(
 244         IN      PRTMP_ADAPTER   pAdapter,
 245         IN      struct iwreq    *wrq,
 246         IN struct ate_racfghdr *pRaCfg
 247 );
 248
 249 static inline INT DO_RACFG_CMD_RX_STOP(
 250         IN      PRTMP_ADAPTER   pAdapter,
 251         IN      struct iwreq    *wrq,
 252         IN struct ate_racfghdr *pRaCfg
 253 );
 254
 255 static inline INT DO_RACFG_CMD_ATE_START_TX_CARRIER(
 256         IN      PRTMP_ADAPTER   pAdapter,
 257         IN      struct iwreq    *wrq,
 258         IN struct ate_racfghdr *pRaCfg
 259 );
 260
 261 static inline INT DO_RACFG_CMD_ATE_START_TX_CONT(
 262         IN      PRTMP_ADAPTER   pAdapter,
 263         IN      struct iwreq    *wrq,
 264         IN struct ate_racfghdr *pRaCfg
 265 );
 266
 267 static inline INT DO_RACFG_CMD_ATE_START_TX_FRAME(
 268         IN      PRTMP_ADAPTER   pAdapter,
 269         IN      struct iwreq    *wrq,
 270         IN struct ate_racfghdr *pRaCfg
 271 );
 272
 273 static inline INT DO_RACFG_CMD_ATE_SET_BW(
 274         IN      PRTMP_ADAPTER   pAdapter,
 275         IN      struct iwreq    *wrq,
 276         IN struct ate_racfghdr *pRaCfg
 277 );
 278
 279 static inline INT DO_RACFG_CMD_ATE_SET_TX_POWER0(
 280         IN      PRTMP_ADAPTER   pAdapter,
 281         IN      struct iwreq    *wrq,
 282         IN struct ate_racfghdr *pRaCfg
 283 );
 284
 285 static inline INT DO_RACFG_CMD_ATE_SET_TX_POWER1(
 286         IN      PRTMP_ADAPTER   pAdapter,
 287         IN      struct iwreq    *wrq,
 288         IN struct ate_racfghdr *pRaCfg
 289 );
 290
 291 static inline INT DO_RACFG_CMD_ATE_SET_FREQ_OFFSET(
 292         IN      PRTMP_ADAPTER   pAdapter,
 293         IN      struct iwreq    *wrq,
 294         IN struct ate_racfghdr *pRaCfg
 295 );
 296
 297 static inline INT DO_RACFG_CMD_ATE_GET_STATISTICS(
 298         IN      PRTMP_ADAPTER   pAdapter,
 299         IN      struct iwreq    *wrq,
 300         IN struct ate_racfghdr *pRaCfg
 301 );
 302
 303 static inline INT DO_RACFG_CMD_ATE_RESET_COUNTER(
 304         IN      PRTMP_ADAPTER   pAdapter,
 305         IN      struct iwreq    *wrq,
 306         IN struct ate_racfghdr *pRaCfg
 307 );
 308
 309 static inline INT DO_RACFG_CMD_ATE_SEL_TX_ANTENNA(
 310         IN      PRTMP_ADAPTER   pAdapter,
 311         IN      struct iwreq    *wrq,
 312         IN struct ate_racfghdr *pRaCfg
 313 );
 314
 315 static inline INT DO_RACFG_CMD_ATE_SEL_RX_ANTENNA(
 316         IN      PRTMP_ADAPTER   pAdapter,
 317         IN      struct iwreq    *wrq,
 318         IN struct ate_racfghdr *pRaCfg
 319 );
 320
 321 static inline INT DO_RACFG_CMD_ATE_SET_PREAMBLE(
 322         IN      PRTMP_ADAPTER   pAdapter,
 323         IN      struct iwreq    *wrq,
 324         IN struct ate_racfghdr *pRaCfg
 325 );
 326
 327 static inline INT DO_RACFG_CMD_ATE_SET_CHANNEL(
 328         IN      PRTMP_ADAPTER   pAdapter,
 329         IN      struct iwreq    *wrq,
 330         IN struct ate_racfghdr *pRaCfg
 331 );
 332
 333 static inline INT DO_RACFG_CMD_ATE_SET_ADDR1(
 334         IN      PRTMP_ADAPTER   pAdapter,
 335         IN      struct iwreq    *wrq,
 336         IN struct ate_racfghdr *pRaCfg
 337 );
 338
 339 static inline INT DO_RACFG_CMD_ATE_SET_ADDR2(
 340         IN      PRTMP_ADAPTER   pAdapter,
 341         IN      struct iwreq    *wrq,
 342         IN struct ate_racfghdr *pRaCfg
 343 );
 344
 345 static inline INT DO_RACFG_CMD_ATE_SET_ADDR3(
 346         IN      PRTMP_ADAPTER   pAdapter,
 347         IN      struct iwreq    *wrq,
 348         IN struct ate_racfghdr *pRaCfg
 349 );
 350
 351 static inline INT DO_RACFG_CMD_ATE_SET_RATE(
 352         IN      PRTMP_ADAPTER   pAdapter,
 353         IN      struct iwreq    *wrq,
 354         IN struct ate_racfghdr *pRaCfg
 355 );
 356
 357 static inline INT DO_RACFG_CMD_ATE_SET_TX_FRAME_LEN(
 358         IN      PRTMP_ADAPTER   pAdapter,
 359         IN      struct iwreq    *wrq,
 360         IN struct ate_racfghdr *pRaCfg
 361 );
 362
 363 static inline INT DO_RACFG_CMD_ATE_SET_TX_FRAME_COUNT(
 364         IN      PRTMP_ADAPTER   pAdapter,
 365         IN      struct iwreq    *wrq,
 366         IN struct ate_racfghdr *pRaCfg
 367 );
 368
 369 static inline INT DO_RACFG_CMD_ATE_START_RX_FRAME(
 370         IN      PRTMP_ADAPTER   pAdapter,
 371         IN      struct iwreq    *wrq,
 372         IN struct ate_racfghdr *pRaCfg
 373 );
 374
 375 static inline INT DO_RACFG_CMD_ATE_E2PROM_READ_BULK(
 376         IN      PRTMP_ADAPTER   pAdapter,
 377         IN      struct iwreq    *wrq,
 378         IN struct ate_racfghdr *pRaCfg
 379 );
 380
 381 static inline INT DO_RACFG_CMD_ATE_E2PROM_WRITE_BULK(
 382         IN      PRTMP_ADAPTER   pAdapter,
 383         IN      struct iwreq    *wrq,
 384         IN struct ate_racfghdr *pRaCfg
 385 );
 386
 387 static inline INT DO_RACFG_CMD_ATE_IO_WRITE_BULK(
 388         IN      PRTMP_ADAPTER   pAdapter,
 389         IN      struct iwreq    *wrq,
 390         IN struct ate_racfghdr *pRaCfg
 391 );
 392
 393 static inline INT DO_RACFG_CMD_ATE_BBP_READ_BULK(
 394         IN      PRTMP_ADAPTER   pAdapter,
 395         IN      struct iwreq    *wrq,
 396         IN struct ate_racfghdr *pRaCfg
 397 );
 398
 399 static inline INT DO_RACFG_CMD_ATE_BBP_WRITE_BULK(
 400         IN      PRTMP_ADAPTER   pAdapter,
 401         IN      struct iwreq    *wrq,
 402         IN struct ate_racfghdr *pRaCfg
 403 );
 404
 405 #endif // RALINK_28xx_QA //
 406
 407
 408 #ifdef RTMP_MAC_PCI
 409 static INT TxDmaBusy(
 410         IN PRTMP_ADAPTER pAd)
 411 {
 412         INT result;
 413         WPDMA_GLO_CFG_STRUC GloCfg;
 414
 415         RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);       // disable DMA
 416         if (GloCfg.field.TxDMABusy)
 417                 result = 1;
 418         else
 419                 result = 0;
 420
 421         return result;
 422 }
 423
 424
 425 static INT RxDmaBusy(
 426         IN PRTMP_ADAPTER pAd)
 427 {
 428         INT result;
 429         WPDMA_GLO_CFG_STRUC GloCfg;
 430
 431         RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);       // disable DMA
 432         if (GloCfg.field.RxDMABusy)
 433                 result = 1;
 434         else
 435                 result = 0;
 436
 437         return result;
 438 }
 439
 440
 441 static VOID RtmpDmaEnable(
 442         IN PRTMP_ADAPTER pAd,
 443         IN INT Enable)
 444 {
 445         BOOLEAN value;
 446         ULONG WaitCnt;
 447         WPDMA_GLO_CFG_STRUC GloCfg;
 448
 449         value = Enable > 0 ? 1 : 0;
 450
 451         // check DMA is in busy mode.
 452         WaitCnt = 0;
 453
 454         while (TxDmaBusy(pAd) || RxDmaBusy(pAd))
 455         {
 456                 RTMPusecDelay(10);
 457                 if (WaitCnt++ > 100)
 458                         break;
 459         }
 460
 461         RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);       // disable DMA
 462         GloCfg.field.EnableTxDMA = value;
 463         GloCfg.field.EnableRxDMA = value;
 464         RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);       // abort all TX rings
 465         RTMPusecDelay(5000);
 466
 467         return;
 468 }
 469 #endif // RTMP_MAC_PCI //
 470
 471
 472
 473
 474 static VOID BbpSoftReset(
 475         IN PRTMP_ADAPTER pAd)
 476 {
 477         UCHAR BbpData = 0;
 478
 479         // Soft reset, set BBP R21 bit0=1->0
 480         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData);
 481         BbpData |= 0x00000001; //set bit0=1
 482         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData);
 483
 484         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData);
 485         BbpData &= ~(0x00000001); //set bit0=0
 486         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData);
 487
 488         return;
 489 }
 490
 491
 492 static VOID RtmpRfIoWrite(
 493         IN PRTMP_ADAPTER pAd)
 494 {
 495         // Set RF value 1's set R3[bit2] = [0]
 496         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
 497         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
 498         RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
 499         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
 500
 501         RTMPusecDelay(200);
 502
 503         // Set RF value 2's set R3[bit2] = [1]
 504         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
 505         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
 506         RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04));
 507         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
 508
 509         RTMPusecDelay(200);
 510
 511         // Set RF value 3's set R3[bit2] = [0]
 512         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
 513         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
 514         RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
 515         RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
 516
 517         return;
 518 }
 519
 520
 521 #ifdef RT30xx
 522 static int CheckMCSValid(
 523         UCHAR Mode,
 524         UCHAR Mcs,
 525         BOOLEAN bRT2070)
 526 #endif // RT30xx //
 527 #ifndef RT30xx
 528 static int CheckMCSValid(
 529         IN UCHAR Mode,
 530         IN UCHAR Mcs)
 531 #endif // RT30xx //
 532 {
 533         INT i;
 534         PCHAR pRateTab;
 535
 536         switch (Mode)
 537         {
 538                 case 0:
 539                         pRateTab = CCKRateTable;
 540                         break;
 541                 case 1:
 542                         pRateTab = OFDMRateTable;
 543                         break;
 544                 case 2:
 545                 case 3:
 546 #ifdef RT30xx
 547                         if (bRT2070)
 548                                 pRateTab = OFDMRateTable;
 549                         else
 550 #endif // RT30xx //
 551                         pRateTab = HTMIXRateTable;
 552                         break;
 553                 default:
 554                         ATEDBGPRINT(RT_DEBUG_ERROR, ("unrecognizable Tx Mode %d\n", Mode));
 555                         return -1;
 556                         break;
 557         }
 558
 559         i = 0;
 560         while (pRateTab[i] != -1)
 561         {
 562                 if (pRateTab[i] == Mcs)
 563                         return 0;
 564                 i++;
 565         }
 566
 567         return -1;
 568 }
 569
 570
 571 static INT ATETxPwrHandler(
 572         IN PRTMP_ADAPTER pAd,
 573         IN char index)
 574 {
 575         ULONG R;
 576         CHAR TxPower;
 577         UCHAR Bbp94 = 0;
 578         BOOLEAN bPowerReduce = FALSE;
 579 #ifdef RTMP_RF_RW_SUPPORT
 580         UCHAR RFValue;
 581 #endif // RTMP_RF_RW_SUPPORT //
 582 #ifdef RALINK_28xx_QA
 583         if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
 584         {
 585                 /*
 586                         When QA is used for Tx, pAd->ate.TxPower0/1 and real tx power
 587                         are not synchronized.
 588                 */
 589                 return 0;
 590         }
 591         else
 592 #endif // RALINK_28xx_QA //
 593         {
 594                 TxPower = index == 0 ? pAd->ate.TxPower0 : pAd->ate.TxPower1;
 595
 596                 if (pAd->ate.Channel <= 14)
 597                 {
 598                         if (TxPower > 31)
 599                         {
 600
 601                                 // R3, R4 can't large than 31 (0x24), 31 ~ 36 used by BBP 94
 602                                 R = 31;
 603                                 if (TxPower <= 36)
 604                                         Bbp94 = BBPR94_DEFAULT + (UCHAR)(TxPower - 31);
 605                         }
 606                         else if (TxPower < 0)
 607                         {
 608
 609                                 // R3, R4 can't less than 0, -1 ~ -6 used by BBP 94
 610                                 R = 0;
 611                                 if (TxPower >= -6)
 612                                         Bbp94 = BBPR94_DEFAULT + TxPower;
 613                         }
 614                         else
 615                         {
 616                                 // 0 ~ 31
 617                                 R = (ULONG) TxPower;
 618                                 Bbp94 = BBPR94_DEFAULT;
 619                         }
 620
 621                         ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%ld, BBP_R94=%d)\n", __FUNCTION__, TxPower, R, Bbp94));
 622                 }
 623                 else /* 5.5 GHz */
 624                 {
 625                         if (TxPower > 15)
 626                         {
 627
 628                                 // R3, R4 can't large than 15 (0x0F)
 629                                 R = 15;
 630                         }
 631                         else if (TxPower < 0)
 632                         {
 633
 634                                 // R3, R4 can't less than 0
 635                                 // -1 ~ -7
 636                                 ASSERT((TxPower >= -7));
 637                                 R = (ULONG)(TxPower + 7);
 638                                 bPowerReduce = TRUE;
 639                         }
 640                         else
 641                         {
 642                                 // 0 ~ 15
 643                                 R = (ULONG) TxPower;
 644                         }
 645
 646                         ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%lu)\n", __FUNCTION__, TxPower, R));
 647                 }
 648 //2008/09/10:KH adds to support 3070 ATE TX Power tunning real time<--
 649 #ifdef RTMP_RF_RW_SUPPORT
 650                 if (IS_RT30xx(pAd))
 651                 {
 652                         // Set Tx Power
 653                         ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R12, (PUCHAR)&RFValue);
 654                         RFValue = (RFValue & 0xE0) | TxPower;
 655                         ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R12, (UCHAR)RFValue);
 656                         ATEDBGPRINT(RT_DEBUG_TRACE, ("3070 or 2070:%s (TxPower=%d, RFValue=%x)\n", __FUNCTION__, TxPower, RFValue));
 657                 }
 658                 else
 659 #endif // RTMP_RF_RW_SUPPORT //
 660                 {
 661                 if (pAd->ate.Channel <= 14)
 662                 {
 663                         if (index == 0)
 664                         {
 665                                 // shift TX power control to correct RF(R3) register bit position
 666                                 R = R << 9;
 667                                 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
 668                                 pAd->LatchRfRegs.R3 = R;
 669                         }
 670                         else
 671                         {
 672                                 // shift TX power control to correct RF(R4) register bit position
 673                                 R = R << 6;
 674                                 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
 675                                 pAd->LatchRfRegs.R4 = R;
 676                         }
 677                 }
 678                 else /* 5.5GHz */
 679                 {
 680                         if (bPowerReduce == FALSE)
 681                         {
 682                                 if (index == 0)
 683                                 {
 684                                         // shift TX power control to correct RF(R3) register bit position
 685                                         R = (R << 10) | (1 << 9);
 686                                         R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
 687                                         pAd->LatchRfRegs.R3 = R;
 688                                 }
 689                                 else
 690                                 {
 691                                         // shift TX power control to correct RF(R4) register bit position
 692                                         R = (R << 7) | (1 << 6);
 693                                         R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
 694                                         pAd->LatchRfRegs.R4 = R;
 695                                 }
 696                         }
 697                         else
 698                         {
 699                                 if (index == 0)
 700                                 {
 701                                         // shift TX power control to correct RF(R3) register bit position
 702                                         R = (R << 10);
 703                                         R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
 704
 705                                         /* Clear bit 9 of R3 to reduce 7dB. */
 706                                         pAd->LatchRfRegs.R3 = (R & (~(1 << 9)));
 707                                 }
 708                                 else
 709                                 {
 710                                         // shift TX power control to correct RF(R4) register bit position
 711                                         R = (R << 7);
 712                                         R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
 713
 714                                         /* Clear bit 6 of R4 to reduce 7dB. */
 715                                         pAd->LatchRfRegs.R4 = (R & (~(1 << 6)));
 716                                 }
 717                         }
 718                 }
 719                 RtmpRfIoWrite(pAd);
 720         }
 721 //2008/09/10:KH adds to support 3070 ATE TX Power tunning real time-->
 722
 723                 return 0;
 724         }
 725 }
 726
 727
 728 /*
 729 ==========================================================================
 730     Description:
 731         Set ATE operation mode to
 732         0. ATESTART  = Start ATE Mode
 733         1. ATESTOP   = Stop ATE Mode
 734         2. TXCONT    = Continuous Transmit
 735         3. TXCARR    = Transmit Carrier
 736         4. TXFRAME   = Transmit Frames
 737         5. RXFRAME   = Receive Frames
 738 #ifdef RALINK_28xx_QA
 739         6. TXSTOP    = Stop Any Type of Transmition
 740         7. RXSTOP    = Stop Receiving Frames
 741 #endif // RALINK_28xx_QA //
 742     Return:
 743         TRUE if all parameters are OK, FALSE otherwise
 744 ==========================================================================
 745 */
 746 #ifdef RTMP_MAC_PCI
 747 static INT      ATECmdHandler(
 748         IN      PRTMP_ADAPTER   pAd,
 749         IN      PSTRING                 arg)
 750 {
 751         UINT32                  Value = 0;
 752         UCHAR                   BbpData;
 753         UINT32                  MacData = 0;
 754         PTXD_STRUC              pTxD;
 755         INT                             index;
 756         UINT                    i = 0, atemode = 0;
 757         PRXD_STRUC              pRxD;
 758         PRTMP_TX_RING   pTxRing = &pAd->TxRing[QID_AC_BE];
 759         NDIS_STATUS             Status = NDIS_STATUS_SUCCESS;
 760 #ifdef  RT_BIG_ENDIAN
 761     PTXD_STRUC      pDestTxD;
 762     TXD_STRUC       TxD;
 763 #endif
 764
 765         ATEDBGPRINT(RT_DEBUG_TRACE, ("===> ATECmdHandler()\n"));
 766
 767         ATEAsicSwitchChannel(pAd);
 768
 769         /* empty function */
 770         AsicLockChannel(pAd, pAd->ate.Channel);
 771
 772         RTMPusecDelay(5000);
 773
 774         // read MAC_SYS_CTRL and backup MAC_SYS_CTRL value.
 775         RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
 776
 777         // Default value in BBP R22 is 0x0.
 778         BbpData = 0;
 779
 780         // clean bit4 to stop continuous Tx production test.
 781         MacData &= 0xFFFFFFEF;
 782
 783         // Enter ATE mode and set Tx/Rx Idle
 784         if (!strcmp(arg, "ATESTART"))
 785         {
 786                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: ATESTART\n"));
 787
 788 #if defined(LINUX) || defined(VXWORKS)
 789                 // check if we have removed the firmware
 790                 if (!(ATE_ON(pAd)))
 791                 {
 792                         NICEraseFirmware(pAd);
 793                 }
 794 #endif // defined(LINUX) || defined(VXWORKS) //
 795
 796                 atemode = pAd->ate.Mode;
 797                 pAd->ate.Mode = ATE_START;
 798                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
 799
 800                 if (atemode == ATE_TXCARR)
 801                 {
 802                         // No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0
 803                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
 804                         BbpData &= 0xFFFFFF00; // clear bit7, bit6, bit[5~0]
 805                     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
 806                 }
 807                 else if (atemode == ATE_TXCARRSUPP)
 808                 {
 809                         // No Cont. TX set BBP R22 bit7=0
 810                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
 811                         BbpData &= ~(1 << 7); // set bit7=0
 812                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
 813
 814                         // No Carrier Suppression set BBP R24 bit0=0
 815                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &BbpData);
 816                         BbpData &= 0xFFFFFFFE; // clear bit0
 817                     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, BbpData);
 818                 }
 819
 820                 /*
 821                         We should free some resource which was allocated
 822                         when ATE_TXFRAME , ATE_STOP, and ATE_TXCONT.
 823                 */
 824                 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
 825                 {
 826                         PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
 827
 828                         if (atemode == ATE_TXCONT)
 829                         {
 830                                 // No Cont. TX set BBP R22 bit7=0
 831                                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
 832                                 BbpData &= ~(1 << 7); // set bit7=0
 833                                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
 834                         }
 835
 836                         // Abort Tx, Rx DMA.
 837                         RtmpDmaEnable(pAd, 0);
 838                         for (i=0; i<TX_RING_SIZE; i++)
 839                         {
 840                                 PNDIS_PACKET  pPacket;
 841
 842 #ifndef RT_BIG_ENDIAN
 843                             pTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
 844 #else
 845                         pDestTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
 846                         TxD = *pDestTxD;
 847                         pTxD = &TxD;
 848                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
 849 #endif
 850                                 pTxD->DMADONE = 0;
 851                                 pPacket = pTxRing->Cell[i].pNdisPacket;
 852
 853                                 if (pPacket)
 854                                 {
 855                                         PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
 856                                         RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
 857                                 }
 858
 859                                 // Always assign pNdisPacket as NULL after clear
 860                                 pTxRing->Cell[i].pNdisPacket = NULL;
 861
 862                                 pPacket = pTxRing->Cell[i].pNextNdisPacket;
 863
 864                                 if (pPacket)
 865                                 {
 866                                         PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
 867                                         RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
 868                                 }
 869
 870                                 // Always assign pNextNdisPacket as NULL after clear
 871                                 pTxRing->Cell[i].pNextNdisPacket = NULL;
 872 #ifdef RT_BIG_ENDIAN
 873                                 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
 874                                 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
 875 #endif
 876                         }
 877
 878                         // Start Tx, RX DMA
 879                         RtmpDmaEnable(pAd, 1);
 880                 }
 881
 882                 // reset Rx statistics.
 883                 pAd->ate.LastSNR0 = 0;
 884                 pAd->ate.LastSNR1 = 0;
 885                 pAd->ate.LastRssi0 = 0;
 886                 pAd->ate.LastRssi1 = 0;
 887                 pAd->ate.LastRssi2 = 0;
 888                 pAd->ate.AvgRssi0 = 0;
 889                 pAd->ate.AvgRssi1 = 0;
 890                 pAd->ate.AvgRssi2 = 0;
 891                 pAd->ate.AvgRssi0X8 = 0;
 892                 pAd->ate.AvgRssi1X8 = 0;
 893                 pAd->ate.AvgRssi2X8 = 0;
 894                 pAd->ate.NumOfAvgRssiSample = 0;
 895
 896 #ifdef RALINK_28xx_QA
 897                 // Tx frame
 898                 pAd->ate.bQATxStart = FALSE;
 899                 pAd->ate.bQARxStart = FALSE;
 900                 pAd->ate.seq = 0;
 901
 902                 // counters
 903                 pAd->ate.U2M = 0;
 904                 pAd->ate.OtherData = 0;
 905                 pAd->ate.Beacon = 0;
 906                 pAd->ate.OtherCount = 0;
 907                 pAd->ate.TxAc0 = 0;
 908                 pAd->ate.TxAc1 = 0;
 909                 pAd->ate.TxAc2 = 0;
 910                 pAd->ate.TxAc3 = 0;
 911                 /*pAd->ate.TxHCCA = 0;*/
 912                 pAd->ate.TxMgmt = 0;
 913                 pAd->ate.RSSI0 = 0;
 914                 pAd->ate.RSSI1 = 0;
 915                 pAd->ate.RSSI2 = 0;
 916                 pAd->ate.SNR0 = 0;
 917                 pAd->ate.SNR1 = 0;
 918
 919                 // control
 920                 pAd->ate.TxDoneCount = 0;
 921                 // TxStatus : 0 --> task is idle, 1 --> task is running
 922                 pAd->ate.TxStatus = 0;
 923 #endif // RALINK_28xx_QA //
 924
 925                 // Soft reset BBP.
 926                 BbpSoftReset(pAd);
 927
 928
 929 #ifdef CONFIG_STA_SUPPORT
 930                 /* LinkDown() has "AsicDisableSync();" and "RTMP_BBP_IO_R/W8_BY_REG_ID();" inside. */
 931 //      LinkDown(pAd, FALSE);
 932 //              AsicEnableBssSync(pAd);
 933
 934 #if defined(LINUX) || defined(VXWORKS)
 935                 RTMP_OS_NETDEV_STOP_QUEUE(pAd->net_dev);
 936 #endif // defined(LINUX) || defined(VXWORKS) //
 937
 938                 /*
 939                         If we skip "LinkDown()", we should disable protection
 940                         to prevent from sending out RTS or CTS-to-self.
 941                 */
 942                 ATEDisableAsicProtect(pAd);
 943                 RTMPStationStop(pAd);
 944 #endif // CONFIG_STA_SUPPORT //
 945
 946                 /* Disable Tx */
 947                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
 948                 Value &= ~(1 << 2);
 949                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
 950
 951                 /* Disable Rx */
 952                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
 953                 Value &= ~(1 << 3);
 954                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
 955         }
 956         else if (!strcmp(arg, "ATESTOP"))
 957         {
 958                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: ATESTOP\n"));
 959
 960                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
 961
 962                 // recover the MAC_SYS_CTRL register back
 963                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
 964
 965                 // disable Tx, Rx
 966                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
 967                 Value &= (0xfffffff3);
 968                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
 969
 970                 // abort Tx, RX DMA
 971                 RtmpDmaEnable(pAd, 0);
 972
 973 #ifdef LINUX
 974                 pAd->ate.bFWLoading = TRUE;
 975
 976                 Status = NICLoadFirmware(pAd);
 977
 978                 if (Status != NDIS_STATUS_SUCCESS)
 979                 {
 980                         ATEDBGPRINT(RT_DEBUG_ERROR, ("NICLoadFirmware failed, Status[=0x%08x]\n", Status));
 981                         return FALSE;
 982                 }
 983 #endif // LINUX //
 984                 pAd->ate.Mode = ATE_STOP;
 985
 986                 /*
 987                         Even the firmware has been loaded,
 988                         we still could use ATE_BBP_IO_READ8_BY_REG_ID().
 989                         But this is not suggested.
 990                 */
 991                 BbpSoftReset(pAd);
 992
 993                 RTMP_ASIC_INTERRUPT_DISABLE(pAd);
 994
 995                 NICInitializeAdapter(pAd, TRUE);
 996
 997                 /*
 998                         Reinitialize Rx Ring before Rx DMA is enabled.
 999                         >>>RxCoherent<<< was gone !
1000                 */
1001                 for (index = 0; index < RX_RING_SIZE; index++)
1002                 {
1003                         pRxD = (PRXD_STRUC) pAd->RxRing.Cell[index].AllocVa;
1004                         pRxD->DDONE = 0;
1005                 }
1006
1007                 // We should read EEPROM for all cases.
1008                 NICReadEEPROMParameters(pAd, NULL);
1009                 NICInitAsicFromEEPROM(pAd);
1010
1011                 AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
1012
1013                 /* empty function */
1014                 AsicLockChannel(pAd, pAd->CommonCfg.Channel);
1015
1016                 /* clear garbage interrupts */
1017                 RTMP_IO_WRITE32(pAd, INT_SOURCE_CSR, 0xffffffff);
1018                 /* Enable Interrupt */
1019                 RTMP_ASIC_INTERRUPT_ENABLE(pAd);
1020
1021                 /* restore RX_FILTR_CFG */
1022
1023 #ifdef CONFIG_STA_SUPPORT
1024                 /* restore RX_FILTR_CFG due to that QA maybe set it to 0x3 */
1025                 RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, STANORMAL);
1026 #endif // CONFIG_STA_SUPPORT //
1027
1028                 // Enable Tx
1029                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1030                 Value |= (1 << 2);
1031                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1032
1033                 // Enable Tx, Rx DMA.
1034                 RtmpDmaEnable(pAd, 1);
1035
1036                 // Enable Rx
1037                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1038                 Value |= (1 << 3);
1039                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1040
1041
1042 #ifdef CONFIG_STA_SUPPORT
1043                 RTMPStationStart(pAd);
1044 #endif // CONFIG_STA_SUPPORT //
1045
1046 #if defined(LINUX) || defined(VXWORKS)
1047                 RTMP_OS_NETDEV_START_QUEUE(pAd->net_dev);
1048 #endif // defined(LINUX) || defined(VXWORKS) //
1049         }
1050         else if (!strcmp(arg, "TXCARR"))
1051         {
1052                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXCARR\n"));
1053                 pAd->ate.Mode = ATE_TXCARR;
1054
1055                 // QA has done the following steps if it is used.
1056                 if (pAd->ate.bQATxStart == FALSE)
1057                 {
1058                         // Soft reset BBP.
1059                         BbpSoftReset(pAd);
1060
1061                         // Carrier Test set BBP R22 bit7=1, bit6=1, bit[5~0]=0x01
1062                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1063                         BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
1064                         BbpData |= 0x000000C1; //set bit7=1, bit6=1, bit[5~0]=0x01
1065                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1066
1067                         // set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1
1068                         RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1069                         Value = Value | 0x00000010;
1070                         RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1071                 }
1072         }
1073         else if (!strcmp(arg, "TXCONT"))
1074         {
1075                 if (pAd->ate.bQATxStart == TRUE)
1076                 {
1077                         /*
1078                                 set MAC_SYS_CTRL(0x1004) bit4(Continuous Tx Production Test)
1079                                 and bit2(MAC TX enable) back to zero.
1080                         */
1081                         RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1082                         MacData &= 0xFFFFFFEB;
1083                         RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1084
1085                         // set BBP R22 bit7=0
1086                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1087                         BbpData &= 0xFFFFFF7F; //set bit7=0
1088                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1089                 }
1090
1091                 /*
1092                         for TxCont mode.
1093                         Step 1: Send 50 packets first then wait for a moment.
1094                         Step 2: Send more 50 packet then start continue mode.
1095                 */
1096                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXCONT\n"));
1097
1098                 // Step 1: send 50 packets first.
1099                 pAd->ate.Mode = ATE_TXCONT;
1100                 pAd->ate.TxCount = 50;
1101
1102                 /* Do it after Tx/Rx DMA is aborted. */
1103 //              pAd->ate.TxDoneCount = 0;
1104
1105                 // Soft reset BBP.
1106                 BbpSoftReset(pAd);
1107
1108                 // Abort Tx, RX DMA.
1109                 RtmpDmaEnable(pAd, 0);
1110
1111                 // Fix can't smooth kick
1112                 {
1113                         RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * 0x10,  &pTxRing->TxDmaIdx);
1114                         pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
1115                         pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
1116                         RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * 0x10, pTxRing->TxCpuIdx);
1117                 }
1118
1119                 pAd->ate.TxDoneCount = 0;
1120
1121                 /* Only needed if we have to send some normal frames. */
1122                 SetJapanFilter(pAd);
1123
1124                 for (i = 0; (i < TX_RING_SIZE-1) && (i < pAd->ate.TxCount); i++)
1125                 {
1126                         PNDIS_PACKET pPacket;
1127                         UINT32 TxIdx = pTxRing->TxCpuIdx;
1128
1129 #ifndef RT_BIG_ENDIAN
1130                         pTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1131 #else
1132                         pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1133                         TxD = *pDestTxD;
1134                         pTxD = &TxD;
1135                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1136 #endif
1137                         // Clean current cell.
1138                         pPacket = pTxRing->Cell[TxIdx].pNdisPacket;
1139
1140                         if (pPacket)
1141                         {
1142                                 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
1143                                 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1144                         }
1145
1146                         // Always assign pNdisPacket as NULL after clear
1147                         pTxRing->Cell[TxIdx].pNdisPacket = NULL;
1148
1149                         pPacket = pTxRing->Cell[TxIdx].pNextNdisPacket;
1150
1151                         if (pPacket)
1152                         {
1153                                 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
1154                                 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1155                         }
1156
1157                         // Always assign pNextNdisPacket as NULL after clear
1158                         pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
1159
1160 #ifdef RT_BIG_ENDIAN
1161                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1162                         WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
1163 #endif
1164
1165                         if (ATESetUpFrame(pAd, TxIdx) != 0)
1166                                 break;
1167
1168                         INC_RING_INDEX(pTxRing->TxCpuIdx, TX_RING_SIZE);
1169                 }
1170
1171                 // Setup frame format.
1172                 ATESetUpFrame(pAd, pTxRing->TxCpuIdx);
1173
1174                 // Start Tx, RX DMA.
1175                 RtmpDmaEnable(pAd, 1);
1176
1177                 // Enable Tx
1178                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1179                 Value |= (1 << 2);
1180                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1181
1182                 // Disable Rx
1183                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1184                 Value &= ~(1 << 3);
1185                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1186
1187 #ifdef RALINK_28xx_QA
1188                 if (pAd->ate.bQATxStart == TRUE)
1189                 {
1190                         pAd->ate.TxStatus = 1;
1191                 }
1192 #endif // RALINK_28xx_QA //
1193
1194                 // kick Tx-Ring
1195                 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * RINGREG_DIFF, pAd->TxRing[QID_AC_BE].TxCpuIdx);
1196
1197                 RTMPusecDelay(5000);
1198
1199
1200                 // Step 2: send more 50 packets then start continue mode.
1201                 // Abort Tx, RX DMA.
1202                 RtmpDmaEnable(pAd, 0);
1203
1204                 // Cont. TX set BBP R22 bit7=1
1205                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1206                 BbpData |= 0x00000080; //set bit7=1
1207                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1208
1209                 pAd->ate.TxCount = 50;
1210
1211                 // Fix can't smooth kick
1212                 {
1213                         RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * 0x10,  &pTxRing->TxDmaIdx);
1214                         pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
1215                         pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
1216                         RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * 0x10, pTxRing->TxCpuIdx);
1217                 }
1218
1219                 pAd->ate.TxDoneCount = 0;
1220
1221                 SetJapanFilter(pAd);
1222
1223                 for (i = 0; (i < TX_RING_SIZE-1) && (i < pAd->ate.TxCount); i++)
1224                 {
1225                         PNDIS_PACKET pPacket;
1226                         UINT32 TxIdx = pTxRing->TxCpuIdx;
1227
1228 #ifndef RT_BIG_ENDIAN
1229                         pTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1230 #else
1231                         pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1232                         TxD = *pDestTxD;
1233                         pTxD = &TxD;
1234                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1235 #endif
1236                         // clean current cell.
1237                         pPacket = pTxRing->Cell[TxIdx].pNdisPacket;
1238
1239                         if (pPacket)
1240                         {
1241                                 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
1242                                 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1243                         }
1244
1245                         // Always assign pNdisPacket as NULL after clear
1246                         pTxRing->Cell[TxIdx].pNdisPacket = NULL;
1247
1248                         pPacket = pTxRing->Cell[TxIdx].pNextNdisPacket;
1249
1250                         if (pPacket)
1251                         {
1252                                 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
1253                                 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1254                         }
1255
1256                         // Always assign pNextNdisPacket as NULL after clear
1257                         pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
1258
1259 #ifdef RT_BIG_ENDIAN
1260                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1261                         WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
1262 #endif
1263
1264                         if (ATESetUpFrame(pAd, TxIdx) != 0)
1265                                 break;
1266
1267                         INC_RING_INDEX(pTxRing->TxCpuIdx, TX_RING_SIZE);
1268                 }
1269
1270                 ATESetUpFrame(pAd, pTxRing->TxCpuIdx);
1271
1272                 // Start Tx, RX DMA.
1273                 RtmpDmaEnable(pAd, 1);
1274
1275                 // Enable Tx
1276                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1277                 Value |= (1 << 2);
1278                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1279
1280                 // Disable Rx
1281                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1282                 Value &= ~(1 << 3);
1283                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1284
1285 #ifdef RALINK_28xx_QA
1286                 if (pAd->ate.bQATxStart == TRUE)
1287                 {
1288                         pAd->ate.TxStatus = 1;
1289                 }
1290 #endif // RALINK_28xx_QA //
1291
1292                 // kick Tx-Ring.
1293                 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * RINGREG_DIFF, pAd->TxRing[QID_AC_BE].TxCpuIdx);
1294
1295                 RTMPusecDelay(500);
1296
1297                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1298                 MacData |= 0x00000010;
1299                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1300         }
1301         else if (!strcmp(arg, "TXFRAME"))
1302         {
1303                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXFRAME(Count=%d)\n", pAd->ate.TxCount));
1304                 pAd->ate.Mode |= ATE_TXFRAME;
1305                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1306
1307                 // Soft reset BBP.
1308                 BbpSoftReset(pAd);
1309                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1310
1311                 // Abort Tx, RX DMA.
1312                 RtmpDmaEnable(pAd, 0);
1313
1314                 // Fix can't smooth kick
1315                 {
1316                         RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * 0x10,  &pTxRing->TxDmaIdx);
1317                         pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
1318                         pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
1319                         RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * 0x10, pTxRing->TxCpuIdx);
1320                 }
1321
1322                 pAd->ate.TxDoneCount = 0;
1323
1324                 SetJapanFilter(pAd);
1325
1326                 for (i = 0; (i < TX_RING_SIZE-1) && (i < pAd->ate.TxCount); i++)
1327                 {
1328                         PNDIS_PACKET pPacket;
1329                         UINT32 TxIdx = pTxRing->TxCpuIdx;
1330
1331 #ifndef RT_BIG_ENDIAN
1332                         pTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1333 #else
1334                         pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
1335                         TxD = *pDestTxD;
1336                         pTxD = &TxD;
1337                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1338 #endif
1339                         // Clean current cell.
1340                         pPacket = pTxRing->Cell[TxIdx].pNdisPacket;
1341
1342                         if (pPacket)
1343                         {
1344                                 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
1345                                 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1346                         }
1347
1348                         // Always assign pNdisPacket as NULL after clear
1349                         pTxRing->Cell[TxIdx].pNdisPacket = NULL;
1350
1351                         pPacket = pTxRing->Cell[TxIdx].pNextNdisPacket;
1352
1353                         if (pPacket)
1354                         {
1355                                 PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
1356                                 RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1357                         }
1358
1359                         // Always assign pNextNdisPacket as NULL after clear
1360                         pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
1361
1362 #ifdef RT_BIG_ENDIAN
1363                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1364                         WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
1365 #endif
1366
1367                         if (ATESetUpFrame(pAd, TxIdx) != 0)
1368                                 break;
1369
1370                         INC_RING_INDEX(pTxRing->TxCpuIdx, TX_RING_SIZE);
1371
1372                 }
1373
1374                 ATESetUpFrame(pAd, pTxRing->TxCpuIdx);
1375
1376                 // Start Tx, Rx DMA.
1377                 RtmpDmaEnable(pAd, 1);
1378
1379                 // Enable Tx
1380                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1381                 Value |= (1 << 2);
1382                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1383
1384 #ifdef RALINK_28xx_QA
1385                 // add this for LoopBack mode
1386                 if (pAd->ate.bQARxStart == FALSE)
1387                 {
1388                         // Disable Rx
1389                         RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1390                         Value &= ~(1 << 3);
1391                         RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1392                 }
1393
1394                 if (pAd->ate.bQATxStart == TRUE)
1395                 {
1396                         pAd->ate.TxStatus = 1;
1397                 }
1398 #else
1399                 // Disable Rx
1400                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1401                 Value &= ~(1 << 3);
1402                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1403 #endif // RALINK_28xx_QA //
1404
1405                 RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QID_AC_BE * RINGREG_DIFF, &pAd->TxRing[QID_AC_BE].TxDmaIdx);
1406                 // kick Tx-Ring.
1407                 RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QID_AC_BE * RINGREG_DIFF, pAd->TxRing[QID_AC_BE].TxCpuIdx);
1408
1409                 pAd->RalinkCounters.KickTxCount++;
1410         }
1411 #ifdef RALINK_28xx_QA
1412         else if (!strcmp(arg, "TXSTOP"))
1413         {
1414                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXSTOP\n"));
1415                 atemode = pAd->ate.Mode;
1416                 pAd->ate.Mode &= ATE_TXSTOP;
1417                 pAd->ate.bQATxStart = FALSE;
1418 //              pAd->ate.TxDoneCount = pAd->ate.TxCount;
1419
1420                 if (atemode == ATE_TXCARR)
1421                 {
1422                         // No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0
1423                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1424                         BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
1425                     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1426                 }
1427                 else if (atemode == ATE_TXCARRSUPP)
1428                 {
1429                         // No Cont. TX set BBP R22 bit7=0
1430                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1431                         BbpData &= ~(1 << 7); //set bit7=0
1432                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1433
1434                         // No Carrier Suppression set BBP R24 bit0=0
1435                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &BbpData);
1436                         BbpData &= 0xFFFFFFFE; //clear bit0
1437                     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, BbpData);
1438                 }
1439
1440                 /*
1441                         We should free some resource which was allocated
1442                         when ATE_TXFRAME, ATE_STOP, and ATE_TXCONT.
1443                 */
1444                 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
1445                 {
1446                         PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
1447
1448                         if (atemode == ATE_TXCONT)
1449                         {
1450                                 // No Cont. TX set BBP R22 bit7=0
1451                                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1452                                 BbpData &= ~(1 << 7); //set bit7=0
1453                                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1454                         }
1455
1456                         // Abort Tx, Rx DMA.
1457                         RtmpDmaEnable(pAd, 0);
1458
1459                         for (i=0; i<TX_RING_SIZE; i++)
1460                         {
1461                                 PNDIS_PACKET  pPacket;
1462
1463 #ifndef RT_BIG_ENDIAN
1464                             pTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
1465 #else
1466                         pDestTxD = (PTXD_STRUC)pAd->TxRing[QID_AC_BE].Cell[i].AllocVa;
1467                         TxD = *pDestTxD;
1468                         pTxD = &TxD;
1469                         RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1470 #endif
1471                                 pTxD->DMADONE = 0;
1472                                 pPacket = pTxRing->Cell[i].pNdisPacket;
1473
1474                                 if (pPacket)
1475                                 {
1476                                         PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
1477                                         RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1478                                 }
1479
1480                                 // Always assign pNdisPacket as NULL after clear
1481                                 pTxRing->Cell[i].pNdisPacket = NULL;
1482
1483                                 pPacket = pTxRing->Cell[i].pNextNdisPacket;
1484
1485                                 if (pPacket)
1486                                 {
1487                                         PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
1488                                         RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
1489                                 }
1490
1491                                 // Always assign pNextNdisPacket as NULL after clear
1492                                 pTxRing->Cell[i].pNextNdisPacket = NULL;
1493 #ifdef RT_BIG_ENDIAN
1494                                 RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
1495                                 WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
1496 #endif
1497                         }
1498                         // Enable Tx, Rx DMA
1499                         RtmpDmaEnable(pAd, 1);
1500
1501                 }
1502
1503                 // TxStatus : 0 --> task is idle, 1 --> task is running
1504                 pAd->ate.TxStatus = 0;
1505
1506                 // Soft reset BBP.
1507                 BbpSoftReset(pAd);
1508
1509                 // Disable Tx
1510                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1511                 Value &= ~(1 << 2);
1512                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1513         }
1514         else if (!strcmp(arg, "RXSTOP"))
1515         {
1516                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: RXSTOP\n"));
1517                 atemode = pAd->ate.Mode;
1518                 pAd->ate.Mode &= ATE_RXSTOP;
1519                 pAd->ate.bQARxStart = FALSE;
1520 //              pAd->ate.TxDoneCount = pAd->ate.TxCount;
1521
1522                 if (atemode == ATE_TXCARR)
1523                 {
1524                         ;
1525                 }
1526                 else if (atemode == ATE_TXCARRSUPP)
1527                 {
1528                         ;
1529                 }
1530
1531                 /*
1532                         We should free some resource which was allocated
1533                         when ATE_TXFRAME, ATE_STOP, and ATE_TXCONT.
1534                 */
1535                 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
1536                 {
1537                         if (atemode == ATE_TXCONT)
1538                         {
1539                                 ;
1540                         }
1541                 }
1542
1543                 // Soft reset BBP.
1544                 BbpSoftReset(pAd);
1545
1546                 // Disable Rx
1547                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1548                 Value &= ~(1 << 3);
1549                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1550         }
1551 #endif // RALINK_28xx_QA //
1552         else if (!strcmp(arg, "RXFRAME"))
1553         {
1554                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: RXFRAME\n"));
1555
1556                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1557                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1558
1559                 pAd->ate.Mode |= ATE_RXFRAME;
1560
1561                 // Disable Tx of MAC block.
1562                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1563                 Value &= ~(1 << 2);
1564                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1565
1566                 // Enable Rx of MAC block.
1567                 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1568                 Value |= (1 << 3);
1569                 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1570         }
1571         else
1572         {
1573                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: Invalid arg!\n"));
1574                 return FALSE;
1575         }
1576         RTMPusecDelay(5000);
1577
1578         ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== ATECmdHandler()\n"));
1579
1580         return TRUE;
1581 }
1582 /*=======================End of RTMP_MAC_PCI =======================*/
1583 #endif // RTMP_MAC_PCI //
1584
1585
1586
1587
1588 INT     Set_ATE_Proc(
1589         IN      PRTMP_ADAPTER   pAd,
1590         IN      PSTRING                 arg)
1591 {
1592         if (ATECmdHandler(pAd, arg))
1593         {
1594                 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Proc Success\n"));
1595
1596
1597                 return TRUE;
1598         }
1599         else
1600         {
1601                 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Proc Failed\n"));
1602                 return FALSE;
1603         }
1604 }
1605
1606
1607 /*
1608 ==========================================================================
1609     Description:
1610         Set ATE ADDR1=DA for TxFrame(AP  : To DS = 0 ; From DS = 1)
1611         or
1612         Set ATE ADDR3=DA for TxFrame(STA : To DS = 1 ; From DS = 0)
1613
1614     Return:
1615         TRUE if all parameters are OK, FALSE otherwise
1616 ==========================================================================
1617 */
1618 INT     Set_ATE_DA_Proc(
1619         IN      PRTMP_ADAPTER   pAd,
1620         IN      PSTRING                 arg)
1621 {
1622         PSTRING                         value;
1623         INT                                     i;
1624
1625         // Mac address acceptable format 01:02:03:04:05:06 length 17
1626         if (strlen(arg) != 17)
1627                 return FALSE;
1628
1629     for (i = 0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1630         {
1631                 /* sanity check */
1632                 if ((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))))
1633                 {
1634                         return FALSE;
1635                 }
1636
1637 #ifdef CONFIG_STA_SUPPORT
1638                 AtoH(value, &pAd->ate.Addr3[i++], 1);
1639 #endif // CONFIG_STA_SUPPORT //
1640         }
1641
1642         /* sanity check */
1643         if (i != 6)
1644         {
1645                 return FALSE;
1646         }
1647
1648 #ifdef CONFIG_STA_SUPPORT
1649         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_DA_Proc (DA = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr3[0],
1650                 pAd->ate.Addr3[1], pAd->ate.Addr3[2], pAd->ate.Addr3[3], pAd->ate.Addr3[4], pAd->ate.Addr3[5]));
1651 #endif // CONFIG_STA_SUPPORT //
1652
1653         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_DA_Proc Success\n"));
1654
1655         return TRUE;
1656 }
1657
1658
1659 /*
1660 ==========================================================================
1661     Description:
1662         Set ATE ADDR3=SA for TxFrame(AP  : To DS = 0 ; From DS = 1)
1663         or
1664         Set ATE ADDR2=SA for TxFrame(STA : To DS = 1 ; From DS = 0)
1665
1666     Return:
1667         TRUE if all parameters are OK, FALSE otherwise
1668 ==========================================================================
1669 */
1670 INT     Set_ATE_SA_Proc(
1671         IN      PRTMP_ADAPTER   pAd,
1672         IN      PSTRING                 arg)
1673 {
1674         PSTRING                         value;
1675         INT                                     i;
1676
1677         // Mac address acceptable format 01:02:03:04:05:06 length 17
1678         if (strlen(arg) != 17)
1679                 return FALSE;
1680
1681     for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1682         {
1683                 /* sanity check */
1684                 if ((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))))
1685                 {
1686                         return FALSE;
1687                 }
1688
1689 #ifdef CONFIG_STA_SUPPORT
1690                 AtoH(value, &pAd->ate.Addr2[i++], 1);
1691 #endif // CONFIG_STA_SUPPORT //
1692         }
1693
1694         /* sanity check */
1695         if (i != 6)
1696         {
1697                 return FALSE;
1698         }
1699
1700 #ifdef CONFIG_STA_SUPPORT
1701         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_SA_Proc (SA = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr2[0],
1702                 pAd->ate.Addr2[1], pAd->ate.Addr2[2], pAd->ate.Addr2[3], pAd->ate.Addr2[4], pAd->ate.Addr2[5]));
1703 #endif // CONFIG_STA_SUPPORT //
1704
1705         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_SA_Proc Success\n"));
1706
1707         return TRUE;
1708 }
1709
1710
1711 /*
1712 ==========================================================================
1713     Description:
1714         Set ATE ADDR2=BSSID for TxFrame(AP  : To DS = 0 ; From DS = 1)
1715         or
1716         Set ATE ADDR1=BSSID for TxFrame(STA : To DS = 1 ; From DS = 0)
1717
1718     Return:
1719         TRUE if all parameters are OK, FALSE otherwise
1720 ==========================================================================
1721 */
1722 INT     Set_ATE_BSSID_Proc(
1723         IN      PRTMP_ADAPTER   pAd,
1724         IN      PSTRING                 arg)
1725 {
1726         PSTRING                         value;
1727         INT                                     i;
1728
1729         // Mac address acceptable format 01:02:03:04:05:06 length 17
1730         if (strlen(arg) != 17)
1731                 return FALSE;
1732
1733     for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1734         {
1735                 /* sanity check */
1736                 if ((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))))
1737                 {
1738                         return FALSE;
1739                 }
1740
1741 #ifdef CONFIG_STA_SUPPORT
1742                 AtoH(value, &pAd->ate.Addr1[i++], 1);
1743 #endif // CONFIG_STA_SUPPORT //
1744         }
1745
1746         /* sanity check */
1747         if(i != 6)
1748         {
1749                 return FALSE;
1750         }
1751
1752 #ifdef CONFIG_STA_SUPPORT
1753         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_BSSID_Proc (BSSID = %2X:%2X:%2X:%2X:%2X:%2X)\n",  pAd->ate.Addr1[0],
1754                 pAd->ate.Addr1[1], pAd->ate.Addr1[2], pAd->ate.Addr1[3], pAd->ate.Addr1[4], pAd->ate.Addr1[5]));
1755 #endif // CONFIG_STA_SUPPORT //
1756
1757         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_BSSID_Proc Success\n"));
1758
1759         return TRUE;
1760 }
1761
1762
1763 /*
1764 ==========================================================================
1765     Description:
1766         Set ATE Tx Channel
1767
1768     Return:
1769         TRUE if all parameters are OK, FALSE otherwise
1770 ==========================================================================
1771 */
1772 INT     Set_ATE_CHANNEL_Proc(
1773         IN      PRTMP_ADAPTER   pAd,
1774         IN      PSTRING                 arg)
1775 {
1776         UCHAR channel;
1777
1778         channel = simple_strtol(arg, 0, 10);
1779
1780         // to allow A band channel : ((channel < 1) || (channel > 14))
1781         if ((channel < 1) || (channel > 216))
1782         {
1783                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_CHANNEL_Proc::Out of range, it should be in range of 1~14.\n"));
1784                 return FALSE;
1785         }
1786         pAd->ate.Channel = channel;
1787
1788         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_CHANNEL_Proc (ATE Channel = %d)\n", pAd->ate.Channel));
1789         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_CHANNEL_Proc Success\n"));
1790
1791
1792         return TRUE;
1793 }
1794
1795
1796 /*
1797 ==========================================================================
1798     Description:
1799         Set ATE Tx Power0
1800
1801     Return:
1802         TRUE if all parameters are OK, FALSE otherwise
1803 ==========================================================================
1804 */
1805 INT     Set_ATE_TX_POWER0_Proc(
1806         IN      PRTMP_ADAPTER   pAd,
1807         IN      PSTRING                 arg)
1808 {
1809         CHAR TxPower;
1810
1811         TxPower = simple_strtol(arg, 0, 10);
1812
1813         if (pAd->ate.Channel <= 14)
1814         {
1815                 if ((TxPower > 31) || (TxPower < 0))
1816                 {
1817                         ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER0_Proc::Out of range (Value=%d)\n", TxPower));
1818                         return FALSE;
1819                 }
1820         }
1821         else/* 5.5 GHz */
1822         {
1823                 if ((TxPower > 15) || (TxPower < -7))
1824                 {
1825                         ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER0_Proc::Out of range (Value=%d)\n", TxPower));
1826                         return FALSE;
1827                 }
1828         }
1829
1830         pAd->ate.TxPower0 = TxPower;
1831         ATETxPwrHandler(pAd, 0);
1832         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER0_Proc Success\n"));
1833
1834
1835         return TRUE;
1836 }
1837
1838
1839 /*
1840 ==========================================================================
1841     Description:
1842         Set ATE Tx Power1
1843
1844     Return:
1845         TRUE if all parameters are OK, FALSE otherwise
1846 ==========================================================================
1847 */
1848 INT     Set_ATE_TX_POWER1_Proc(
1849         IN      PRTMP_ADAPTER   pAd,
1850         IN      PSTRING                 arg)
1851 {
1852         CHAR TxPower;
1853
1854         TxPower = simple_strtol(arg, 0, 10);
1855
1856         if (pAd->ate.Channel <= 14)
1857         {
1858                 if ((TxPower > 31) || (TxPower < 0))
1859                 {
1860                         ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER1_Proc::Out of range (Value=%d)\n", TxPower));
1861                         return FALSE;
1862                 }
1863         }
1864         else
1865         {
1866                 if ((TxPower > 15) || (TxPower < -7))
1867                 {
1868                         ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER1_Proc::Out of range (Value=%d)\n", TxPower));
1869                         return FALSE;
1870                 }
1871         }
1872
1873         pAd->ate.TxPower1 = TxPower;
1874         ATETxPwrHandler(pAd, 1);
1875         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER1_Proc Success\n"));
1876
1877
1878         return TRUE;
1879 }
1880
1881
1882 /*
1883 ==========================================================================
1884     Description:
1885         Set ATE Tx Antenna
1886
1887     Return:
1888         TRUE if all parameters are OK, FALSE otherwise
1889 ==========================================================================
1890 */
1891 INT     Set_ATE_TX_Antenna_Proc(
1892         IN      PRTMP_ADAPTER   pAd,
1893         IN      PSTRING                 arg)
1894 {
1895         CHAR value;
1896
1897         value = simple_strtol(arg, 0, 10);
1898
1899         if ((value > 2) || (value < 0))
1900         {
1901                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_Antenna_Proc::Out of range (Value=%d)\n", value));
1902                 return FALSE;
1903         }
1904
1905         pAd->ate.TxAntennaSel = value;
1906
1907         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_Antenna_Proc (Antenna = %d)\n", pAd->ate.TxAntennaSel));
1908         ATEDBGPRINT(RT_DEBUG_TRACE,("Ralink: Set_ATE_TX_Antenna_Proc Success\n"));
1909
1910         // calibration power unbalance issues, merged from Arch Team
1911         ATEAsicSwitchChannel(pAd);
1912
1913
1914         return TRUE;
1915 }
1916
1917
1918 /*
1919 ==========================================================================
1920     Description:
1921         Set ATE Rx Antenna
1922
1923     Return:
1924         TRUE if all parameters are OK, FALSE otherwise
1925 ==========================================================================
1926 */
1927 INT     Set_ATE_RX_Antenna_Proc(
1928         IN      PRTMP_ADAPTER   pAd,
1929         IN      PSTRING                 arg)
1930 {
1931         CHAR value;
1932
1933         value = simple_strtol(arg, 0, 10);
1934
1935         if ((value > 3) || (value < 0))
1936         {
1937                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_RX_Antenna_Proc::Out of range (Value=%d)\n", value));
1938                 return FALSE;
1939         }
1940
1941         pAd->ate.RxAntennaSel = value;
1942
1943         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_Antenna_Proc (Antenna = %d)\n", pAd->ate.RxAntennaSel));
1944         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_Antenna_Proc Success\n"));
1945
1946         // calibration power unbalance issues, merged from Arch Team
1947         ATEAsicSwitchChannel(pAd);
1948
1949
1950         return TRUE;
1951 }
1952
1953
1954 /*
1955 ==========================================================================
1956     Description:
1957         Set ATE RF frequence offset
1958
1959     Return:
1960         TRUE if all parameters are OK, FALSE otherwise
1961 ==========================================================================
1962 */
1963 INT     Set_ATE_TX_FREQOFFSET_Proc(
1964         IN      PRTMP_ADAPTER   pAd,
1965         IN      PSTRING                 arg)
1966 {
1967         UCHAR RFFreqOffset = 0;
1968         ULONG R4 = 0;
1969
1970         RFFreqOffset = simple_strtol(arg, 0, 10);
1971 #ifndef RTMP_RF_RW_SUPPORT
1972         if (RFFreqOffset >= 64)
1973 #endif // RTMP_RF_RW_SUPPORT //
1974         /* RT35xx ATE will reuse this code segment. */
1975 #ifdef RTMP_RF_RW_SUPPORT
1976 //2008/08/06: KH modified the limit of offset value from 65 to 95(0x5F)
1977         if (RFFreqOffset >= 95)
1978 #endif // RTMP_RF_RW_SUPPORT //
1979         {
1980                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_FREQOFFSET_Proc::Out of range, it should be in range of 0~63.\n"));
1981                 return FALSE;
1982         }
1983
1984         pAd->ate.RFFreqOffset = RFFreqOffset;
1985 #ifdef RTMP_RF_RW_SUPPORT
1986         if (IS_RT30xx(pAd) || IS_RT3572(pAd))
1987         {
1988                 // Set RF offset
1989                 UCHAR RFValue;
1990                 ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R23, (PUCHAR)&RFValue);
1991 //2008/08/06: KH modified "pAd->RFFreqOffset" to "pAd->ate.RFFreqOffset"
1992                 RFValue = ((RFValue & 0x80) | pAd->ate.RFFreqOffset);
1993                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R23, (UCHAR)RFValue);
1994         }
1995         else
1996 #endif // RTMP_RF_RW_SUPPORT //
1997         {
1998                 // RT28xx
1999                 // shift TX power control to correct RF register bit position
2000                 R4 = pAd->ate.RFFreqOffset << 15;
2001                 R4 |= (pAd->LatchRfRegs.R4 & ((~0x001f8000)));
2002                 pAd->LatchRfRegs.R4 = R4;
2003
2004                 RtmpRfIoWrite(pAd);
2005         }
2006         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_FREQOFFSET_Proc (RFFreqOffset = %d)\n", pAd->ate.RFFreqOffset));
2007         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_FREQOFFSET_Proc Success\n"));
2008
2009
2010         return TRUE;
2011 }
2012
2013
2014 /*
2015 ==========================================================================
2016     Description:
2017         Set ATE RF BW
2018
2019     Return:
2020         TRUE if all parameters are OK, FALSE otherwise
2021 ==========================================================================
2022 */
2023 INT     Set_ATE_TX_BW_Proc(
2024         IN      PRTMP_ADAPTER   pAd,
2025         IN      PSTRING                 arg)
2026 {
2027         INT i;
2028         UCHAR value = 0;
2029         UCHAR BBPCurrentBW;
2030
2031         BBPCurrentBW = simple_strtol(arg, 0, 10);
2032
2033         if ((BBPCurrentBW == 0)
2034 #ifdef RT30xx
2035                 || IS_RT2070(pAd)
2036 #endif // RT30xx //
2037                 )
2038         {
2039                 pAd->ate.TxWI.BW = BW_20;
2040         }
2041         else
2042         {
2043                 pAd->ate.TxWI.BW = BW_40;
2044         }
2045
2046         /* RT35xx ATE will reuse this code segment. */
2047         // Fix the error spectrum of CCK-40MHZ
2048         // Turn on BBP 20MHz mode by request here.
2049         if ((pAd->ate.TxWI.PHYMODE == MODE_CCK) && (pAd->ate.TxWI.BW == BW_40))
2050         {
2051                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_BW_Proc!! Warning!! CCK only supports 20MHZ!!\nBandwidth switch to 20\n"));
2052                 pAd->ate.TxWI.BW = BW_20;
2053         }
2054
2055         if (pAd->ate.TxWI.BW == BW_20)
2056         {
2057                 if (pAd->ate.Channel <= 14)
2058                 {
2059                         for (i=0; i<5; i++)
2060                         {
2061                                 if (pAd->Tx20MPwrCfgGBand[i] != 0xffffffff)
2062                                 {
2063                                         RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx20MPwrCfgGBand[i]);
2064                                         RTMPusecDelay(5000);
2065                                 }
2066                         }
2067                 }
2068                 else
2069                 {
2070                         for (i=0; i<5; i++)
2071                         {
2072                                 if (pAd->Tx20MPwrCfgABand[i] != 0xffffffff)
2073                                 {
2074                                         RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx20MPwrCfgABand[i]);
2075                                         RTMPusecDelay(5000);
2076                                 }
2077                         }
2078                 }
2079
2080                 // Set BBP R4 bit[4:3]=0:0
2081                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
2082                 value &= (~0x18);
2083                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
2084
2085
2086                 // Set BBP R66=0x3C
2087                 value = 0x3C;
2088                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
2089
2090                 // Set BBP R68=0x0B
2091                 // to improve Rx sensitivity.
2092                 value = 0x0B;
2093                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
2094                 // Set BBP R69=0x16
2095                 value = 0x16;
2096                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
2097                 // Set BBP R70=0x08
2098                 value = 0x08;
2099                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
2100                 // Set BBP R73=0x11
2101                 value = 0x11;
2102                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
2103
2104             /*
2105                         If Channel=14, Bandwidth=20M and Mode=CCK, Set BBP R4 bit5=1
2106                         (to set Japan filter coefficients).
2107                         This segment of code will only works when ATETXMODE and ATECHANNEL
2108                         were set to MODE_CCK and 14 respectively before ATETXBW is set to 0.
2109             */
2110                 if (pAd->ate.Channel == 14)
2111                 {
2112                         INT TxMode = pAd->ate.TxWI.PHYMODE;
2113
2114                         if (TxMode == MODE_CCK)
2115                         {
2116                                 // when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1
2117                                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
2118                                 value |= 0x20; //set bit5=1
2119                                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
2120                         }
2121                 }
2122
2123 #ifdef RT30xx
2124                 // set BW = 20 MHz
2125                 if (IS_RT30xx(pAd))
2126                         ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR) pAd->Mlme.CaliBW20RfR24);
2127                 else
2128 #endif // RT30xx //
2129                 // set BW = 20 MHz
2130                 {
2131                         pAd->LatchRfRegs.R4 &= ~0x00200000;
2132                         RtmpRfIoWrite(pAd);
2133                 }
2134
2135         }
2136         // If bandwidth = 40M, set RF Reg4 bit 21 = 0.
2137         else if (pAd->ate.TxWI.BW == BW_40)
2138         {
2139                 if (pAd->ate.Channel <= 14)
2140                 {
2141                         for (i=0; i<5; i++)
2142                         {
2143                                 if (pAd->Tx40MPwrCfgGBand[i] != 0xffffffff)
2144                                 {
2145                                         RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx40MPwrCfgGBand[i]);
2146                                         RTMPusecDelay(5000);
2147                                 }
2148                         }
2149                 }
2150                 else
2151                 {
2152                         for (i=0; i<5; i++)
2153                         {
2154                                 if (pAd->Tx40MPwrCfgABand[i] != 0xffffffff)
2155                                 {
2156                                         RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx40MPwrCfgABand[i]);
2157                                         RTMPusecDelay(5000);
2158                                 }
2159                         }
2160 #ifdef DOT11_N_SUPPORT
2161                         if ((pAd->ate.TxWI.PHYMODE >= MODE_HTMIX) && (pAd->ate.TxWI.MCS == 7))
2162                         {
2163                         value = 0x28;
2164                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value);
2165                         }
2166 #endif // DOT11_N_SUPPORT //
2167                 }
2168
2169                 // Set BBP R4 bit[4:3]=1:0
2170                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
2171                 value &= (~0x18);
2172                 value |= 0x10;
2173                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
2174
2175
2176                 // Set BBP R66=0x3C
2177                 value = 0x3C;
2178                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
2179
2180                 // Set BBP R68=0x0C
2181                 // to improve Rx sensitivity
2182                 value = 0x0C;
2183                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
2184                 // Set BBP R69=0x1A
2185                 value = 0x1A;
2186                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
2187                 // Set BBP R70=0x0A
2188                 value = 0x0A;
2189                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
2190                 // Set BBP R73=0x16
2191                 value = 0x16;
2192                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
2193
2194                 // If bandwidth = 40M, set RF Reg4 bit 21 = 1.
2195 #ifdef RT30xx
2196                 // set BW = 40 MHz
2197                 if(IS_RT30xx(pAd))
2198                         ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR) pAd->Mlme.CaliBW40RfR24);
2199                 else
2200 #endif // RT30xx //
2201                 // set BW = 40 MHz
2202                 {
2203                 pAd->LatchRfRegs.R4 |= 0x00200000;
2204                 RtmpRfIoWrite(pAd);
2205                 }
2206         }
2207
2208         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_BW_Proc (BBPCurrentBW = %d)\n", pAd->ate.TxWI.BW));
2209         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_BW_Proc Success\n"));
2210
2211
2212         return TRUE;
2213 }
2214
2215
2216 /*
2217 ==========================================================================
2218     Description:
2219         Set ATE Tx frame length
2220
2221     Return:
2222         TRUE if all parameters are OK, FALSE otherwise
2223 ==========================================================================
2224 */
2225 INT     Set_ATE_TX_LENGTH_Proc(
2226         IN      PRTMP_ADAPTER   pAd,
2227         IN      PSTRING                 arg)
2228 {
2229         pAd->ate.TxLength = simple_strtol(arg, 0, 10);
2230
2231         if ((pAd->ate.TxLength < 24) || (pAd->ate.TxLength > (MAX_FRAME_SIZE - 34/* == 2312 */)))
2232         {
2233                 pAd->ate.TxLength = (MAX_FRAME_SIZE - 34/* == 2312 */);
2234                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_LENGTH_Proc::Out of range, it should be in range of 24~%d.\n", (MAX_FRAME_SIZE - 34/* == 2312 */)));
2235                 return FALSE;
2236         }
2237
2238         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_LENGTH_Proc (TxLength = %d)\n", pAd->ate.TxLength));
2239         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_LENGTH_Proc Success\n"));
2240
2241
2242         return TRUE;
2243 }
2244
2245
2246 /*
2247 ==========================================================================
2248     Description:
2249         Set ATE Tx frame count
2250
2251     Return:
2252         TRUE if all parameters are OK, FALSE otherwise
2253 ==========================================================================
2254 */
2255 INT     Set_ATE_TX_COUNT_Proc(
2256         IN      PRTMP_ADAPTER   pAd,
2257         IN      PSTRING                 arg)
2258 {
2259         pAd->ate.TxCount = simple_strtol(arg, 0, 10);
2260
2261         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_COUNT_Proc (TxCount = %d)\n", pAd->ate.TxCount));
2262         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_COUNT_Proc Success\n"));
2263
2264
2265         return TRUE;
2266 }
2267
2268
2269 /*
2270 ==========================================================================
2271     Description:
2272         Set ATE Tx frame MCS
2273
2274         Return:
2275                 TRUE if all parameters are OK, FALSE otherwise
2276 ==========================================================================
2277 */
2278 INT     Set_ATE_TX_MCS_Proc(
2279         IN      PRTMP_ADAPTER   pAd,
2280         IN      PSTRING                 arg)
2281 {
2282         UCHAR MCS;
2283         INT result;
2284
2285         MCS = simple_strtol(arg, 0, 10);
2286 #ifndef RT30xx
2287         result = CheckMCSValid(pAd->ate.TxWI.PHYMODE, MCS);
2288 #endif // RT30xx //
2289
2290         /* RT35xx ATE will reuse this code segment. */
2291 #ifdef RT30xx
2292         result = CheckMCSValid(pAd->ate.TxWI.PHYMODE, MCS, IS_RT2070(pAd));
2293 #endif // RT30xx //
2294
2295
2296         if (result != -1)
2297         {
2298                 pAd->ate.TxWI.MCS = (UCHAR)MCS;
2299         }
2300         else
2301         {
2302                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MCS_Proc::Out of range, refer to rate table.\n"));
2303                 return FALSE;
2304         }
2305
2306         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MCS_Proc (MCS = %d)\n", pAd->ate.TxWI.MCS));
2307         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MCS_Proc Success\n"));
2308
2309
2310         return TRUE;
2311 }
2312
2313
2314 /*
2315 ==========================================================================
2316     Description:
2317         Set ATE Tx frame Mode
2318         0: MODE_CCK
2319         1: MODE_OFDM
2320         2: MODE_HTMIX
2321         3: MODE_HTGREENFIELD
2322
2323         Return:
2324                 TRUE if all parameters are OK, FALSE otherwise
2325 ==========================================================================
2326 */
2327 INT     Set_ATE_TX_MODE_Proc(
2328         IN      PRTMP_ADAPTER   pAd,
2329         IN      PSTRING                 arg)
2330 {
2331         UCHAR BbpData = 0;
2332
2333         pAd->ate.TxWI.PHYMODE = simple_strtol(arg, 0, 10);
2334
2335         if (pAd->ate.TxWI.PHYMODE > 3)
2336         {
2337                 pAd->ate.TxWI.PHYMODE = 0;
2338                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MODE_Proc::Out of range.\nIt should be in range of 0~3\n"));
2339                 ATEDBGPRINT(RT_DEBUG_ERROR, ("0: CCK, 1: OFDM, 2: HT_MIX, 3: HT_GREEN_FIELD.\n"));
2340                 return FALSE;
2341         }
2342
2343         // Turn on BBP 20MHz mode by request here.
2344         if (pAd->ate.TxWI.PHYMODE == MODE_CCK)
2345         {
2346                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BbpData);
2347                 BbpData &= (~0x18);
2348                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData);
2349                 pAd->ate.TxWI.BW = BW_20;
2350                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MODE_Proc::CCK Only support 20MHZ. Switch to 20MHZ.\n"));
2351         }
2352
2353         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MODE_Proc (TxMode = %d)\n", pAd->ate.TxWI.PHYMODE));
2354         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MODE_Proc Success\n"));
2355
2356
2357         return TRUE;
2358 }
2359
2360
2361 /*
2362 ==========================================================================
2363     Description:
2364         Set ATE Tx frame GI
2365
2366         Return:
2367                 TRUE if all parameters are OK, FALSE otherwise
2368 ==========================================================================
2369 */
2370 INT     Set_ATE_TX_GI_Proc(
2371         IN      PRTMP_ADAPTER   pAd,
2372         IN      PSTRING                 arg)
2373 {
2374         pAd->ate.TxWI.ShortGI = simple_strtol(arg, 0, 10);
2375
2376         if (pAd->ate.TxWI.ShortGI > 1)
2377         {
2378                 pAd->ate.TxWI.ShortGI = 0;
2379                 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_GI_Proc::Out of range\n"));
2380                 return FALSE;
2381         }
2382
2383         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_GI_Proc (GI = %d)\n", pAd->ate.TxWI.ShortGI));
2384         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_GI_Proc Success\n"));
2385
2386
2387         return TRUE;
2388 }
2389
2390
2391 INT     Set_ATE_RX_FER_Proc(
2392         IN      PRTMP_ADAPTER   pAd,
2393         IN      PSTRING                 arg)
2394 {
2395         pAd->ate.bRxFER = simple_strtol(arg, 0, 10);
2396
2397         if (pAd->ate.bRxFER == 1)
2398         {
2399                 pAd->ate.RxCntPerSec = 0;
2400                 pAd->ate.RxTotalCnt = 0;
2401         }
2402
2403         ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_FER_Proc (bRxFER = %d)\n", pAd->ate.bRxFER));
2404         ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_FER_Proc Success\n"));
2405
2406
2407         return TRUE;
2408 }
2409
2410
2411 INT Set_ATE_Read_RF_Proc(
2412         IN      PRTMP_ADAPTER   pAd,
2413         IN      PSTRING                 arg)
2414 {
2415 #ifdef RTMP_RF_RW_SUPPORT
2416 //2008/07/10:KH add to support RT30xx ATE<--
2417         if (IS_RT30xx(pAd) || IS_RT3572(pAd))
2418         {
2419                 /* modify by WY for Read RF Reg. error */
2420                 UCHAR RFValue;
2421                 INT index=0;
2422
2423                 for (index = 0; index < 32; index++)
2424                 {
2425                         ATE_RF_IO_READ8_BY_REG_ID(pAd, index, (PUCHAR)&RFValue);
2426                         ate_print("R%d=%d\n",index,RFValue);
2427                 }
2428         }
2429         else
2430 //2008/07/10:KH add to support RT30xx ATE-->
2431 #endif // RTMP_RF_RW_SUPPORT //
2432         {
2433                 ate_print(KERN_EMERG "R1 = %lx\n", pAd->LatchRfRegs.R1);
2434                 ate_print(KERN_EMERG "R2 = %lx\n", pAd->LatchRfRegs.R2);
2435                 ate_print(KERN_EMERG "R3 = %lx\n", pAd->LatchRfRegs.R3);
2436                 ate_print(KERN_EMERG "R4 = %lx\n", pAd->LatchRfRegs.R4);
2437         }
2438         return TRUE;
2439 }
2440
2441
2442 INT Set_ATE_Write_RF1_Proc(
2443         IN      PRTMP_ADAPTER   pAd,
2444         IN      PSTRING                 arg)
2445 {
2446         UINT32 value = (UINT32) simple_strtol(arg, 0, 16);
2447
2448 #ifdef RTMP_RF_RW_SUPPORT
2449 //2008/07/10:KH add to support 3070 ATE<--
2450         if (IS_RT30xx(pAd) || IS_RT3572(pAd))
2451         {
2452                 ate_print("Warning!! RT3xxx Don't Support !\n");
2453                 return FALSE;
2454
2455         }
2456         else
2457 //2008/07/10:KH add to support 3070 ATE-->
2458 #endif // RTMP_RF_RW_SUPPORT //
2459         {
2460                 pAd->LatchRfRegs.R1 = value;
2461                 RtmpRfIoWrite(pAd);
2462         }
2463         return TRUE;
2464 }
2465
2466
2467 INT Set_ATE_Write_RF2_Proc(
2468         IN      PRTMP_ADAPTER   pAd,
2469         IN      PSTRING                 arg)
2470 {
2471         UINT32 value = (UINT32) simple_strtol(arg, 0, 16);
2472
2473 #ifdef RTMP_RF_RW_SUPPORT
2474 //2008/07/10:KH add to support 3070 ATE<--
2475         if (IS_RT30xx(pAd) || IS_RT3572(pAd))
2476         {
2477                 ate_print("Warning!! RT3xxx Don't Support !\n");
2478                 return FALSE;
2479
2480         }
2481         else
2482 //2008/07/10:KH add to support 3070 ATE-->
2483 #endif // RTMP_RF_RW_SUPPORT //
2484         {
2485                 pAd->LatchRfRegs.R2 = value;
2486                 RtmpRfIoWrite(pAd);
2487         }
2488         return TRUE;
2489 }
2490
2491
2492 INT Set_ATE_Write_RF3_Proc(
2493         IN      PRTMP_ADAPTER   pAd,
2494         IN      PSTRING                 arg)
2495 {
2496         UINT32 value = simple_strtol(arg, 0, 16);
2497
2498 #ifdef RTMP_RF_RW_SUPPORT
2499 //2008/07/10:KH add to support 3070 ATE<--
2500         if (IS_RT30xx(pAd) || IS_RT3572(pAd))
2501         {
2502                 ate_print("Warning!! RT3xxx Don't Support !\n");
2503                 return FALSE;
2504
2505         }
2506         else
2507 //2008/07/10:KH add to support 3070 ATE-->
2508 #endif // RTMP_RF_RW_SUPPORT //
2509         {
2510                 pAd->LatchRfRegs.R3 = value;
2511                 RtmpRfIoWrite(pAd);
2512         }
2513         return TRUE;
2514 }
2515
2516
2517 INT Set_ATE_Write_RF4_Proc(
2518         IN      PRTMP_ADAPTER   pAd,
2519         IN      PSTRING                 arg)
2520 {
2521         UINT32 value = (UINT32) simple_strtol(arg, 0, 16);
2522
2523 #ifdef RTMP_RF_RW_SUPPORT
2524 //2008/07/10:KH add to support 3070 ATE<--
2525         if (IS_RT30xx(pAd) || IS_RT3572(pAd))
2526         {
2527                 ate_print("Warning!! RT3xxx Don't Support !\n");
2528                 return FALSE;
2529
2530         }
2531         else
2532 //2008/07/10:KH add to support 3070 ATE-->
2533 #endif // RTMP_RF_RW_SUPPORT //
2534         {
2535                 pAd->LatchRfRegs.R4 = value;
2536                 RtmpRfIoWrite(pAd);
2537         }
2538         return TRUE;
2539 }
2540
2541
2542 /*
2543 ==========================================================================
2544     Description:
2545         Load and Write EEPROM from a binary file prepared in advance.
2546
2547         Return:
2548                 TRUE if all parameters are OK, FALSE otherwise
2549 ==========================================================================
2550 */
2551 #if defined(LINUX) || defined(VXWORKS)
2552 INT Set_ATE_Load_E2P_Proc(
2553         IN      PRTMP_ADAPTER   pAd,
2554         IN      PSTRING                 arg)
2555 {
2556         BOOLEAN                 ret = FALSE;
2557         PSTRING                 src = EEPROM_BIN_FILE_NAME;
2558         RTMP_OS_FD              srcf;
2559         INT32                   retval;
2560         USHORT                  WriteEEPROM[(EEPROM_SIZE/2)];
2561         INT                             FileLength = 0;
2562         UINT32                  value = (UINT32) simple_strtol(arg, 0, 10);
2563         RTMP_OS_FS_INFO osFSInfo;
2564
2565         ATEDBGPRINT(RT_DEBUG_ERROR, ("===> %s (value=%d)\n\n", __FUNCTION__, value));
2566
2567         if (value > 0)
2568         {
2569                 /* zero the e2p buffer */
2570                 NdisZeroMemory((PUCHAR)WriteEEPROM, EEPROM_SIZE);
2571
2572                 RtmpOSFSInfoChange(&osFSInfo, TRUE);
2573
2574                 do
2575                 {
2576                         /* open the bin file */
2577                         srcf = RtmpOSFileOpen(src, O_RDONLY, 0);
2578
2579                         if (IS_FILE_OPEN_ERR(srcf))
2580                         {
2581                                 ate_print("%s - Error opening file %s\n", __FUNCTION__, src);
2582                                 break;
2583                         }
2584
2585                         /* read the firmware from the file *.bin */
2586                         FileLength = RtmpOSFileRead(srcf, (PSTRING)WriteEEPROM, EEPROM_SIZE);
2587
2588                         if (FileLength != EEPROM_SIZE)
2589                         {
2590                                 ate_print("%s: error file length (=%d) in e2p.bin\n",
2591                                            __FUNCTION__, FileLength);
2592                                 break;
2593                         }
2594                         else
2595                         {
2596                                 /* write the content of .bin file to EEPROM */
2597                                 rt_ee_write_all(pAd, WriteEEPROM);
2598                                 ret = TRUE;
2599                         }
2600                         break;
2601                 } while(TRUE);
2602
2603                 /* close firmware file */
2604                 if (IS_FILE_OPEN_ERR(srcf))
2605                 {
2606                                 ;
2607                 }
2608                 else
2609                 {
2610                         retval = RtmpOSFileClose(srcf);
2611
2612                         if (retval)
2613                         {
2614                                 ATEDBGPRINT(RT_DEBUG_ERROR, ("--> Error %d closing %s\n", -retval, src));
2615
2616                         }
2617                 }
2618
2619                 /* restore */
2620                 RtmpOSFSInfoChange(&osFSInfo, FALSE);
2621         }
2622
2623     ATEDBGPRINT(RT_DEBUG_ERROR, ("<=== %s (ret=%d)\n", __FUNCTION__, ret));
2624
2625     return ret;
2626
2627 }
2628 #endif // defined(LINUX) || defined(VXWORKS) //
2629
2630
2631
2632
2633 INT Set_ATE_Read_E2P_Proc(
2634         IN      PRTMP_ADAPTER   pAd,
2635         IN      PSTRING                 arg)
2636 {
2637         USHORT buffer[EEPROM_SIZE/2];
2638         USHORT *p;
2639         int i;
2640
2641         rt_ee_read_all(pAd, (USHORT *)buffer);
2642         p = buffer;
2643         for (i = 0; i < (EEPROM_SIZE/2); i++)
2644         {
2645                 ate_print("%4.4x ", *p);
2646                 if (((i+1) % 16) == 0)
2647                         ate_print("\n");
2648                 p++;
2649         }
2650         return TRUE;
2651 }
2652
2653
2654
2655
2656 INT     Set_ATE_Show_Proc(
2657         IN      PRTMP_ADAPTER   pAd,
2658         IN      PSTRING                 arg)
2659 {
2660         ate_print("Mode=%d\n", pAd->ate.Mode);
2661         ate_print("TxPower0=%d\n", pAd->ate.TxPower0);
2662         ate_print("TxPower1=%d\n", pAd->ate.TxPower1);
2663         ate_print("TxAntennaSel=%d\n", pAd->ate.TxAntennaSel);
2664         ate_print("RxAntennaSel=%d\n", pAd->ate.RxAntennaSel);
2665         ate_print("BBPCurrentBW=%d\n", pAd->ate.TxWI.BW);
2666         ate_print("GI=%d\n", pAd->ate.TxWI.ShortGI);
2667         ate_print("MCS=%d\n", pAd->ate.TxWI.MCS);
2668         ate_print("TxMode=%d\n", pAd->ate.TxWI.PHYMODE);
2669         ate_print("Addr1=%02x:%02x:%02x:%02x:%02x:%02x\n",
2670                 pAd->ate.Addr1[0], pAd->ate.Addr1[1], pAd->ate.Addr1[2], pAd->ate.Addr1[3], pAd->ate.Addr1[4], pAd->ate.Addr1[5]);
2671         ate_print("Addr2=%02x:%02x:%02x:%02x:%02x:%02x\n",
2672                 pAd->ate.Addr2[0], pAd->ate.Addr2[1], pAd->ate.Addr2[2], pAd->ate.Addr2[3], pAd->ate.Addr2[4], pAd->ate.Addr2[5]);
2673         ate_print("Addr3=%02x:%02x:%02x:%02x:%02x:%02x\n",
2674                 pAd->ate.Addr3[0], pAd->ate.Addr3[1], pAd->ate.Addr3[2], pAd->ate.Addr3[3], pAd->ate.Addr3[4], pAd->ate.Addr3[5]);
2675         ate_print("Channel=%d\n", pAd->ate.Channel);
2676         ate_print("TxLength=%d\n", pAd->ate.TxLength);
2677         ate_print("TxCount=%u\n", pAd->ate.TxCount);
2678         ate_print("RFFreqOffset=%d\n", pAd->ate.RFFreqOffset);
2679         ate_print(KERN_EMERG "Set_ATE_Show_Proc Success\n");
2680         return TRUE;
2681 }
2682
2683
2684 INT     Set_ATE_Help_Proc(
2685         IN      PRTMP_ADAPTER   pAd,
2686         IN      PSTRING                 arg)
2687 {
2688         ate_print("ATE=ATESTART, ATESTOP, TXCONT, TXCARR, TXFRAME, RXFRAME\n");
2689         ate_print("ATEDA\n");
2690         ate_print("ATESA\n");
2691         ate_print("ATEBSSID\n");
2692         ate_print("ATECHANNEL, range:0~14(unless A band !)\n");
2693         ate_print("ATETXPOW0, set power level of antenna 1.\n");
2694         ate_print("ATETXPOW1, set power level of antenna 2.\n");
2695         ate_print("ATETXANT, set TX antenna. 0:all, 1:antenna one, 2:antenna two.\n");
2696         ate_print("ATERXANT, set RX antenna.0:all, 1:antenna one, 2:antenna two, 3:antenna three.\n");
2697         ate_print("ATETXFREQOFFSET, set frequency offset, range 0~63\n");
2698         ate_print("ATETXBW, set BandWidth, 0:20MHz, 1:40MHz.\n");
2699         ate_print("ATETXLEN, set Frame length, range 24~%d\n", (MAX_FRAME_SIZE - 34/* == 2312 */));
2700         ate_print("ATETXCNT, set how many frame going to transmit.\n");
2701         ate_print("ATETXMCS, set MCS, reference to rate table.\n");
2702         ate_print("ATETXMODE, set Mode 0:CCK, 1:OFDM, 2:HT-Mix, 3:GreenField, reference to rate table.\n");
2703         ate_print("ATETXGI, set GI interval, 0:Long, 1:Short\n");
2704         ate_print("ATERXFER, 0:disable Rx Frame error rate. 1:enable Rx Frame error rate.\n");
2705         ate_print("ATERRF, show all RF registers.\n");
2706         ate_print("ATEWRF1, set RF1 register.\n");
2707         ate_print("ATEWRF2, set RF2 register.\n");
2708         ate_print("ATEWRF3, set RF3 register.\n");
2709         ate_print("ATEWRF4, set RF4 register.\n");
2710         ate_print("ATELDE2P, load EEPROM from .bin file.\n");
2711         ate_print("ATERE2P, display all EEPROM content.\n");
2712         ate_print("ATESHOW, display all parameters of ATE.\n");
2713         ate_print("ATEHELP, online help.\n");
2714
2715         return TRUE;
2716 }
2717
2718
2719
2720
2721 /*
2722 ==========================================================================
2723     Description:
2724
2725         AsicSwitchChannel() dedicated for ATE.
2726
2727 ==========================================================================
2728 */
2729 VOID ATEAsicSwitchChannel(
2730     IN PRTMP_ADAPTER pAd)
2731 {
2732         UINT32 R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0, Value = 0;
2733         CHAR TxPwer = 0, TxPwer2 = 0;
2734         UCHAR index = 0, BbpValue = 0, R66 = 0x30;
2735         RTMP_RF_REGS *RFRegTable;
2736         UCHAR Channel = 0;
2737
2738         RFRegTable = NULL;
2739
2740 #ifdef RALINK_28xx_QA
2741         // for QA mode, TX power values are passed from UI
2742         if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
2743         {
2744                 if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
2745                 {
2746                         pAd->ate.Channel = pAd->LatchRfRegs.Channel;
2747                 }
2748                 return;
2749         }
2750         else
2751 #endif // RALINK_28xx_QA //
2752         Channel = pAd->ate.Channel;
2753
2754         // select antenna for RT3090
2755         AsicAntennaSelect(pAd, Channel);
2756
2757         // fill Tx power value
2758         TxPwer = pAd->ate.TxPower0;
2759         TxPwer2 = pAd->ate.TxPower1;
2760 #ifdef RT30xx
2761 //2008/07/10:KH add to support 3070 ATE<--
2762
2763         /*
2764                 The RF programming sequence is difference between 3xxx and 2xxx.
2765                 The 3070 is 1T1R. Therefore, we don't need to set the number of Tx/Rx path
2766                 and the only job is to set the parameters of channels.
2767         */
2768         if (IS_RT30xx(pAd) && ((pAd->RfIcType == RFIC_3020) ||
2769                         (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) ||
2770                         (pAd->RfIcType == RFIC_2020)))
2771         {
2772                 /* modify by WY for Read RF Reg. error */
2773                 UCHAR RFValue = 0;
2774
2775                 for (index = 0; index < NUM_OF_3020_CHNL; index++)
2776                 {
2777                         if (Channel == FreqItems3020[index].Channel)
2778                         {
2779                                 // Programming channel parameters.
2780                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R02, FreqItems3020[index].N);
2781                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R03, FreqItems3020[index].K);
2782
2783                                 ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R06, (PUCHAR)&RFValue);
2784                                 RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
2785                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R06, (UCHAR)RFValue);
2786
2787                                 // Set Tx Power.
2788                                 ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R12, (PUCHAR)&RFValue);
2789                                 RFValue = (RFValue & 0xE0) | TxPwer;
2790                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R12, (UCHAR)RFValue);
2791
2792                                 // Set RF offset.
2793                                 ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R23, (PUCHAR)&RFValue);
2794                                 //2008/08/06: KH modified "pAd->RFFreqOffset" to "pAd->ate.RFFreqOffset"
2795                                 RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
2796                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R23, (UCHAR)RFValue);
2797
2798                                 // Set BW.
2799                                 if (pAd->ate.TxWI.BW == BW_40)
2800                                 {
2801                                         RFValue = pAd->Mlme.CaliBW40RfR24;
2802 //                                      DISABLE_11N_CHECK(pAd);
2803                                 }
2804                                 else
2805                                 {
2806                                         RFValue = pAd->Mlme.CaliBW20RfR24;
2807                                 }
2808                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)RFValue);
2809
2810                                 // Enable RF tuning
2811                                 ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R07, (PUCHAR)&RFValue);
2812                                 RFValue = RFValue | 0x1;
2813                                 ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R07, (UCHAR)RFValue);
2814
2815                                 // latch channel for future usage
2816                                 pAd->LatchRfRegs.Channel = Channel;
2817
2818                                 break;
2819                         }
2820                 }
2821
2822                 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
2823                         Channel,
2824                         pAd->RfIcType,
2825                         TxPwer,
2826                         TxPwer2,
2827                         pAd->Antenna.field.TxPath,
2828                         FreqItems3020[index].N,
2829                         FreqItems3020[index].K,
2830                         FreqItems3020[index].R));
2831         }
2832         else
2833 //2008/07/10:KH add to support 3070 ATE-->
2834 #endif // RT30xx //
2835         {
2836                 /* RT28xx */
2837                 RFRegTable = RF2850RegTable;
2838
2839                 switch (pAd->RfIcType)
2840                 {
2841                         /* But only 2850 and 2750 support 5.5GHz band... */
2842                         case RFIC_2820:
2843                         case RFIC_2850:
2844                         case RFIC_2720:
2845                         case RFIC_2750:
2846
2847                                 for (index = 0; index < NUM_OF_2850_CHNL; index++)
2848                                 {
2849                                         if (Channel == RFRegTable[index].Channel)
2850                                         {
2851                                                 R2 = RFRegTable[index].R2;
2852
2853                                                 // If TX path is 1, bit 14 = 1;
2854                                                 if (pAd->Antenna.field.TxPath == 1)
2855                                                 {
2856                                                         R2 |= 0x4000;
2857                                                 }
2858
2859                                                 if (pAd->Antenna.field.RxPath == 2)
2860                                                 {
2861                                                         switch (pAd->ate.RxAntennaSel)
2862                                                         {
2863                                                                 case 1:
2864                                                                         R2 |= 0x20040;
2865                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2866                                                                         BbpValue &= 0xE4;
2867                                                                         BbpValue |= 0x00;
2868                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2869                                                                         break;
2870                                                                 case 2:
2871                                                                         R2 |= 0x10040;
2872                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2873                                                                         BbpValue &= 0xE4;
2874                                                                         BbpValue |= 0x01;
2875                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2876                                                                         break;
2877                                                                 default:
2878                                                                         R2 |= 0x40;
2879                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2880                                                                         BbpValue &= 0xE4;
2881                                                                         /* Only enable two Antenna to receive. */
2882                                                                         BbpValue |= 0x08;
2883                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2884                                                                         break;
2885                                                         }
2886                                                 }
2887                                                 else if (pAd->Antenna.field.RxPath == 1)
2888                                                 {
2889                                                         // write 1 to off RxPath
2890                                                         R2 |= 0x20040;
2891                                                 }
2892
2893                                                 if (pAd->Antenna.field.TxPath == 2)
2894                                                 {
2895                                                         if (pAd->ate.TxAntennaSel == 1)
2896                                                         {
2897                                                                 // If TX Antenna select is 1 , bit 14 = 1; Disable Ant 2
2898                                                                 R2 |= 0x4000;
2899                                                                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2900                                                                 BbpValue &= 0xE7;               // 11100111B
2901                                                                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2902                                                         }
2903                                                         else if (pAd->ate.TxAntennaSel == 2)
2904                                                         {
2905                                                                 // If TX Antenna select is 2 , bit 15 = 1; Disable Ant 1
2906                                                                 R2 |= 0x8000;
2907                                                                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2908                                                                 BbpValue &= 0xE7;
2909                                                                 BbpValue |= 0x08;
2910                                                                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2911                                                         }
2912                                                         else
2913                                                         {
2914                                                                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2915                                                                 BbpValue &= 0xE7;
2916                                                                 BbpValue |= 0x10;
2917                                                                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2918                                                         }
2919                                                 }
2920                                                 if (pAd->Antenna.field.RxPath == 3)
2921                                                 {
2922                                                         switch (pAd->ate.RxAntennaSel)
2923                                                         {
2924                                                                 case 1:
2925                                                                         R2 |= 0x20040;
2926                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2927                                                                         BbpValue &= 0xE4;
2928                                                                         BbpValue |= 0x00;
2929                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2930                                                                         break;
2931                                                                 case 2:
2932                                                                         R2 |= 0x10040;
2933                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2934                                                                         BbpValue &= 0xE4;
2935                                                                         BbpValue |= 0x01;
2936                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2937                                                                         break;
2938                                                                 case 3:
2939                                                                         R2 |= 0x30000;
2940                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2941                                                                         BbpValue &= 0xE4;
2942                                                                         BbpValue |= 0x02;
2943                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2944                                                                         break;
2945                                                                 default:
2946                                                                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2947                                                                         BbpValue &= 0xE4;
2948                                                                         BbpValue |= 0x10;
2949                                                                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2950                                                                         break;
2951                                                         }
2952                                                 }
2953
2954                                                 if (Channel > 14)
2955                                                 {
2956                                                         // initialize R3, R4
2957                                                         R3 = (RFRegTable[index].R3 & 0xffffc1ff);
2958                                                         R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->ate.RFFreqOffset << 15);
2959
2960                                     /*
2961                                             According the Rory's suggestion to solve the middle range issue.
2962
2963                                                                 5.5G band power range : 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0"
2964                                                                                                                 means the TX power reduce 7dB.
2965                                                         */
2966                                                         // R3
2967                                                         if ((TxPwer >= -7) && (TxPwer < 0))
2968                                                         {
2969                                                                 TxPwer = (7+TxPwer);
2970                                                                 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
2971                                                                 R3 |= (TxPwer << 10);
2972                                                                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer=%d \n", TxPwer));
2973                                                         }
2974                                                         else
2975                                                         {
2976                                                                 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
2977                                                                 R3 |= (TxPwer << 10) | (1 << 9);
2978                                                         }
2979
2980                                                         // R4
2981                                                         if ((TxPwer2 >= -7) && (TxPwer2 < 0))
2982                                                         {
2983                                                                 TxPwer2 = (7+TxPwer2);
2984                                                                 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
2985                                                                 R4 |= (TxPwer2 << 7);
2986                                                                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
2987                                                         }
2988                                                         else
2989                                                         {
2990                                                                 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
2991                                                                 R4 |= (TxPwer2 << 7) | (1 << 6);
2992                                                         }
2993                                                 }
2994                                                 else
2995                                                 {
2996                                                         // Set TX power0.
2997                                                         R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9);
2998                                                         // Set frequency offset and TX power1.
2999                                                         R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->ate.RFFreqOffset << 15) | (TxPwer2 <<6);
3000                                                 }
3001
3002                                                 // based on BBP current mode before changing RF channel
3003                                                 if (pAd->ate.TxWI.BW == BW_40)
3004                                                 {
3005                                                         R4 |=0x200000;
3006                                                 }
3007
3008                                                 // Update variables.
3009                                                 pAd->LatchRfRegs.Channel = Channel;
3010                                                 pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
3011                                                 pAd->LatchRfRegs.R2 = R2;
3012                                                 pAd->LatchRfRegs.R3 = R3;
3013                                                 pAd->LatchRfRegs.R4 = R4;
3014
3015                                                 RtmpRfIoWrite(pAd);
3016
3017                                                 break;
3018                                         }
3019                                 }
3020                                 break;
3021
3022                         default:
3023                                 break;
3024                 }
3025         }
3026
3027         // Change BBP setting during switch from a->g, g->a
3028         if (Channel <= 14)
3029         {
3030             UINT32 TxPinCfg = 0x00050F0A;// 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A
3031
3032                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
3033                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
3034                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
3035
3036                 /* For 1T/2R chip only... */
3037             if (pAd->NicConfig2.field.ExternalLNAForG)
3038             {
3039                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
3040             }
3041             else
3042             {
3043                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
3044             }
3045
3046         // According the Rory's suggestion to solve the middle range issue.
3047                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R86, &BbpValue);// may be removed for RT35xx ++
3048
3049                 ASSERT((BbpValue == 0x00));
3050                 if ((BbpValue != 0x00))
3051                 {
3052                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x00);
3053                 }// may be removed for RT35xx --
3054
3055                 // 5.5 GHz band selection PIN, bit1 and bit2 are complement
3056                 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
3057                 Value &= (~0x6);
3058                 Value |= (0x04);
3059                 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
3060
3061         // Turn off unused PA or LNA when only 1T or 1R.
3062                 if (pAd->Antenna.field.TxPath == 1)
3063                 {
3064                         TxPinCfg &= 0xFFFFFFF3;
3065                 }
3066                 if (pAd->Antenna.field.RxPath == 1)
3067                 {
3068                         TxPinCfg &= 0xFFFFF3FF;
3069                 }
3070
3071                 // calibration power unbalance issues
3072                 if (pAd->Antenna.field.TxPath == 2)
3073                 {
3074                         if (pAd->ate.TxAntennaSel == 1)
3075                         {
3076                                 TxPinCfg &= 0xFFFFFFF7;
3077                         }
3078                         else if (pAd->ate.TxAntennaSel == 2)
3079                         {
3080                                 TxPinCfg &= 0xFFFFFFFD;
3081                         }
3082                 }
3083
3084                 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
3085         }
3086         else
3087         {
3088             UINT32      TxPinCfg = 0x00050F05;// 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05
3089
3090                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
3091                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
3092                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
3093                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
3094
3095         // According the Rory's suggestion to solve the middle range issue.
3096                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R86, &BbpValue);// may be removed for RT35xx ++
3097
3098                 ASSERT((BbpValue == 0x00));
3099                 if ((BbpValue != 0x00))
3100                 {
3101                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x00);
3102                 }
3103
3104                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
3105                 ASSERT((BbpValue == 0x04));
3106
3107                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R92, &BbpValue);
3108                 ASSERT((BbpValue == 0x00));// may be removed for RT35xx --
3109
3110                 // 5.5 GHz band selection PIN, bit1 and bit2 are complement
3111                 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
3112                 Value &= (~0x6);
3113                 Value |= (0x02);
3114                 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
3115
3116                 // Turn off unused PA or LNA when only 1T or 1R.
3117                 if (pAd->Antenna.field.TxPath == 1)
3118                 {
3119                         TxPinCfg &= 0xFFFFFFF3;
3120                 }
3121                 if (pAd->Antenna.field.RxPath == 1)
3122                 {
3123                         TxPinCfg &= 0xFFFFF3FF;
3124                 }
3125
3126                 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
3127         }
3128
3129
3130     // R66 should be set according to Channel and use 20MHz when scanning
3131         if (Channel <= 14)
3132         {
3133                 // BG band
3134                 R66 = 0x2E + GET_LNA_GAIN(pAd);
3135                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
3136         }
3137         else
3138         {
3139                 // 5.5 GHz band
3140                 if (pAd->ate.TxWI.BW == BW_20)
3141                 {
3142                         R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3);
3143                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
3144                 }
3145                 else
3146                 {
3147                         R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3);
3148                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
3149                 }
3150         }
3151
3152         /*
3153                 On 11A, We should delay and wait RF/BBP to be stable
3154                 and the appropriate time should be 1000 micro seconds.
3155
3156                 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
3157         */
3158         RTMPusecDelay(1000);
3159
3160 #ifndef RTMP_RF_RW_SUPPORT
3161         if (Channel > 14)
3162         {
3163                 // When 5.5GHz band the LSB of TxPwr will be used to reduced 7dB or not.
3164                 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
3165                                                                   Channel,
3166                                                                   pAd->RfIcType,
3167                                                                   pAd->Antenna.field.TxPath,
3168                                                                   pAd->LatchRfRegs.R1,
3169                                                                   pAd->LatchRfRegs.R2,
3170                                                                   pAd->LatchRfRegs.R3,
3171                                                                   pAd->LatchRfRegs.R4));
3172         }
3173         else
3174         {
3175                 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
3176                                                                   Channel,
3177                                                                   pAd->RfIcType,
3178                                                                   (R3 & 0x00003e00) >> 9,
3179                                                                   (R4 & 0x000007c0) >> 6,
3180                                                                   pAd->Antenna.field.TxPath,
3181                                                                   pAd->LatchRfRegs.R1,
3182                                                                   pAd->LatchRfRegs.R2,
3183                                                                   pAd->LatchRfRegs.R3,
3184                                                                   pAd->LatchRfRegs.R4));
3185     }
3186 #endif // RTMP_RF_RW_SUPPORT //
3187 }
3188
3189
3190
3191 /* In fact, no one will call this routine so far ! */
3192
3193 /*
3194 ==========================================================================
3195         Description:
3196                 Gives CCK TX rate 2 more dB TX power.
3197                 This routine works only in ATE mode.
3198
3199                 calculate desired Tx power in RF R3.Tx0~5,      should consider -
3200                 0. if current radio is a noisy environment (pAd->DrsCounters.fNoisyEnvironment)
3201                 1. TxPowerPercentage
3202                 2. auto calibration based on TSSI feedback
3203                 3. extra 2 db for CCK
3204                 4. -10 db upon very-short distance (AvgRSSI >= -40db) to AP
3205
3206         NOTE: Since this routine requires the value of (pAd->DrsCounters.fNoisyEnvironment),
3207                 it should be called AFTER MlmeDynamicTxRateSwitching()
3208 ==========================================================================
3209 */
3210 VOID ATEAsicAdjustTxPower(
3211         IN PRTMP_ADAPTER pAd)
3212 {
3213         INT                     i, j;
3214         CHAR            DeltaPwr = 0;
3215         BOOLEAN         bAutoTxAgc = FALSE;
3216         UCHAR           TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep;
3217         UCHAR           BbpR49 = 0, idx;
3218         PCHAR           pTxAgcCompensate;
3219         ULONG           TxPwr[5];
3220         CHAR            Value;
3221
3222         /* no one calls this procedure so far */
3223         if (pAd->ate.TxWI.BW == BW_40)
3224         {
3225                 if (pAd->ate.Channel > 14)
3226                 {
3227                         TxPwr[0] = pAd->Tx40MPwrCfgABand[0];
3228                         TxPwr[1] = pAd->Tx40MPwrCfgABand[1];
3229                         TxPwr[2] = pAd->Tx40MPwrCfgABand[2];
3230                         TxPwr[3] = pAd->Tx40MPwrCfgABand[3];
3231                         TxPwr[4] = pAd->Tx40MPwrCfgABand[4];
3232                 }
3233                 else
3234                 {
3235                         TxPwr[0] = pAd->Tx40MPwrCfgGBand[0];
3236                         TxPwr[1] = pAd->Tx40MPwrCfgGBand[1];
3237                         TxPwr[2] = pAd->Tx40MPwrCfgGBand[2];
3238                         TxPwr[3] = pAd->Tx40MPwrCfgGBand[3];
3239                         TxPwr[4] = pAd->Tx40MPwrCfgGBand[4];
3240                 }
3241         }
3242         else
3243         {
3244                 if (pAd->ate.Channel > 14)
3245                 {
3246                         TxPwr[0] = pAd->Tx20MPwrCfgABand[0];
3247                         TxPwr[1] = pAd->Tx20MPwrCfgABand[1];
3248                         TxPwr[2] = pAd->Tx20MPwrCfgABand[2];
3249                         TxPwr[3] = pAd->Tx20MPwrCfgABand[3];
3250                         TxPwr[4] = pAd->Tx20MPwrCfgABand[4];
3251                 }
3252                 else
3253                 {
3254                         TxPwr[0] = pAd->Tx20MPwrCfgGBand[0];
3255                         TxPwr[1] = pAd->Tx20MPwrCfgGBand[1];
3256                         TxPwr[2] = pAd->Tx20MPwrCfgGBand[2];
3257                         TxPwr[3] = pAd->Tx20MPwrCfgGBand[3];
3258                         TxPwr[4] = pAd->Tx20MPwrCfgGBand[4];
3259                 }
3260         }
3261
3262         // TX power compensation for temperature variation based on TSSI.
3263         // Do it per 4 seconds.
3264         if (pAd->Mlme.OneSecPeriodicRound % 4 == 0)
3265         {
3266                 if (pAd->ate.Channel <= 14)
3267                 {
3268                         /* bg channel */
3269                         bAutoTxAgc         = pAd->bAutoTxAgcG;
3270                         TssiRef            = pAd->TssiRefG;
3271                         pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0];
3272                         pTssiPlusBoundary  = &pAd->TssiPlusBoundaryG[0];
3273                         TxAgcStep          = pAd->TxAgcStepG;
3274                         pTxAgcCompensate   = &pAd->TxAgcCompensateG;
3275                 }
3276                 else
3277                 {
3278                         /* a channel */
3279                         bAutoTxAgc         = pAd->bAutoTxAgcA;
3280                         TssiRef            = pAd->TssiRefA;
3281                         pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0];
3282                         pTssiPlusBoundary  = &pAd->TssiPlusBoundaryA[0];
3283                         TxAgcStep          = pAd->TxAgcStepA;
3284                         pTxAgcCompensate   = &pAd->TxAgcCompensateA;
3285                 }
3286
3287                 if (bAutoTxAgc)
3288                 {
3289                         /* BbpR49 is unsigned char. */
3290                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49);
3291
3292                         /* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */
3293                         /* compensate: +4     +3   +2   +1    0   -1   -2   -3   -4 * steps */
3294                         /* step value is defined in pAd->TxAgcStepG for tx power value */
3295
3296                         /* [4]+1+[4]   p4     p3   p2   p1   o1   m1   m2   m3   m4 */
3297                         /* ex:         0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
3298                            above value are examined in mass factory production */
3299                         /*             [4]    [3]  [2]  [1]  [0]  [1]  [2]  [3]  [4] */
3300
3301                         /* plus is 0x10 ~ 0x40, minus is 0x60 ~ 0x90 */
3302                         /* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */
3303                         /* if value is 0x65, tx power will be -= TxAgcStep*(2-1) */
3304
3305                         if (BbpR49 > pTssiMinusBoundary[1])
3306                         {
3307                                 // Reading is larger than the reference value.
3308                                 // Check for how large we need to decrease the Tx power.
3309                                 for (idx = 1; idx < 5; idx++)
3310                                 {
3311                                         // Found the range.
3312                                         if (BbpR49 <= pTssiMinusBoundary[idx])
3313                                                 break;
3314                                 }
3315
3316                                 // The index is the step we should decrease, idx = 0 means there is nothing to compensate.
3317 //                              if (R3 > (ULONG) (TxAgcStep * (idx-1)))
3318                                         *pTxAgcCompensate = -(TxAgcStep * (idx-1));
3319 //                              else
3320 //                                      *pTxAgcCompensate = -((UCHAR)R3);
3321
3322                                 DeltaPwr += (*pTxAgcCompensate);
3323                                 ATEDBGPRINT(RT_DEBUG_TRACE, ("-- Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n",
3324                                         BbpR49, TssiRef, TxAgcStep, idx-1));
3325                         }
3326                         else if (BbpR49 < pTssiPlusBoundary[1])
3327                         {
3328                                 // Reading is smaller than the reference value.
3329                                 // Check for how large we need to increase the Tx power.
3330                                 for (idx = 1; idx < 5; idx++)
3331                                 {
3332                                         // Found the range.
3333                                         if (BbpR49 >= pTssiPlusBoundary[idx])
3334                                                 break;
3335                                 }
3336
3337                                 // The index is the step we should increase, idx = 0 means there is nothing to compensate.
3338                                 *pTxAgcCompensate = TxAgcStep * (idx-1);
3339                                 DeltaPwr += (*pTxAgcCompensate);
3340                                 ATEDBGPRINT(RT_DEBUG_TRACE, ("++ Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
3341                                         BbpR49, TssiRef, TxAgcStep, idx-1));
3342                         }
3343                         else
3344                         {
3345                                 *pTxAgcCompensate = 0;
3346                                 ATEDBGPRINT(RT_DEBUG_TRACE, ("   Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
3347                                         BbpR49, TssiRef, TxAgcStep, 0));
3348                         }
3349                 }
3350         }
3351         else
3352         {
3353                 if (pAd->ate.Channel <= 14)
3354                 {
3355                         bAutoTxAgc         = pAd->bAutoTxAgcG;
3356                         pTxAgcCompensate   = &pAd->TxAgcCompensateG;
3357                 }
3358                 else
3359                 {
3360                         bAutoTxAgc         = pAd->bAutoTxAgcA;
3361                         pTxAgcCompensate   = &pAd->TxAgcCompensateA;
3362                 }
3363
3364                 if (bAutoTxAgc)
3365                         DeltaPwr += (*pTxAgcCompensate);
3366         }
3367
3368         /* Calculate delta power based on the percentage specified from UI. */
3369         // E2PROM setting is calibrated for maximum TX power (i.e. 100%)
3370         // We lower TX power here according to the percentage specified from UI.
3371         if (pAd->CommonCfg.TxPowerPercentage == 0xffffffff)       // AUTO TX POWER control
3372                 ;
3373         else if (pAd->CommonCfg.TxPowerPercentage > 90)  // 91 ~ 100% & AUTO, treat as 100% in terms of mW
3374                 ;
3375         else if (pAd->CommonCfg.TxPowerPercentage > 60)  // 61 ~ 90%, treat as 75% in terms of mW
3376         {
3377                 DeltaPwr -= 1;
3378         }
3379         else if (pAd->CommonCfg.TxPowerPercentage > 30)  // 31 ~ 60%, treat as 50% in terms of mW
3380         {
3381                 DeltaPwr -= 3;
3382         }
3383         else if (pAd->CommonCfg.TxPowerPercentage > 15)  // 16 ~ 30%, treat as 25% in terms of mW
3384         {
3385                 DeltaPwr -= 6;
3386         }
3387         else if (pAd->CommonCfg.TxPowerPercentage > 9)   // 10 ~ 15%, treat as 12.5% in terms of mW
3388         {
3389                 DeltaPwr -= 9;
3390         }
3391         else                                           // 0 ~ 9 %, treat as MIN(~3%) in terms of mW
3392         {
3393                 DeltaPwr -= 12;
3394         }
3395
3396         /* Reset different new tx power for different TX rate. */
3397         for (i=0; i<5; i++)
3398         {
3399                 if (TxPwr[i] != 0xffffffff)
3400                 {
3401                         for (j=0; j<8; j++)
3402                         {
3403                                 Value = (CHAR)((TxPwr[i] >> j*4) & 0x0F); /* 0 ~ 15 */
3404
3405                                 if ((Value + DeltaPwr) < 0)
3406                                 {
3407                                         Value = 0; /* min */
3408                                 }
3409                                 else if ((Value + DeltaPwr) > 0xF)
3410                                 {
3411                                         Value = 0xF; /* max */
3412                                 }
3413                                 else
3414                                 {
3415                                         Value += DeltaPwr; /* temperature compensation */
3416                                 }
3417
3418                                 /* fill new value to CSR offset */
3419                                 TxPwr[i] = (TxPwr[i] & ~(0x0000000F << j*4)) | (Value << j*4);
3420                         }
3421
3422                         /* write tx power value to CSR */
3423                         /* TX_PWR_CFG_0 (8 tx rate) for TX power for OFDM 12M/18M
3424                                                                                         TX power for OFDM 6M/9M
3425                                                                                         TX power for CCK5.5M/11M
3426                                                                                         TX power for CCK1M/2M */
3427                         /* TX_PWR_CFG_1 ~ TX_PWR_CFG_4 */
3428                         RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, TxPwr[i]);
3429
3430
3431                 }
3432         }
3433
3434 }
3435
3436
3437 /*
3438 ========================================================================
3439         Routine Description:
3440                 Write TxWI for ATE mode.
3441
3442         Return Value:
3443                 None
3444 ========================================================================
3445 */
3446 #ifdef RTMP_MAC_PCI
3447 static VOID ATEWriteTxWI(
3448         IN      PRTMP_ADAPTER   pAd,
3449         IN      PTXWI_STRUC     pOutTxWI,
3450         IN      BOOLEAN                 FRAG,
3451         IN      BOOLEAN                 CFACK,
3452         IN      BOOLEAN                 InsTimestamp,
3453         IN      BOOLEAN                 AMPDU,
3454         IN      BOOLEAN                 Ack,
3455         IN      BOOLEAN                 NSeq,           // HW new a sequence.
3456         IN      UCHAR                   BASize,
3457         IN      UCHAR                   WCID,
3458         IN      ULONG                   Length,
3459         IN      UCHAR                   PID,
3460         IN      UCHAR                   TID,
3461         IN      UCHAR                   TxRate,
3462         IN      UCHAR                   Txopmode,
3463         IN      BOOLEAN                 CfAck,
3464         IN      HTTRANSMIT_SETTING      *pTransmit)
3465 {
3466         TXWI_STRUC              TxWI;
3467         PTXWI_STRUC     pTxWI;
3468
3469         //
3470         // Always use Long preamble before verifiation short preamble functionality works well.
3471         // Todo: remove the following line if short preamble functionality works
3472         //
3473         OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
3474         NdisZeroMemory(&TxWI, TXWI_SIZE);
3475         pTxWI = &TxWI;
3476
3477         pTxWI->FRAG= FRAG;
3478
3479         pTxWI->CFACK = CFACK;
3480         pTxWI->TS= InsTimestamp;
3481         pTxWI->AMPDU = AMPDU;
3482         pTxWI->ACK = Ack;
3483         pTxWI->txop= Txopmode;
3484
3485         pTxWI->NSEQ = NSeq;
3486
3487         // John tune the performace with Intel Client in 20 MHz performance
3488         if ( BASize >7 )
3489                 BASize =7;
3490
3491         pTxWI->BAWinSize = BASize;
3492         pTxWI->WirelessCliID = WCID;
3493         pTxWI->MPDUtotalByteCount = Length;
3494         pTxWI->PacketId = PID;
3495
3496         // If CCK or OFDM, BW must be 20
3497         pTxWI->BW = (pTransmit->field.MODE <= MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
3498         pTxWI->ShortGI = pTransmit->field.ShortGI;
3499         pTxWI->STBC = pTransmit->field.STBC;
3500
3501         pTxWI->MCS = pTransmit->field.MCS;
3502         pTxWI->PHYMODE = pTransmit->field.MODE;
3503         pTxWI->CFACK = CfAck;
3504         pTxWI->MIMOps = 0;
3505         pTxWI->MpduDensity = 0;
3506
3507         pTxWI->PacketId = pTxWI->MCS;
3508         NdisMoveMemory(pOutTxWI, &TxWI, sizeof(TXWI_STRUC));
3509
3510     return;
3511 }
3512 #endif // RTMP_MAC_PCI //
3513
3514
3515
3516
3517 /*
3518 ========================================================================
3519
3520         Routine Description:
3521                 Disable protection for ATE.
3522 ========================================================================
3523 */
3524 VOID ATEDisableAsicProtect(
3525         IN              PRTMP_ADAPTER   pAd)
3526 {
3527         PROT_CFG_STRUC  ProtCfg, ProtCfg4;
3528         UINT32 Protect[6];
3529         USHORT                  offset;
3530         UCHAR                   i;
3531         UINT32 MacReg = 0;
3532
3533         // Config ASIC RTS threshold register
3534         RTMP_IO_READ32(pAd, TX_RTS_CFG, &MacReg);
3535         MacReg &= 0xFF0000FF;
3536         MacReg |= (pAd->CommonCfg.RtsThreshold << 8);
3537         RTMP_IO_WRITE32(pAd, TX_RTS_CFG, MacReg);
3538
3539         // Initial common protection settings
3540         RTMPZeroMemory(Protect, sizeof(Protect));
3541         ProtCfg4.word = 0;
3542         ProtCfg.word = 0;
3543         ProtCfg.field.TxopAllowGF40 = 1;
3544         ProtCfg.field.TxopAllowGF20 = 1;
3545         ProtCfg.field.TxopAllowMM40 = 1;
3546         ProtCfg.field.TxopAllowMM20 = 1;
3547         ProtCfg.field.TxopAllowOfdm = 1;
3548         ProtCfg.field.TxopAllowCck = 1;
3549         ProtCfg.field.RTSThEn = 1;
3550         ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
3551
3552         // Handle legacy(B/G) protection
3553         ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate;
3554         ProtCfg.field.ProtectCtrl = 0;
3555         Protect[0] = ProtCfg.word;
3556         Protect[1] = ProtCfg.word;
3557
3558         // NO PROTECT
3559         // 1.All STAs in the BSS are 20/40 MHz HT
3560         // 2. in ai 20/40MHz BSS
3561         // 3. all STAs are 20MHz in a 20MHz BSS
3562         // Pure HT. no protection.
3563
3564         // MM20_PROT_CFG
3565         //      Reserved (31:27)
3566         //      PROT_TXOP(25:20) -- 010111
3567         //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
3568         //  PROT_CTRL(17:16) -- 00 (None)
3569         //      PROT_RATE(15:0)  -- 0x4004 (OFDM 24M)
3570         Protect[2] = 0x01744004;
3571
3572         // MM40_PROT_CFG
3573         //      Reserved (31:27)
3574         //      PROT_TXOP(25:20) -- 111111
3575         //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
3576         //  PROT_CTRL(17:16) -- 00 (None)
3577         //      PROT_RATE(15:0)  -- 0x4084 (duplicate OFDM 24M)
3578         Protect[3] = 0x03f44084;
3579
3580         // CF20_PROT_CFG
3581         //      Reserved (31:27)
3582         //      PROT_TXOP(25:20) -- 010111
3583         //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
3584         //  PROT_CTRL(17:16) -- 00 (None)
3585         //      PROT_RATE(15:0)  -- 0x4004 (OFDM 24M)
3586         Protect[4] = 0x01744004;
3587
3588         // CF40_PROT_CFG
3589         //      Reserved (31:27)
3590         //      PROT_TXOP(25:20) -- 111111
3591         //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
3592         //  PROT_CTRL(17:16) -- 00 (None)
3593         //      PROT_RATE(15:0)  -- 0x4084 (duplicate OFDM 24M)
3594         Protect[5] = 0x03f44084;
3595
3596         pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
3597
3598         offset = CCK_PROT_CFG;
3599         for (i = 0;i < 6;i++)
3600                 RTMP_IO_WRITE32(pAd, offset + i*4, Protect[i]);
3601
3602 }
3603
3604
3605
3606
3607 /* There are two ways to convert Rssi */
3608 /* the way used with GET_LNA_GAIN() */
3609 CHAR ATEConvertToRssi(
3610         IN PRTMP_ADAPTER pAd,
3611         IN      CHAR    Rssi,
3612         IN  UCHAR   RssiNumber)
3613 {
3614         UCHAR   RssiOffset, LNAGain;
3615
3616         // Rssi equals to zero should be an invalid value
3617         if (Rssi == 0)
3618                 return -99;
3619
3620         LNAGain = GET_LNA_GAIN(pAd);
3621         if (pAd->LatchRfRegs.Channel > 14)
3622         {
3623                 if (RssiNumber == 0)
3624                         RssiOffset = pAd->ARssiOffset0;
3625                 else if (RssiNumber == 1)
3626                         RssiOffset = pAd->ARssiOffset1;
3627                 else
3628                         RssiOffset = pAd->ARssiOffset2;
3629         }
3630         else
3631         {
3632                 if (RssiNumber == 0)
3633                         RssiOffset = pAd->BGRssiOffset0;
3634                 else if (RssiNumber == 1)
3635                         RssiOffset = pAd->BGRssiOffset1;
3636                 else
3637                         RssiOffset = pAd->BGRssiOffset2;
3638         }
3639
3640         return (-12 - RssiOffset - LNAGain - Rssi);
3641 }
3642
3643
3644 /*
3645 ========================================================================
3646
3647         Routine Description:
3648                 Set Japan filter coefficients if needed.
3649         Note:
3650                 This routine should only be called when
3651                 entering TXFRAME mode or TXCONT mode.
3652
3653 ========================================================================
3654 */
3655 static VOID SetJapanFilter(
3656         IN              PRTMP_ADAPTER   pAd)
3657 {
3658         UCHAR                   BbpData = 0;
3659
3660         //
3661         // If Channel=14 and Bandwidth=20M and Mode=CCK, set BBP R4 bit5=1
3662         // (Japan Tx filter coefficients)when (TXFRAME or TXCONT).
3663         //
3664         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BbpData);
3665
3666     if ((pAd->ate.TxWI.PHYMODE == MODE_CCK) && (pAd->ate.Channel == 14) && (pAd->ate.TxWI.BW == BW_20))
3667     {
3668         BbpData |= 0x20;    // turn on
3669         ATEDBGPRINT(RT_DEBUG_TRACE, ("SetJapanFilter!!!\n"));
3670     }
3671     else
3672     {
3673                 BbpData &= 0xdf;    // turn off
3674                 ATEDBGPRINT(RT_DEBUG_TRACE, ("ClearJapanFilter!!!\n"));
3675     }
3676
3677         ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData);
3678 }
3679
3680
3681 VOID ATESampleRssi(
3682         IN PRTMP_ADAPTER        pAd,
3683         IN PRXWI_STRUC          pRxWI)
3684 {
3685         /* There are two ways to collect RSSI. */
3686 //      pAd->LastRxRate = (USHORT)((pRxWI->MCS) + (pRxWI->BW <<7) + (pRxWI->ShortGI <<8)+ (pRxWI->PHYMODE <<14)) ;
3687         if (pRxWI->RSSI0 != 0)
3688         {
3689                 pAd->ate.LastRssi0      = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI0, RSSI_0);
3690                 pAd->ate.AvgRssi0X8     = (pAd->ate.AvgRssi0X8 - pAd->ate.AvgRssi0) + pAd->ate.LastRssi0;
3691                 pAd->ate.AvgRssi0       = pAd->ate.AvgRssi0X8 >> 3;
3692         }
3693         if (pRxWI->RSSI1 != 0)
3694         {
3695                 pAd->ate.LastRssi1      = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI1, RSSI_1);
3696                 pAd->ate.AvgRssi1X8     = (pAd->ate.AvgRssi1X8 - pAd->ate.AvgRssi1) + pAd->ate.LastRssi1;
3697                 pAd->ate.AvgRssi1       = pAd->ate.AvgRssi1X8 >> 3;
3698         }
3699         if (pRxWI->RSSI2 != 0)
3700         {
3701                 pAd->ate.LastRssi2      = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI2, RSSI_2);
3702                 pAd->ate.AvgRssi2X8     = (pAd->ate.AvgRssi2X8 - pAd->ate.AvgRssi2) + pAd->ate.LastRssi2;
3703                 pAd->ate.AvgRssi2       = pAd->ate.AvgRssi2X8 >> 3;
3704         }
3705
3706         pAd->ate.LastSNR0 = (CHAR)(pRxWI->SNR0);// CHAR ==> UCHAR ?
3707         pAd->ate.LastSNR1 = (CHAR)(pRxWI->SNR1);// CHAR ==> UCHAR ?
3708
3709         pAd->ate.NumOfAvgRssiSample ++;
3710 }
3711
3712
3713 #ifdef CONFIG_STA_SUPPORT
3714 VOID RTMPStationStop(
3715     IN  PRTMP_ADAPTER   pAd)
3716 {
3717 //      BOOLEAN       Cancelled;
3718
3719     ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStop\n"));
3720
3721         // For rx statistics, we need to keep this timer running.
3722 //      RTMPCancelTimer(&pAd->Mlme.PeriodicTimer,      &Cancelled);
3723
3724     ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStop\n"));
3725 }
3726
3727
3728 VOID RTMPStationStart(
3729     IN  PRTMP_ADAPTER   pAd)
3730 {
3731     ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStart\n"));
3732
3733 #ifdef RTMP_MAC_PCI
3734         pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
3735
3736         /* We did not cancel this timer when entering ATE mode. */
3737 //      RTMPSetTimer(&pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV);
3738 #endif // RTMP_MAC_PCI //
3739
3740         ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStart\n"));
3741 }
3742 #endif // CONFIG_STA_SUPPORT //
3743
3744
3745 /*
3746 ==========================================================================
3747         Description:
3748                 Setup Frame format.
3749         NOTE:
3750                 This routine should only be used in ATE mode.
3751 ==========================================================================
3752 */
3753 #ifdef RTMP_MAC_PCI
3754 static INT ATESetUpFrame(
3755         IN PRTMP_ADAPTER pAd,
3756         IN UINT32 TxIdx)
3757 {
3758         UINT j;
3759         PTXD_STRUC pTxD;
3760 #ifdef RT_BIG_ENDIAN
3761     PTXD_STRUC      pDestTxD;
3762     TXD_STRUC       TxD;
3763 #endif
3764         PNDIS_PACKET pPacket;
3765         PUCHAR pDest;
3766         PVOID AllocVa;
3767         NDIS_PHYSICAL_ADDRESS AllocPa;
3768         HTTRANSMIT_SETTING      TxHTPhyMode;
3769
3770         PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
3771         PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
3772         PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
3773
3774 #ifdef RALINK_28xx_QA
3775         PHEADER_802_11  pHeader80211;
3776 #endif // RALINK_28xx_QA //
3777
3778         if (pAd->ate.bQATxStart == TRUE)
3779         {
3780                 // always use QID_AC_BE and FIFO_EDCA
3781
3782                 // fill TxWI
3783                 TxHTPhyMode.field.BW = pAd->ate.TxWI.BW;
3784                 TxHTPhyMode.field.ShortGI = pAd->ate.TxWI.ShortGI;
3785                 TxHTPhyMode.field.STBC = 0;
3786                 TxHTPhyMode.field.MCS = pAd->ate.TxWI.MCS;
3787                 TxHTPhyMode.field.MODE = pAd->ate.TxWI.PHYMODE;
3788
3789                 ATEWriteTxWI(pAd, pTxWI, pAd->ate.TxWI.FRAG, pAd->ate.TxWI.CFACK,
3790                         pAd->ate.TxWI.TS,  pAd->ate.TxWI.AMPDU, pAd->ate.TxWI.ACK, pAd->ate.TxWI.NSEQ,
3791                         pAd->ate.TxWI.BAWinSize, 0, pAd->ate.TxWI.MPDUtotalByteCount, pAd->ate.TxWI.PacketId, 0, 0,
3792                         pAd->ate.TxWI.txop/*IFS_HTTXOP*/, pAd->ate.TxWI.CFACK/*FALSE*/, &TxHTPhyMode);
3793         }
3794         else
3795         {
3796                 TxHTPhyMode.field.BW = pAd->ate.TxWI.BW;
3797                 TxHTPhyMode.field.ShortGI = pAd->ate.TxWI.ShortGI;
3798                 TxHTPhyMode.field.STBC = 0;
3799                 TxHTPhyMode.field.MCS = pAd->ate.TxWI.MCS;
3800                 TxHTPhyMode.field.MODE = pAd->ate.TxWI.PHYMODE;
3801                 ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE,  FALSE, FALSE, FALSE,
3802                         4, 0, pAd->ate.TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
3803         }
3804
3805         // fill 802.11 header
3806 #ifdef RALINK_28xx_QA
3807         if (pAd->ate.bQATxStart == TRUE)
3808         {
3809                 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE, pAd->ate.Header, pAd->ate.HLen);
3810         }
3811         else
3812 #endif // RALINK_28xx_QA //
3813         {
3814                 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE, TemplateFrame, LENGTH_802_11);
3815                 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE+4, pAd->ate.Addr1, ETH_LENGTH_OF_ADDRESS);
3816                 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE+10, pAd->ate.Addr2, ETH_LENGTH_OF_ADDRESS);
3817                 NdisMoveMemory(pDMAHeaderBufVA+TXWI_SIZE+16, pAd->ate.Addr3, ETH_LENGTH_OF_ADDRESS);
3818         }
3819
3820 #ifdef RT_BIG_ENDIAN
3821         RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA)+TXWI_SIZE), DIR_READ, FALSE);
3822 #endif // RT_BIG_ENDIAN //
3823
3824         /* alloc buffer for payload */
3825 #ifdef RALINK_28xx_QA
3826         if (pAd->ate.bQATxStart == TRUE)
3827         {
3828                 pPacket = RTMP_AllocateRxPacketBuffer(pAd, pAd->ate.DLen + 0x100, FALSE, &AllocVa, &AllocPa);
3829         }
3830         else
3831 #endif // RALINK_28xx_QA //
3832         {
3833                 pPacket = RTMP_AllocateRxPacketBuffer(pAd, pAd->ate.TxLength, FALSE, &AllocVa, &AllocPa);
3834         }
3835
3836         if (pPacket == NULL)
3837         {
3838                 pAd->ate.TxCount = 0;
3839                 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s fail to alloc packet space.\n", __FUNCTION__));
3840                 return -1;
3841         }
3842         pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
3843
3844         pDest = (PUCHAR) AllocVa;
3845
3846 #ifdef RALINK_28xx_QA
3847         if (pAd->ate.bQATxStart == TRUE)
3848         {
3849                 RTPKT_TO_OSPKT(pPacket)->len = pAd->ate.DLen;
3850         }
3851         else
3852 #endif // RALINK_28xx_QA //
3853         {
3854                 RTPKT_TO_OSPKT(pPacket)->len = pAd->ate.TxLength - LENGTH_802_11;
3855         }
3856
3857         // prepare frame payload
3858 #ifdef RALINK_28xx_QA
3859         if (pAd->ate.bQATxStart == TRUE)
3860         {
3861                 // copy pattern
3862                 if ((pAd->ate.PLen != 0))
3863                 {
3864                         int j;
3865
3866                         for (j = 0; j < pAd->ate.DLen; j+=pAd->ate.PLen)
3867                         {
3868                                 memcpy(RTPKT_TO_OSPKT(pPacket)->data + j, pAd->ate.Pattern, pAd->ate.PLen);
3869                         }
3870                 }
3871         }
3872         else
3873 #endif // RALINK_28xx_QA //
3874         {
3875                 for (j = 0; j < RTPKT_TO_OSPKT(pPacket)->len; j++)
3876                 {
3877                         pDest[j] = 0xA5;
3878                 }
3879         }
3880
3881         /* build Tx Descriptor */
3882 #ifndef RT_BIG_ENDIAN
3883         pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
3884 #else
3885     pDestTxD  = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
3886     TxD = *pDestTxD;
3887     pTxD = &TxD;
3888 #endif // !RT_BIG_ENDIAN //
3889
3890 #ifdef RALINK_28xx_QA
3891         if (pAd->ate.bQATxStart == TRUE)
3892         {
3893                 // prepare TxD
3894                 NdisZeroMemory(pTxD, TXD_SIZE);
3895                 RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
3896                 // build TX DESC
3897                 pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
3898                 pTxD->SDLen0 = TXWI_SIZE + pAd->ate.HLen;
3899                 pTxD->LastSec0 = 0;
3900                 pTxD->SDPtr1 = AllocPa;
3901                 pTxD->SDLen1 = RTPKT_TO_OSPKT(pPacket)->len;
3902                 pTxD->LastSec1 = 1;
3903
3904                 pDest = (PUCHAR)pTxWI;
3905                 pDest += TXWI_SIZE;
3906                 pHeader80211 = (PHEADER_802_11)pDest;
3907
3908                 // modify sequence number...
3909                 if (pAd->ate.TxDoneCount == 0)
3910                 {
3911                         pAd->ate.seq = pHeader80211->Sequence;
3912                 }
3913                 else
3914                         pHeader80211->Sequence = ++pAd->ate.seq;
3915         }
3916         else
3917 #endif // RALINK_28xx_QA //
3918         {
3919                 NdisZeroMemory(pTxD, TXD_SIZE);
3920                 RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
3921                 // build TX DESC
3922                 pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
3923                 pTxD->SDLen0 = TXWI_SIZE + LENGTH_802_11;
3924                 pTxD->LastSec0 = 0;
3925                 pTxD->SDPtr1 = AllocPa;
3926                 pTxD->SDLen1 = RTPKT_TO_OSPKT(pPacket)->len;
3927                 pTxD->LastSec1 = 1;
3928         }
3929
3930 #ifdef RT_BIG_ENDIAN
3931         RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI);
3932         RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA)+TXWI_SIZE), DIR_WRITE, FALSE);
3933     RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
3934     WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
3935 #endif // RT_BIG_ENDIAN //
3936
3937         return 0;
3938 }
3939 /*=======================End of RTMP_MAC_PCI =======================*/
3940 #endif // RTMP_MAC_PCI //
3941
3942
3943
3944
3945 VOID rt_ee_read_all(PRTMP_ADAPTER pAd, USHORT *Data)
3946 {
3947         USHORT i;
3948         USHORT value;
3949
3950
3951         for (i = 0 ; i < EEPROM_SIZE/2 ; )
3952         {
3953                 /* "value" is especially for some compilers... */
3954                 RT28xx_EEPROM_READ16(pAd, i*2, value);
3955                 Data[i] = value;
3956                 i++;
3957         }
3958 }
3959
3960
3961 VOID rt_ee_write_all(PRTMP_ADAPTER pAd, USHORT *Data)
3962 {
3963         USHORT i;
3964         USHORT value;
3965
3966
3967         for (i = 0 ; i < EEPROM_SIZE/2 ; )
3968         {
3969                 /* "value" is especially for some compilers... */
3970                 value = Data[i];
3971                 RT28xx_EEPROM_WRITE16(pAd, i*2, value);
3972                 i++;
3973         }
3974 }
3975
3976
3977 #ifdef RALINK_28xx_QA
3978 VOID ATE_QA_Statistics(
3979         IN PRTMP_ADAPTER                        pAd,
3980         IN PRXWI_STRUC                          pRxWI,
3981         IN PRT28XX_RXD_STRUC            pRxD,
3982         IN PHEADER_802_11                       pHeader)
3983 {
3984         // update counter first
3985         if (pHeader != NULL)
3986         {
3987                 if (pHeader->FC.Type == BTYPE_DATA)
3988                 {
3989                         if (pRxD->U2M)
3990                                 pAd->ate.U2M++;
3991                         else
3992                                 pAd->ate.OtherData++;
3993                 }
3994                 else if (pHeader->FC.Type == BTYPE_MGMT)
3995                 {
3996                         if (pHeader->FC.SubType == SUBTYPE_BEACON)
3997                                 pAd->ate.Beacon++;
3998                         else
3999                                 pAd->ate.OtherCount++;
4000                 }
4001                 else if (pHeader->FC.Type == BTYPE_CNTL)
4002                 {
4003                         pAd->ate.OtherCount++;
4004                 }
4005         }
4006         pAd->ate.RSSI0 = pRxWI->RSSI0;
4007         pAd->ate.RSSI1 = pRxWI->RSSI1;
4008         pAd->ate.RSSI2 = pRxWI->RSSI2;
4009         pAd->ate.SNR0 = pRxWI->SNR0;
4010         pAd->ate.SNR1 = pRxWI->SNR1;
4011 }
4012
4013
4014 /* command id with Cmd Type == 0x0008(for 28xx)/0x0005(for iNIC) */
4015 #define RACFG_CMD_RF_WRITE_ALL          0x0000
4016 #define RACFG_CMD_E2PROM_READ16         0x0001
4017 #define RACFG_CMD_E2PROM_WRITE16        0x0002
4018 #define RACFG_CMD_E2PROM_READ_ALL       0x0003
4019 #define RACFG_CMD_E2PROM_WRITE_ALL      0x0004
4020 #define RACFG_CMD_IO_READ                       0x0005
4021 #define RACFG_CMD_IO_WRITE                      0x0006
4022 #define RACFG_CMD_IO_READ_BULK          0x0007
4023 #define RACFG_CMD_BBP_READ8                     0x0008
4024 #define RACFG_CMD_BBP_WRITE8            0x0009
4025 #define RACFG_CMD_BBP_READ_ALL          0x000a
4026 #define RACFG_CMD_GET_COUNTER           0x000b
4027 #define RACFG_CMD_CLEAR_COUNTER         0x000c
4028
4029 #define RACFG_CMD_RSV1                          0x000d
4030 #define RACFG_CMD_RSV2                          0x000e
4031 #define RACFG_CMD_RSV3                          0x000f
4032
4033 #define RACFG_CMD_TX_START                      0x0010
4034 #define RACFG_CMD_GET_TX_STATUS         0x0011
4035 #define RACFG_CMD_TX_STOP                       0x0012
4036 #define RACFG_CMD_RX_START                      0x0013
4037 #define RACFG_CMD_RX_STOP                       0x0014
4038 #define RACFG_CMD_GET_NOISE_LEVEL       0x0015
4039
4040 #define RACFG_CMD_ATE_START                     0x0080
4041 #define RACFG_CMD_ATE_STOP                      0x0081
4042
4043 #define RACFG_CMD_ATE_START_TX_CARRIER          0x0100
4044 #define RACFG_CMD_ATE_START_TX_CONT                     0x0101
4045 #define RACFG_CMD_ATE_START_TX_FRAME            0x0102
4046 #define RACFG_CMD_ATE_SET_BW                0x0103
4047 #define RACFG_CMD_ATE_SET_TX_POWER0             0x0104
4048 #define RACFG_CMD_ATE_SET_TX_POWER1                     0x0105
4049 #define RACFG_CMD_ATE_SET_FREQ_OFFSET           0x0106
4050 #define RACFG_CMD_ATE_GET_STATISTICS            0x0107
4051 #define RACFG_CMD_ATE_RESET_COUNTER                     0x0108
4052 #define RACFG_CMD_ATE_SEL_TX_ANTENNA            0x0109
4053 #define RACFG_CMD_ATE_SEL_RX_ANTENNA            0x010a
4054 #define RACFG_CMD_ATE_SET_PREAMBLE                      0x010b
4055 #define RACFG_CMD_ATE_SET_CHANNEL                       0x010c
4056 #define RACFG_CMD_ATE_SET_ADDR1                         0x010d
4057 #define RACFG_CMD_ATE_SET_ADDR2                         0x010e
4058 #define RACFG_CMD_ATE_SET_ADDR3                         0x010f
4059 #define RACFG_CMD_ATE_SET_RATE                          0x0110
4060 #define RACFG_CMD_ATE_SET_TX_FRAME_LEN          0x0111
4061 #define RACFG_CMD_ATE_SET_TX_FRAME_COUNT        0x0112
4062 #define RACFG_CMD_ATE_START_RX_FRAME            0x0113
4063 #define RACFG_CMD_ATE_E2PROM_READ_BULK  0x0114
4064 #define RACFG_CMD_ATE_E2PROM_WRITE_BULK 0x0115
4065 #define RACFG_CMD_ATE_IO_WRITE_BULK             0x0116
4066 #define RACFG_CMD_ATE_BBP_READ_BULK             0x0117
4067 #define RACFG_CMD_ATE_BBP_WRITE_BULK    0x0118
4068 #define RACFG_CMD_ATE_RF_READ_BULK              0x0119
4069 #define RACFG_CMD_ATE_RF_WRITE_BULK             0x011a
4070
4071
4072 static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len);
4073 static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len);
4074 static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, UINT32 len);
4075
4076
4077
4078 VOID RtmpDoAte(
4079         IN      PRTMP_ADAPTER   pAdapter,
4080         IN      struct iwreq    *wrq)
4081 {
4082         USHORT Command_Id;
4083         INT     Status = NDIS_STATUS_SUCCESS;
4084         struct ate_racfghdr *pRaCfg;
4085
4086
4087         if ((pRaCfg = kmalloc(sizeof(struct ate_racfghdr), GFP_KERNEL)) == NULL)
4088         {
4089                 Status = -EINVAL;
4090                 return;
4091         }
4092
4093         NdisZeroMemory(pRaCfg, sizeof(struct ate_racfghdr));
4094
4095     if (copy_from_user((PUCHAR)pRaCfg, wrq->u.data.pointer, wrq->u.data.length))
4096         {
4097                 Status = -EFAULT;
4098                 kfree(pRaCfg);
4099                 return;
4100         }
4101
4102         Command_Id = ntohs(pRaCfg->command_id);
4103
4104         ATEDBGPRINT(RT_DEBUG_TRACE,("\n%s: Command_Id = 0x%04x !\n", __FUNCTION__, Command_Id));
4105
4106         switch (Command_Id)
4107         {
4108                 /* We will get this command when QA starts. */
4109                 case RACFG_CMD_ATE_START:
4110                         Status=DO_RACFG_CMD_ATE_START(pAdapter,wrq,pRaCfg);
4111                         break;
4112
4113                 /* We will get this command either QA is closed or ated is killed by user. */
4114                 case RACFG_CMD_ATE_STOP:
4115                         Status=DO_RACFG_CMD_ATE_STOP(pAdapter,wrq,pRaCfg);
4116                         break;
4117
4118                 case RACFG_CMD_RF_WRITE_ALL:
4119                         Status=DO_RACFG_CMD_RF_WRITE_ALL(pAdapter,wrq,pRaCfg);
4120                         break;
4121
4122                 case RACFG_CMD_E2PROM_READ16:
4123                         Status=DO_RACFG_CMD_E2PROM_READ16(pAdapter,wrq,pRaCfg);
4124                         break;
4125
4126                 case RACFG_CMD_E2PROM_WRITE16:
4127                         Status=DO_RACFG_CMD_E2PROM_WRITE16(pAdapter,wrq,pRaCfg);
4128                         break;
4129
4130                 case RACFG_CMD_E2PROM_READ_ALL:
4131                         Status=DO_RACFG_CMD_E2PROM_READ_ALL(pAdapter,wrq,pRaCfg);
4132                         break;
4133
4134                 case RACFG_CMD_E2PROM_WRITE_ALL:
4135                         Status=DO_RACFG_CMD_E2PROM_WRITE_ALL(pAdapter,wrq,pRaCfg);
4136                         break;
4137
4138                 case RACFG_CMD_IO_READ:
4139                         Status=DO_RACFG_CMD_IO_READ(pAdapter,wrq,pRaCfg);
4140                         break;
4141
4142                 case RACFG_CMD_IO_WRITE:
4143                         Status=DO_RACFG_CMD_IO_WRITE(pAdapter,wrq,pRaCfg);
4144                         break;
4145
4146                 case RACFG_CMD_IO_READ_BULK:
4147                         Status=DO_RACFG_CMD_IO_READ_BULK(pAdapter,wrq,pRaCfg);
4148                         break;
4149
4150                 case RACFG_CMD_BBP_READ8:
4151                         Status=DO_RACFG_CMD_BBP_READ8(pAdapter,wrq,pRaCfg);
4152                         break;
4153                 case RACFG_CMD_BBP_WRITE8:
4154                         Status=DO_RACFG_CMD_BBP_WRITE8(pAdapter,wrq,pRaCfg);
4155                         break;
4156
4157                 case RACFG_CMD_BBP_READ_ALL:
4158                         Status=DO_RACFG_CMD_BBP_READ_ALL(pAdapter,wrq,pRaCfg);
4159                         break;
4160
4161                 case RACFG_CMD_ATE_E2PROM_READ_BULK:
4162                         Status=DO_RACFG_CMD_ATE_E2PROM_READ_BULK(pAdapter,wrq,pRaCfg);
4163                         break;
4164
4165                 case RACFG_CMD_ATE_E2PROM_WRITE_BULK:
4166                         Status=DO_RACFG_CMD_ATE_E2PROM_WRITE_BULK(pAdapter,wrq,pRaCfg);
4167                         break;
4168
4169                 case RACFG_CMD_ATE_IO_WRITE_BULK:
4170                         Status=DO_RACFG_CMD_ATE_IO_WRITE_BULK(pAdapter,wrq,pRaCfg);
4171                         break;
4172
4173                 case RACFG_CMD_ATE_BBP_READ_BULK:
4174                         Status=DO_RACFG_CMD_ATE_BBP_READ_BULK(pAdapter,wrq,pRaCfg);
4175                         break;
4176
4177                 case RACFG_CMD_ATE_BBP_WRITE_BULK:
4178                         Status=DO_RACFG_CMD_ATE_BBP_WRITE_BULK(pAdapter,wrq,pRaCfg);
4179                         break;
4180
4181
4182                 case RACFG_CMD_GET_NOISE_LEVEL:
4183                         Status=DO_RACFG_CMD_GET_NOISE_LEVEL(pAdapter,wrq,pRaCfg);
4184                         break;
4185
4186                 case RACFG_CMD_GET_COUNTER:
4187                         Status=DO_RACFG_CMD_GET_COUNTER(pAdapter,wrq,pRaCfg);
4188                         break;
4189
4190                 case RACFG_CMD_CLEAR_COUNTER:
4191                         Status=DO_RACFG_CMD_CLEAR_COUNTER(pAdapter,wrq,pRaCfg);
4192                         break;
4193
4194                 case RACFG_CMD_TX_START:
4195                         Status=DO_RACFG_CMD_TX_START(pAdapter,wrq,pRaCfg);
4196                         break;
4197
4198                 case RACFG_CMD_GET_TX_STATUS:
4199                         Status=DO_RACFG_CMD_GET_TX_STATUS(pAdapter,wrq,pRaCfg);
4200                         break;
4201
4202                 case RACFG_CMD_TX_STOP:
4203                         Status=DO_RACFG_CMD_TX_STOP(pAdapter,wrq,pRaCfg);
4204                         break;
4205
4206                 case RACFG_CMD_RX_START:
4207                         Status=DO_RACFG_CMD_RX_START(pAdapter,wrq,pRaCfg);
4208                         break;
4209
4210                 case RACFG_CMD_RX_STOP:
4211                         Status=DO_RACFG_CMD_RX_STOP(pAdapter,wrq,pRaCfg);
4212                         break;
4213
4214                 /* The following cases are for new ATE GUI(not QA). */
4215                 /*==================================================*/
4216                 case RACFG_CMD_ATE_START_TX_CARRIER:
4217                         Status=DO_RACFG_CMD_ATE_START_TX_CARRIER(pAdapter,wrq,pRaCfg);
4218                         break;
4219
4220                 case RACFG_CMD_ATE_START_TX_CONT:
4221                         Status=DO_RACFG_CMD_ATE_START_TX_CONT(pAdapter,wrq,pRaCfg);
4222                         break;
4223
4224                 case RACFG_CMD_ATE_START_TX_FRAME:
4225                         Status=DO_RACFG_CMD_ATE_START_TX_FRAME(pAdapter,wrq,pRaCfg);
4226                         break;
4227
4228                 case RACFG_CMD_ATE_SET_BW:
4229                         Status=DO_RACFG_CMD_ATE_SET_BW(pAdapter,wrq,pRaCfg);
4230                         break;
4231
4232                 case RACFG_CMD_ATE_SET_TX_POWER0:
4233                         Status=DO_RACFG_CMD_ATE_SET_TX_POWER0(pAdapter,wrq,pRaCfg);
4234                         break;
4235
4236                 case RACFG_CMD_ATE_SET_TX_POWER1:
4237                         Status=DO_RACFG_CMD_ATE_SET_TX_POWER1(pAdapter,wrq,pRaCfg);
4238                         break;
4239
4240                 case RACFG_CMD_ATE_SET_FREQ_OFFSET:
4241                         Status=DO_RACFG_CMD_ATE_SET_TX_POWER1(pAdapter,wrq,pRaCfg);
4242                         break;
4243
4244                 case RACFG_CMD_ATE_GET_STATISTICS:
4245                         Status=DO_RACFG_CMD_ATE_GET_STATISTICS(pAdapter,wrq,pRaCfg);
4246                         break;
4247
4248                 case RACFG_CMD_ATE_RESET_COUNTER:
4249                         Status=DO_RACFG_CMD_ATE_RESET_COUNTER(pAdapter,wrq,pRaCfg);
4250                         break;
4251
4252                 case RACFG_CMD_ATE_SEL_TX_ANTENNA:
4253                         Status=DO_RACFG_CMD_ATE_SEL_TX_ANTENNA(pAdapter,wrq,pRaCfg);
4254                         break;
4255
4256                 case RACFG_CMD_ATE_SEL_RX_ANTENNA:
4257                         Status=DO_RACFG_CMD_ATE_SEL_TX_ANTENNA(pAdapter,wrq,pRaCfg);
4258                         break;
4259
4260                 case RACFG_CMD_ATE_SET_PREAMBLE:
4261                         Status=DO_RACFG_CMD_ATE_SET_PREAMBLE(pAdapter,wrq,pRaCfg);
4262                         break;
4263
4264                 case RACFG_CMD_ATE_SET_CHANNEL:
4265                         Status=DO_RACFG_CMD_ATE_SET_CHANNEL(pAdapter,wrq,pRaCfg);
4266                         break;
4267
4268                 case RACFG_CMD_ATE_SET_ADDR1:
4269                         Status=DO_RACFG_CMD_ATE_SET_ADDR1(pAdapter,wrq,pRaCfg);
4270                         break;
4271
4272                 case RACFG_CMD_ATE_SET_ADDR2:
4273                         Status=DO_RACFG_CMD_ATE_SET_ADDR2(pAdapter,wrq,pRaCfg);
4274                         break;
4275
4276                 case RACFG_CMD_ATE_SET_ADDR3:
4277                         Status=DO_RACFG_CMD_ATE_SET_ADDR3(pAdapter,wrq,pRaCfg);
4278                         break;
4279
4280                 case RACFG_CMD_ATE_SET_RATE:
4281                         Status=DO_RACFG_CMD_ATE_SET_RATE(pAdapter,wrq,pRaCfg);
4282                         break;
4283
4284                 case RACFG_CMD_ATE_SET_TX_FRAME_LEN:
4285                         Status=DO_RACFG_CMD_ATE_SET_TX_FRAME_LEN(pAdapter,wrq,pRaCfg);
4286                         break;
4287
4288                 case RACFG_CMD_ATE_SET_TX_FRAME_COUNT:
4289                         Status=DO_RACFG_CMD_ATE_SET_TX_FRAME_COUNT(pAdapter,wrq,pRaCfg);
4290                         break;
4291
4292                 case RACFG_CMD_ATE_START_RX_FRAME:
4293                         Status=DO_RACFG_CMD_ATE_START_RX_FRAME(pAdapter,wrq,pRaCfg);
4294                         break;
4295                 default:
4296                         break;
4297         }
4298
4299     ASSERT(pRaCfg != NULL);
4300
4301     if (pRaCfg != NULL)
4302             kfree(pRaCfg);
4303
4304         return;
4305 }
4306
4307
4308 VOID BubbleSort(INT32 n, INT32 a[])
4309 {
4310         INT32 k, j, temp;
4311
4312         for (k = n-1;  k>0;  k--)
4313         {
4314                 for (j = 0; j<k; j++)
4315                 {
4316                         if (a[j] > a[j+1])
4317                         {
4318                                 temp = a[j];
4319                                 a[j]=a[j+1];
4320                                 a[j+1]=temp;
4321                         }
4322                 }
4323         }
4324 }
4325
4326
4327 VOID CalNoiseLevel(PRTMP_ADAPTER pAd, UCHAR channel, INT32 RSSI[3][10])
4328 {
4329         INT32           RSSI0, RSSI1, RSSI2;
4330         CHAR            Rssi0Offset, Rssi1Offset, Rssi2Offset;
4331         UCHAR           BbpR50Rssi0 = 0, BbpR51Rssi1 = 0, BbpR52Rssi2 = 0;
4332         UCHAR           Org_BBP66value = 0, Org_BBP69value = 0, Org_BBP70value = 0, data = 0;
4333         USHORT          LNA_Gain = 0;
4334         INT32       j = 0;
4335         UCHAR           Org_Channel = pAd->ate.Channel;
4336         USHORT      GainValue = 0, OffsetValue = 0;
4337
4338         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &Org_BBP66value);
4339         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R69, &Org_BBP69value);
4340         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R70, &Org_BBP70value);
4341
4342         //**********************************************************************
4343         // Read the value of LNA gain and Rssi offset
4344         //**********************************************************************
4345         RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, GainValue);
4346
4347         // for Noise Level
4348         if (channel <= 14)
4349         {
4350                 LNA_Gain = GainValue & 0x00FF;
4351
4352                 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, OffsetValue);
4353                 Rssi0Offset = OffsetValue & 0x00FF;
4354                 Rssi1Offset = (OffsetValue & 0xFF00) >> 8;
4355                 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_BG_OFFSET + 2)/* 0x48 */, OffsetValue);
4356                 Rssi2Offset = OffsetValue & 0x00FF;
4357         }
4358         else
4359         {
4360                 LNA_Gain = (GainValue & 0xFF00) >> 8;
4361
4362                 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, OffsetValue);
4363                 Rssi0Offset = OffsetValue & 0x00FF;
4364                 Rssi1Offset = (OffsetValue & 0xFF00) >> 8;
4365                 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET + 2)/* 0x4C */, OffsetValue);
4366                 Rssi2Offset = OffsetValue & 0x00FF;
4367         }
4368         //**********************************************************************
4369         {
4370                 pAd->ate.Channel = channel;
4371                 ATEAsicSwitchChannel(pAd);
4372                 mdelay(5);
4373
4374                 data = 0x10;
4375                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, data);
4376                 data = 0x40;
4377                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, data);
4378                 data = 0x40;
4379                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, data);
4380                 mdelay(5);
4381
4382                 // start Rx
4383                 pAd->ate.bQARxStart = TRUE;
4384                 Set_ATE_Proc(pAd, "RXFRAME");
4385
4386                 mdelay(5);
4387
4388                 for (j = 0; j < 10; j++)
4389                 {
4390                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R50, &BbpR50Rssi0);
4391                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R51, &BbpR51Rssi1);
4392                         ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R52, &BbpR52Rssi2);
4393
4394                         mdelay(10);
4395
4396                         // calculate RSSI 0
4397                         if (BbpR50Rssi0 == 0)
4398                         {
4399                                 RSSI0 = -100;
4400                         }
4401                         else
4402                         {
4403                                 RSSI0 = (INT32)(-12 - BbpR50Rssi0 - LNA_Gain - Rssi0Offset);
4404                         }
4405                         RSSI[0][j] = RSSI0;
4406
4407                         if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
4408                         {
4409                                 // calculate RSSI 1
4410                                 if (BbpR51Rssi1 == 0)
4411                                 {
4412                                         RSSI1 = -100;
4413                                 }
4414                                 else
4415                                 {
4416                                         RSSI1 = (INT32)(-12 - BbpR51Rssi1 - LNA_Gain - Rssi1Offset);
4417                                 }
4418                                 RSSI[1][j] = RSSI1;
4419                         }
4420
4421                         if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
4422                         {
4423                                 // calculate RSSI 2
4424                                 if (BbpR52Rssi2 == 0)
4425                                         RSSI2 = -100;
4426                                 else
4427                                         RSSI2 = (INT32)(-12 - BbpR52Rssi2 - LNA_Gain - Rssi2Offset);
4428
4429                                 RSSI[2][j] = RSSI2;
4430                         }
4431                 }
4432
4433                 // stop Rx
4434                 Set_ATE_Proc(pAd, "RXSTOP");
4435
4436                 mdelay(5);
4437
4438                 BubbleSort(10, RSSI[0]);        // 1R
4439
4440                 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
4441                 {
4442                         BubbleSort(10, RSSI[1]);
4443                 }
4444
4445                 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
4446                 {
4447                         BubbleSort(10, RSSI[2]);
4448                 }
4449         }
4450
4451         pAd->ate.Channel = Org_Channel;
4452         ATEAsicSwitchChannel(pAd);
4453
4454         // restore original value
4455     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Org_BBP66value);
4456     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, Org_BBP69value);
4457     ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, Org_BBP70value);
4458
4459         return;
4460 }
4461
4462
4463 BOOLEAN SyncTxRxConfig(PRTMP_ADAPTER pAd, USHORT offset, UCHAR value)
4464 {
4465         UCHAR tmp = 0, bbp_data = 0;
4466
4467         if (ATE_ON(pAd))
4468         {
4469                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, offset, &bbp_data);
4470         }
4471         else
4472         {
4473                 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, offset, &bbp_data);
4474         }
4475
4476         /* confirm again */
4477         ASSERT(bbp_data == value);
4478
4479         switch (offset)
4480         {
4481                 case BBP_R1:
4482                         /* Need to synchronize tx configuration with legacy ATE. */
4483                         tmp = (bbp_data & ((1 << 4) | (1 << 3))/* 0x18 */) >> 3;
4484                     switch (tmp)
4485                     {
4486                                 /* The BBP R1 bit[4:3] = 2 :: Both DACs will be used by QA. */
4487                         case 2:
4488                                         /* All */
4489                                         pAd->ate.TxAntennaSel = 0;
4490                             break;
4491                                 /* The BBP R1 bit[4:3] = 0 :: DAC 0 will be used by QA. */
4492                         case 0:
4493                                         /* Antenna one */
4494                                         pAd->ate.TxAntennaSel = 1;
4495                             break;
4496                                 /* The BBP R1 bit[4:3] = 1 :: DAC 1 will be used by QA. */
4497                         case 1:
4498                                         /* Antenna two */
4499                                         pAd->ate.TxAntennaSel = 2;
4500                             break;
4501                         default:
4502                             DBGPRINT(RT_DEBUG_TRACE, ("%s -- Sth. wrong!  : return FALSE; \n", __FUNCTION__));
4503                             return FALSE;
4504                     }
4505                         break;/* case BBP_R1 */
4506
4507                 case BBP_R3:
4508                         /* Need to synchronize rx configuration with legacy ATE. */
4509                         tmp = (bbp_data & ((1 << 1) | (1 << 0))/* 0x03 */);
4510                     switch(tmp)
4511                     {
4512                                 /* The BBP R3 bit[1:0] = 3 :: All ADCs will be used by QA. */
4513                         case 3:
4514                                         /* All */
4515                                         pAd->ate.RxAntennaSel = 0;
4516                             break;
4517                                 /*
4518                                         The BBP R3 bit[1:0] = 0 :: ADC 0 will be used by QA,
4519                                         unless the BBP R3 bit[4:3] = 2
4520                                 */
4521                         case 0:
4522                                         /* Antenna one */
4523                                         pAd->ate.RxAntennaSel = 1;
4524                                         tmp = ((bbp_data & ((1 << 4) | (1 << 3))/* 0x03 */) >> 3);
4525                                         if (tmp == 2)// 3R
4526                                         {
4527                                                 /* Default : All ADCs will be used by QA */
4528                                                 pAd->ate.RxAntennaSel = 0;
4529                                         }
4530                             break;
4531                                 /* The BBP R3 bit[1:0] = 1 :: ADC 1 will be used by QA. */
4532                         case 1:
4533                                         /* Antenna two */
4534                                         pAd->ate.RxAntennaSel = 2;
4535                             break;
4536                                 /* The BBP R3 bit[1:0] = 2 :: ADC 2 will be used by QA. */
4537                         case 2:
4538                                         /* Antenna three */
4539                                         pAd->ate.RxAntennaSel = 3;
4540                             break;
4541                         default:
4542                             DBGPRINT(RT_DEBUG_ERROR, ("%s -- Impossible!  : return FALSE; \n", __FUNCTION__));
4543                             return FALSE;
4544                     }
4545                         break;/* case BBP_R3 */
4546
4547         default:
4548             DBGPRINT(RT_DEBUG_ERROR, ("%s -- Sth. wrong!  : return FALSE; \n", __FUNCTION__));
4549             return FALSE;
4550
4551         }
4552         return TRUE;
4553 }
4554
4555
4556 static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len)
4557 {
4558         ULONG i, Value = 0;
4559         ULONG *pDst, *pSrc;
4560         UCHAR *p8;
4561
4562         p8 = src;
4563         pDst = (ULONG *) dst;
4564         pSrc = (ULONG *) src;
4565
4566         for (i = 0 ; i < (len/4); i++)
4567         {
4568                 /* For alignment issue, we need a variable "Value". */
4569                 memmove(&Value, pSrc, 4);
4570                 Value = htonl(Value);
4571                 memmove(pDst, &Value, 4);
4572                 pDst++;
4573                 pSrc++;
4574         }
4575         if ((len % 4) != 0)
4576         {
4577                 /* wish that it will never reach here */
4578                 memmove(&Value, pSrc, (len % 4));
4579                 Value = htonl(Value);
4580                 memmove(pDst, &Value, (len % 4));
4581         }
4582 }
4583
4584
4585 static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len)
4586 {
4587         ULONG i;
4588         UCHAR *pDst, *pSrc;
4589
4590         pDst = dst;
4591         pSrc = src;
4592
4593         for (i = 0; i < (len/2); i++)
4594         {
4595                 memmove(pDst, pSrc, 2);
4596                 *((USHORT *)pDst) = htons(*((USHORT *)pDst));
4597                 pDst+=2;
4598                 pSrc+=2;
4599         }
4600
4601         if ((len % 2) != 0)
4602         {
4603                 memmove(pDst, pSrc, 1);
4604         }
4605 }
4606
4607
4608 static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, UINT32 len)
4609 {
4610         UINT32 i, Value;
4611         UINT32 *pDst, *pSrc;
4612
4613         pDst = (UINT32 *) dst;
4614         pSrc = (UINT32 *) src;
4615
4616         for (i = 0 ; i < (len/4); i++)
4617         {
4618                 RTMP_IO_READ32(pAd, (ULONG)pSrc, &Value);
4619                 Value = htonl(Value);
4620                 memmove(pDst, &Value, 4);
4621                 pDst++;
4622                 pSrc++;
4623         }
4624         return;
4625 }
4626
4627
4628 INT Set_TxStop_Proc(
4629         IN      PRTMP_ADAPTER   pAd,
4630         IN      PSTRING                 arg)
4631 {
4632         ATEDBGPRINT(RT_DEBUG_TRACE,("Set_TxStop_Proc\n"));
4633
4634         if (Set_ATE_Proc(pAd, "TXSTOP"))
4635         {
4636                 return TRUE;
4637         }
4638         else
4639         {
4640                 return FALSE;
4641         }
4642 }
4643
4644
4645 INT Set_RxStop_Proc(
4646         IN      PRTMP_ADAPTER   pAd,
4647         IN      PSTRING                 arg)
4648 {
4649         ATEDBGPRINT(RT_DEBUG_TRACE,("Set_RxStop_Proc\n"));
4650
4651         if (Set_ATE_Proc(pAd, "RXSTOP"))
4652         {
4653                 return TRUE;
4654         }
4655         else
4656         {
4657                 return FALSE;
4658         }
4659 }
4660
4661
4662 #ifdef DBG
4663 INT Set_EERead_Proc(
4664         IN      PRTMP_ADAPTER   pAd,
4665         IN      PSTRING                 arg)
4666 {
4667         USHORT buffer[EEPROM_SIZE/2];
4668         USHORT *p;
4669         INT i;
4670
4671         rt_ee_read_all(pAd, (USHORT *)buffer);
4672         p = buffer;
4673
4674         for (i = 0; i < (EEPROM_SIZE/2); i++)
4675         {
4676                 ate_print(KERN_EMERG "%4.4x ", *p);
4677                 if (((i+1) % 16) == 0)
4678                         ate_print(KERN_EMERG "\n");
4679                 p++;
4680         }
4681
4682         return TRUE;
4683 }
4684
4685
4686 INT Set_EEWrite_Proc(
4687         IN      PRTMP_ADAPTER   pAd,
4688         IN      PSTRING                 arg)
4689 {
4690         USHORT offset = 0, value;
4691         PSTRING p2 = arg;
4692
4693         while ((*p2 != ':') && (*p2 != '\0'))
4694         {
4695                 p2++;
4696         }
4697
4698         if (*p2 == ':')
4699         {
4700                 A2Hex(offset, arg);
4701                 A2Hex(value, p2 + 1);
4702         }
4703         else
4704         {
4705                 A2Hex(value, arg);
4706         }
4707
4708         if (offset >= EEPROM_SIZE)
4709         {
4710                 ate_print(KERN_EMERG "Offset can not exceed EEPROM_SIZE( == 0x%04x)\n", EEPROM_SIZE);
4711                 return FALSE;
4712         }
4713
4714         RT28xx_EEPROM_WRITE16(pAd, offset, value);
4715
4716         return TRUE;
4717 }
4718
4719
4720 INT Set_BBPRead_Proc(
4721         IN      PRTMP_ADAPTER   pAd,
4722         IN      PSTRING                 arg)
4723 {
4724         UCHAR value = 0, offset;
4725
4726         A2Hex(offset, arg);
4727
4728         if (ATE_ON(pAd))
4729         {
4730                 ATE_BBP_IO_READ8_BY_REG_ID(pAd, offset,  &value);
4731         }
4732         else
4733         {
4734                 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, offset,  &value);
4735         }
4736
4737         ate_print(KERN_EMERG "%x\n", value);
4738
4739         return TRUE;
4740 }
4741
4742
4743 INT Set_BBPWrite_Proc(
4744         IN      PRTMP_ADAPTER   pAd,
4745         IN      PSTRING                 arg)
4746 {
4747         USHORT offset = 0;
4748         PSTRING p2 = arg;
4749         UCHAR value;
4750
4751         while ((*p2 != ':') && (*p2 != '\0'))
4752         {
4753                 p2++;
4754         }
4755
4756         if (*p2 == ':')
4757         {
4758                 A2Hex(offset, arg);
4759                 A2Hex(value, p2 + 1);
4760         }
4761         else
4762         {
4763                 A2Hex(value, arg);
4764         }
4765
4766         if (ATE_ON(pAd))
4767         {
4768                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, offset,  value);
4769         }
4770         else
4771         {
4772                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, offset,  value);
4773         }
4774
4775         return TRUE;
4776 }
4777
4778
4779 INT Set_RFWrite_Proc(
4780         IN      PRTMP_ADAPTER   pAd,
4781         IN      PSTRING                 arg)
4782 {
4783         PSTRING p2, p3, p4;
4784         UINT32 R1, R2, R3, R4;
4785
4786         p2 = arg;
4787
4788         while ((*p2 != ':') && (*p2 != '\0'))
4789         {
4790                 p2++;
4791         }
4792
4793         if (*p2 != ':')
4794                 return FALSE;
4795
4796         p3 = p2 + 1;
4797
4798         while((*p3 != ':') && (*p3 != '\0'))
4799         {
4800                 p3++;
4801         }
4802
4803         if (*p3 != ':')
4804                 return FALSE;
4805
4806         p4 = p3 + 1;
4807
4808         while ((*p4 != ':') && (*p4 != '\0'))
4809         {
4810                 p4++;
4811         }
4812
4813         if (*p4 != ':')
4814                 return FALSE;
4815
4816
4817         A2Hex(R1, arg);
4818         A2Hex(R2, p2 + 1);
4819         A2Hex(R3, p3 + 1);
4820         A2Hex(R4, p4 + 1);
4821
4822         RTMP_RF_IO_WRITE32(pAd, R1);
4823         RTMP_RF_IO_WRITE32(pAd, R2);
4824         RTMP_RF_IO_WRITE32(pAd, R3);
4825         RTMP_RF_IO_WRITE32(pAd, R4);
4826
4827         return TRUE;
4828 }
4829 #endif // DBG //
4830 #endif // RALINK_28xx_QA //
4831
4832
4833
4834
4835 #ifdef RALINK_28xx_QA
4836 #define LEN_OF_ARG 16
4837
4838 #define RESPONSE_TO_GUI(__pRaCfg, __pwrq, __Length, __Status)                                                                   \
4839         (__pRaCfg)->length = htons((__Length));                                                                                                         \
4840         (__pRaCfg)->status = htons((__Status));                                                                                                         \
4841         (__pwrq)->u.data.length = sizeof((__pRaCfg)->magic_no) + sizeof((__pRaCfg)->command_type)       \
4842                                                         + sizeof((__pRaCfg)->command_id) + sizeof((__pRaCfg)->length)           \
4843                                                         + sizeof((__pRaCfg)->sequence) + ntohs((__pRaCfg)->length);                     \
4844         ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", (__pwrq)->u.data.length));            \
4845         if (copy_to_user((__pwrq)->u.data.pointer, (UCHAR *)(__pRaCfg), (__pwrq)->u.data.length))       \
4846         {                                                                                                                                                                                       \
4847                 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in %s\n", __FUNCTION__));                             \
4848                 return (-EFAULT);                                                                                                                                               \
4849         }                                                                                                                                                                                       \
4850         else                                                                                                                                                                            \
4851         {                                                                                                                                                                                       \
4852                 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s is done !\n", __FUNCTION__));                                                  \
4853         }
4854
4855 static inline INT       DO_RACFG_CMD_ATE_START(
4856         IN      PRTMP_ADAPTER   pAdapter,
4857         IN      struct iwreq    *wrq,
4858         IN  struct ate_racfghdr *pRaCfg)
4859 {
4860         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START\n"));
4861
4862         /* Prepare feedback as soon as we can to avoid QA timeout. */
4863         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
4864         Set_ATE_Proc(pAdapter, "ATESTART");
4865
4866         return NDIS_STATUS_SUCCESS;
4867 }
4868
4869
4870 static inline INT DO_RACFG_CMD_ATE_STOP(
4871         IN      PRTMP_ADAPTER   pAdapter,
4872         IN      struct iwreq    *wrq,
4873         IN  struct ate_racfghdr *pRaCfg)
4874 {
4875         INT32 ret;
4876
4877         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_STOP\n"));
4878
4879         /*
4880                 Distinguish this command came from QA(via ate agent)
4881                 or ate agent according to the existence of pid in payload.
4882
4883                 No need to prepare feedback if this cmd came directly from ate agent,
4884                 not from QA.
4885         */
4886         pRaCfg->length = ntohs(pRaCfg->length);
4887
4888         if (pRaCfg->length == sizeof(pAdapter->ate.AtePid))
4889         {
4890                 /*
4891                         This command came from QA.
4892                         Get the pid of ATE agent.
4893                 */
4894                 memcpy((UCHAR *)&pAdapter->ate.AtePid,
4895                                                 (&pRaCfg->data[0]) - 2/* == sizeof(pRaCfg->status) */,
4896                                                 sizeof(pAdapter->ate.AtePid));
4897
4898                 /* Prepare feedback as soon as we can to avoid QA timeout. */
4899                 RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
4900
4901                 /*
4902                         Kill ATE agent when leaving ATE mode.
4903
4904                         We must kill ATE agent first before setting ATESTOP,
4905                         or Microsoft will report sth. wrong.
4906                 */
4907                 ret = KILL_THREAD_PID(pAdapter->ate.AtePid, SIGTERM, 1);
4908
4909                 if (ret)
4910                 {
4911                         ATEDBGPRINT(RT_DEBUG_ERROR, ("%s: unable to kill ate thread\n", pAdapter->net_dev->name));
4912                 }
4913         }
4914
4915
4916         /* AP/STA might have in ATE_STOP mode due to cmd from QA. */
4917         if (ATE_ON(pAdapter))
4918         {
4919                 /* Someone has killed ate agent while QA GUI is still open. */
4920                 Set_ATE_Proc(pAdapter, "ATESTOP");
4921                 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_AP_START is done !\n"));
4922         }
4923
4924         return NDIS_STATUS_SUCCESS;
4925 }
4926
4927
4928 static inline INT DO_RACFG_CMD_RF_WRITE_ALL(
4929         IN      PRTMP_ADAPTER   pAdapter,
4930         IN      struct iwreq    *wrq,
4931         IN  struct ate_racfghdr *pRaCfg)
4932 {
4933         UINT32 R1, R2, R3, R4;
4934         USHORT channel;
4935
4936         memcpy(&R1, pRaCfg->data-2, 4);
4937         memcpy(&R2, pRaCfg->data+2, 4);
4938         memcpy(&R3, pRaCfg->data+6, 4);
4939         memcpy(&R4, pRaCfg->data+10, 4);
4940         memcpy(&channel, pRaCfg->data+14, 2);
4941
4942         pAdapter->LatchRfRegs.R1 = ntohl(R1);
4943         pAdapter->LatchRfRegs.R2 = ntohl(R2);
4944         pAdapter->LatchRfRegs.R3 = ntohl(R3);
4945         pAdapter->LatchRfRegs.R4 = ntohl(R4);
4946         pAdapter->LatchRfRegs.Channel = ntohs(channel);
4947
4948         RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R1);
4949         RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R2);
4950         RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R3);
4951         RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R4);
4952
4953         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
4954
4955         return  NDIS_STATUS_SUCCESS;
4956 }
4957
4958
4959 static inline INT DO_RACFG_CMD_E2PROM_READ16(
4960         IN      PRTMP_ADAPTER   pAdapter,
4961         IN      struct iwreq    *wrq,
4962         IN  struct ate_racfghdr *pRaCfg)
4963 {
4964         UINT16  offset=0, value=0;
4965         USHORT  tmp=0;
4966
4967         offset = ntohs(pRaCfg->status);
4968
4969         /* "tmp" is especially for some compilers... */
4970         RT28xx_EEPROM_READ16(pAdapter, offset, tmp);
4971         value = tmp;
4972         value = htons(value);
4973
4974         ATEDBGPRINT(RT_DEBUG_TRACE,("EEPROM Read offset = 0x%04x, value = 0x%04x\n", offset, value));
4975         memcpy(pRaCfg->data, &value, 2);
4976
4977         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+2, NDIS_STATUS_SUCCESS);
4978
4979         return NDIS_STATUS_SUCCESS;
4980 }
4981
4982
4983 static inline INT DO_RACFG_CMD_E2PROM_WRITE16(
4984         IN      PRTMP_ADAPTER   pAdapter,
4985         IN      struct iwreq    *wrq,
4986         IN  struct ate_racfghdr *pRaCfg)
4987 {
4988         USHORT  offset, value;
4989
4990         offset = ntohs(pRaCfg->status);
4991         memcpy(&value, pRaCfg->data, 2);
4992         value = ntohs(value);
4993         RT28xx_EEPROM_WRITE16(pAdapter, offset, value);
4994
4995         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
4996
4997         return NDIS_STATUS_SUCCESS;
4998 }
4999
5000
5001 static inline INT DO_RACFG_CMD_E2PROM_READ_ALL(
5002         IN      PRTMP_ADAPTER   pAdapter,
5003         IN      struct iwreq    *wrq,
5004         IN  struct ate_racfghdr *pRaCfg)
5005 {
5006         USHORT buffer[EEPROM_SIZE/2];
5007
5008         rt_ee_read_all(pAdapter,(USHORT *)buffer);
5009         memcpy_exs(pAdapter, pRaCfg->data, (UCHAR *)buffer, EEPROM_SIZE);
5010
5011         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+EEPROM_SIZE, NDIS_STATUS_SUCCESS);
5012
5013         return NDIS_STATUS_SUCCESS;
5014 }
5015
5016
5017 static inline INT DO_RACFG_CMD_E2PROM_WRITE_ALL(
5018         IN      PRTMP_ADAPTER   pAdapter,
5019         IN      struct iwreq    *wrq,
5020         IN  struct ate_racfghdr *pRaCfg)
5021 {
5022         USHORT buffer[EEPROM_SIZE/2];
5023
5024         NdisZeroMemory((UCHAR *)buffer, EEPROM_SIZE);
5025         memcpy_exs(pAdapter, (UCHAR *)buffer, (UCHAR *)&pRaCfg->status, EEPROM_SIZE);
5026         rt_ee_write_all(pAdapter,(USHORT *)buffer);
5027
5028         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5029
5030         return NDIS_STATUS_SUCCESS;
5031 }
5032
5033
5034 static inline INT DO_RACFG_CMD_IO_READ(
5035         IN      PRTMP_ADAPTER   pAdapter,
5036         IN      struct iwreq    *wrq,
5037         IN  struct ate_racfghdr *pRaCfg)
5038 {
5039         UINT32  offset;
5040         UINT32  value;
5041
5042         memcpy(&offset, &pRaCfg->status, 4);
5043         offset = ntohl(offset);
5044
5045         /*
5046                 We do not need the base address.
5047                 So just extract the offset out.
5048         */
5049         offset &= 0x0000FFFF;
5050         RTMP_IO_READ32(pAdapter, offset, &value);
5051         value = htonl(value);
5052         memcpy(pRaCfg->data, &value, 4);
5053
5054         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+4, NDIS_STATUS_SUCCESS);
5055
5056         return NDIS_STATUS_SUCCESS;
5057 }
5058
5059
5060 static inline INT DO_RACFG_CMD_IO_WRITE(
5061         IN      PRTMP_ADAPTER   pAdapter,
5062         IN      struct iwreq    *wrq,
5063         IN  struct ate_racfghdr *pRaCfg)
5064 {
5065         UINT32  offset, value;
5066
5067         memcpy(&offset, pRaCfg->data-2, 4);
5068         memcpy(&value, pRaCfg->data+2, 4);
5069
5070         offset = ntohl(offset);
5071
5072         /*
5073                 We do not need the base address.
5074                 So just extract the offset out.
5075         */
5076         offset &= 0x0000FFFF;
5077         value = ntohl(value);
5078         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_IO_WRITE: offset = %x, value = %x\n", offset, value));
5079         RTMP_IO_WRITE32(pAdapter, offset, value);
5080
5081         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5082
5083         return NDIS_STATUS_SUCCESS;
5084 }
5085
5086
5087 static inline INT DO_RACFG_CMD_IO_READ_BULK(
5088         IN      PRTMP_ADAPTER   pAdapter,
5089         IN      struct iwreq    *wrq,
5090         IN  struct ate_racfghdr *pRaCfg)
5091 {
5092         UINT32  offset;
5093         USHORT  len;
5094
5095         memcpy(&offset, &pRaCfg->status, 4);
5096         offset = ntohl(offset);
5097
5098         /*
5099                 We do not need the base address.
5100                 So just extract the offset out.
5101         */
5102         offset &= 0x0000FFFF;
5103         memcpy(&len, pRaCfg->data+2, 2);
5104         len = ntohs(len);
5105
5106         if (len > 371)
5107         {
5108                 ATEDBGPRINT(RT_DEBUG_TRACE,("length requested is too large, make it smaller\n"));
5109                 pRaCfg->length = htons(2);
5110                 pRaCfg->status = htons(1);
5111                 return -EFAULT;
5112         }
5113
5114         RTMP_IO_READ_BULK(pAdapter, pRaCfg->data, (UCHAR *)offset, len*4);// unit in four bytes
5115
5116         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+(len*4), NDIS_STATUS_SUCCESS);
5117
5118         return NDIS_STATUS_SUCCESS;
5119 }
5120
5121
5122 static inline INT DO_RACFG_CMD_BBP_READ8(
5123         IN      PRTMP_ADAPTER   pAdapter,
5124         IN      struct iwreq    *wrq,
5125         IN  struct ate_racfghdr *pRaCfg)
5126 {
5127         USHORT  offset;
5128         UCHAR   value;
5129
5130         value = 0;
5131         offset = ntohs(pRaCfg->status);
5132
5133         if (ATE_ON(pAdapter))
5134         {
5135                 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, offset, &value);
5136         }
5137         else
5138         {
5139                 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, offset, &value);
5140         }
5141
5142         pRaCfg->data[0] = value;
5143
5144         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+1, NDIS_STATUS_SUCCESS);
5145
5146         return NDIS_STATUS_SUCCESS;
5147 }
5148
5149
5150 static inline INT DO_RACFG_CMD_BBP_WRITE8(
5151         IN      PRTMP_ADAPTER   pAdapter,
5152         IN      struct iwreq    *wrq,
5153         IN  struct ate_racfghdr *pRaCfg)
5154 {
5155         USHORT  offset;
5156         UCHAR   value;
5157
5158         offset = ntohs(pRaCfg->status);
5159         memcpy(&value, pRaCfg->data, 1);
5160
5161         if (ATE_ON(pAdapter))
5162         {
5163                 ATE_BBP_IO_WRITE8_BY_REG_ID(pAdapter, offset, value);
5164         }
5165         else
5166         {
5167                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, offset, value);
5168         }
5169
5170         if ((offset == BBP_R1) || (offset == BBP_R3))
5171         {
5172                 SyncTxRxConfig(pAdapter, offset, value);
5173         }
5174
5175         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5176
5177         return NDIS_STATUS_SUCCESS;
5178 }
5179
5180
5181 static inline INT DO_RACFG_CMD_BBP_READ_ALL(
5182         IN      PRTMP_ADAPTER   pAdapter,
5183         IN      struct iwreq    *wrq,
5184         IN  struct ate_racfghdr *pRaCfg)
5185 {
5186         USHORT bbp_reg_index;
5187
5188         for (bbp_reg_index = 0; bbp_reg_index < MAX_BBP_ID+1; bbp_reg_index++)
5189         {
5190                 pRaCfg->data[bbp_reg_index] = 0;
5191
5192                 if (ATE_ON(pAdapter))
5193                 {
5194                         ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, bbp_reg_index, &pRaCfg->data[bbp_reg_index]);
5195                 }
5196                 else
5197                 {
5198                         RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, bbp_reg_index, &pRaCfg->data[bbp_reg_index]);
5199                 }
5200         }
5201
5202         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+MAX_BBP_ID+1, NDIS_STATUS_SUCCESS);
5203
5204         return NDIS_STATUS_SUCCESS;
5205 }
5206
5207
5208 static inline INT DO_RACFG_CMD_GET_NOISE_LEVEL(
5209         IN      PRTMP_ADAPTER   pAdapter,
5210         IN      struct iwreq    *wrq,
5211         IN  struct ate_racfghdr *pRaCfg)
5212 {
5213         UCHAR   channel;
5214         INT32   buffer[3][10];/* 3 : RxPath ; 10 : no. of per rssi samples */
5215
5216         channel = (ntohs(pRaCfg->status) & 0x00FF);
5217         CalNoiseLevel(pAdapter, channel, buffer);
5218         memcpy_exl(pAdapter, (UCHAR *)pRaCfg->data, (UCHAR *)&(buffer[0][0]), (sizeof(INT32)*3*10));
5219
5220         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+(sizeof(INT32)*3*10), NDIS_STATUS_SUCCESS);
5221
5222         return NDIS_STATUS_SUCCESS;
5223 }
5224
5225
5226 static inline INT DO_RACFG_CMD_GET_COUNTER(
5227         IN      PRTMP_ADAPTER   pAdapter,
5228         IN      struct iwreq    *wrq,
5229         IN  struct ate_racfghdr *pRaCfg)
5230 {
5231         memcpy_exl(pAdapter, &pRaCfg->data[0], (UCHAR *)&pAdapter->ate.U2M, 4);
5232         memcpy_exl(pAdapter, &pRaCfg->data[4], (UCHAR *)&pAdapter->ate.OtherData, 4);
5233         memcpy_exl(pAdapter, &pRaCfg->data[8], (UCHAR *)&pAdapter->ate.Beacon, 4);
5234         memcpy_exl(pAdapter, &pRaCfg->data[12], (UCHAR *)&pAdapter->ate.OtherCount, 4);
5235         memcpy_exl(pAdapter, &pRaCfg->data[16], (UCHAR *)&pAdapter->ate.TxAc0, 4);
5236         memcpy_exl(pAdapter, &pRaCfg->data[20], (UCHAR *)&pAdapter->ate.TxAc1, 4);
5237         memcpy_exl(pAdapter, &pRaCfg->data[24], (UCHAR *)&pAdapter->ate.TxAc2, 4);
5238         memcpy_exl(pAdapter, &pRaCfg->data[28], (UCHAR *)&pAdapter->ate.TxAc3, 4);
5239         /*memcpy_exl(pAdapter, &pRaCfg->data[32], (UCHAR *)&pAdapter->ate.TxHCCA, 4);*/
5240         memcpy_exl(pAdapter, &pRaCfg->data[36], (UCHAR *)&pAdapter->ate.TxMgmt, 4);
5241         memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&pAdapter->ate.RSSI0, 4);
5242         memcpy_exl(pAdapter, &pRaCfg->data[44], (UCHAR *)&pAdapter->ate.RSSI1, 4);
5243         memcpy_exl(pAdapter, &pRaCfg->data[48], (UCHAR *)&pAdapter->ate.RSSI2, 4);
5244         memcpy_exl(pAdapter, &pRaCfg->data[52], (UCHAR *)&pAdapter->ate.SNR0, 4);
5245         memcpy_exl(pAdapter, &pRaCfg->data[56], (UCHAR *)&pAdapter->ate.SNR1, 4);
5246
5247         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+60, NDIS_STATUS_SUCCESS);
5248
5249         return NDIS_STATUS_SUCCESS;
5250 }
5251
5252
5253 static inline INT DO_RACFG_CMD_CLEAR_COUNTER(
5254         IN      PRTMP_ADAPTER   pAdapter,
5255         IN      struct iwreq    *wrq,
5256         IN  struct ate_racfghdr *pRaCfg)
5257 {
5258         pAdapter->ate.U2M = 0;
5259         pAdapter->ate.OtherData = 0;
5260         pAdapter->ate.Beacon = 0;
5261         pAdapter->ate.OtherCount = 0;
5262         pAdapter->ate.TxAc0 = 0;
5263         pAdapter->ate.TxAc1 = 0;
5264         pAdapter->ate.TxAc2 = 0;
5265         pAdapter->ate.TxAc3 = 0;
5266         /*pAdapter->ate.TxHCCA = 0;*/
5267         pAdapter->ate.TxMgmt = 0;
5268         pAdapter->ate.TxDoneCount = 0;
5269
5270         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5271
5272         return NDIS_STATUS_SUCCESS;
5273 }
5274
5275
5276 static inline INT DO_RACFG_CMD_TX_START(
5277         IN      PRTMP_ADAPTER   pAdapter,
5278         IN      struct iwreq    *wrq,
5279         IN  struct ate_racfghdr *pRaCfg)
5280 {
5281         USHORT *p;
5282         USHORT  err = 1;
5283         UCHAR   Bbp22Value = 0, Bbp24Value = 0;
5284
5285         if ((pAdapter->ate.TxStatus != 0) && (pAdapter->ate.Mode & ATE_TXFRAME))
5286         {
5287                 ATEDBGPRINT(RT_DEBUG_TRACE,("Ate Tx is already running, to run next Tx, you must stop it first\n"));
5288                 err = 2;
5289                 goto TX_START_ERROR;
5290         }
5291         else if ((pAdapter->ate.TxStatus != 0) && !(pAdapter->ate.Mode & ATE_TXFRAME))
5292         {
5293                 int i = 0;
5294
5295                 while ((i++ < 10) && (pAdapter->ate.TxStatus != 0))
5296                 {
5297                         RTMPusecDelay(5000);
5298                 }
5299
5300                 /* force it to stop */
5301                 pAdapter->ate.TxStatus = 0;
5302                 pAdapter->ate.TxDoneCount = 0;
5303                 pAdapter->ate.bQATxStart = FALSE;
5304         }
5305
5306         /*
5307                 If pRaCfg->length == 0, this "RACFG_CMD_TX_START"
5308                 is for Carrier test or Carrier Suppression.
5309         */
5310         if (ntohs(pRaCfg->length) != 0)
5311         {
5312                 /* get frame info */
5313
5314                 NdisMoveMemory(&pAdapter->ate.TxWI, pRaCfg->data + 2, 16);
5315 #ifdef RT_BIG_ENDIAN
5316                 RTMPWIEndianChange((PUCHAR)&pAdapter->ate.TxWI, TYPE_TXWI);
5317 #endif // RT_BIG_ENDIAN //
5318
5319                 NdisMoveMemory(&pAdapter->ate.TxCount, pRaCfg->data + 18, 4);
5320                 pAdapter->ate.TxCount = ntohl(pAdapter->ate.TxCount);
5321
5322                 p = (USHORT *)(&pRaCfg->data[22]);
5323
5324                 /* always use QID_AC_BE */
5325                 pAdapter->ate.QID = 0;
5326
5327                 p = (USHORT *)(&pRaCfg->data[24]);
5328                 pAdapter->ate.HLen = ntohs(*p);
5329
5330                 if (pAdapter->ate.HLen > 32)
5331                 {
5332                         ATEDBGPRINT(RT_DEBUG_ERROR,("pAdapter->ate.HLen > 32\n"));
5333                         err = 3;
5334                         goto TX_START_ERROR;
5335                 }
5336
5337                 NdisMoveMemory(&pAdapter->ate.Header, pRaCfg->data + 26, pAdapter->ate.HLen);
5338
5339                 pAdapter->ate.PLen = ntohs(pRaCfg->length) - (pAdapter->ate.HLen + 28);
5340
5341                 if (pAdapter->ate.PLen > 32)
5342                 {
5343                         ATEDBGPRINT(RT_DEBUG_ERROR,("pAdapter->ate.PLen > 32\n"));
5344                         err = 4;
5345                         goto TX_START_ERROR;
5346                 }
5347
5348                 NdisMoveMemory(&pAdapter->ate.Pattern, pRaCfg->data + 26 + pAdapter->ate.HLen, pAdapter->ate.PLen);
5349                 pAdapter->ate.DLen = pAdapter->ate.TxWI.MPDUtotalByteCount - pAdapter->ate.HLen;
5350         }
5351
5352         ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R22, &Bbp22Value);
5353
5354         switch (Bbp22Value)
5355         {
5356                 case BBP22_TXFRAME:
5357                         {
5358                                 if (pAdapter->ate.TxCount == 0)
5359                                 {
5360 #ifdef RTMP_MAC_PCI
5361                                         pAdapter->ate.TxCount = 0xFFFFFFFF;
5362 #endif // RTMP_MAC_PCI //
5363                                 }
5364                                 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXFRAME\n"));
5365                                 pAdapter->ate.bQATxStart = TRUE;
5366                                 Set_ATE_Proc(pAdapter, "TXFRAME");
5367                         }
5368                         break;
5369
5370                 case BBP22_TXCONT_OR_CARRSUPP:
5371                         {
5372                                 ATEDBGPRINT(RT_DEBUG_TRACE,("BBP22_TXCONT_OR_CARRSUPP\n"));
5373                                 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R24, &Bbp24Value);
5374
5375                                 switch (Bbp24Value)
5376                                 {
5377                                         case BBP24_TXCONT:
5378                                                 {
5379                                                         ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCONT\n"));
5380                                                         pAdapter->ate.bQATxStart = TRUE;
5381                                                         Set_ATE_Proc(pAdapter, "TXCONT");
5382                                                 }
5383                                                 break;
5384
5385                                         case BBP24_CARRSUPP:
5386                                                 {
5387                                                         ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCARRSUPP\n"));
5388                                                         pAdapter->ate.bQATxStart = TRUE;
5389                                                         pAdapter->ate.Mode |= ATE_TXCARRSUPP;
5390                                                 }
5391                                                 break;
5392
5393                                         default:
5394                                                 {
5395                                                         ATEDBGPRINT(RT_DEBUG_ERROR,("Unknown TX subtype !"));
5396                                                 }
5397                                                 break;
5398                                 }
5399                         }
5400                         break;
5401
5402                 case BBP22_TXCARR:
5403                         {
5404                                 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCARR\n"));
5405                                 pAdapter->ate.bQATxStart = TRUE;
5406                                 Set_ATE_Proc(pAdapter, "TXCARR");
5407                         }
5408                         break;
5409
5410                 default:
5411                         {
5412                                 ATEDBGPRINT(RT_DEBUG_ERROR,("Unknown Start TX subtype !"));
5413                         }
5414                         break;
5415         }
5416
5417         if (pAdapter->ate.bQATxStart == TRUE)
5418         {
5419                 RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5420                 return NDIS_STATUS_SUCCESS;
5421         }
5422
5423 TX_START_ERROR:
5424         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), err);
5425
5426         return err;
5427 }
5428
5429
5430 static inline INT DO_RACFG_CMD_GET_TX_STATUS(
5431         IN      PRTMP_ADAPTER   pAdapter,
5432         IN      struct iwreq    *wrq,
5433         IN  struct ate_racfghdr *pRaCfg)
5434 {
5435         UINT32 count=0;
5436
5437         count = htonl(pAdapter->ate.TxDoneCount);
5438         NdisMoveMemory(pRaCfg->data, &count, 4);
5439
5440         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+4, NDIS_STATUS_SUCCESS);
5441
5442         return NDIS_STATUS_SUCCESS;
5443 }
5444
5445
5446 static inline INT DO_RACFG_CMD_TX_STOP(
5447         IN      PRTMP_ADAPTER   pAdapter,
5448         IN      struct iwreq    *wrq,
5449         IN  struct ate_racfghdr *pRaCfg)
5450 {
5451         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_TX_STOP\n"));
5452
5453         Set_ATE_Proc(pAdapter, "TXSTOP");
5454
5455         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5456
5457         return NDIS_STATUS_SUCCESS;
5458 }
5459
5460
5461 static inline INT DO_RACFG_CMD_RX_START(
5462         IN      PRTMP_ADAPTER   pAdapter,
5463         IN      struct iwreq    *wrq,
5464         IN  struct ate_racfghdr *pRaCfg)
5465 {
5466         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n"));
5467
5468         pAdapter->ate.bQARxStart = TRUE;
5469         Set_ATE_Proc(pAdapter, "RXFRAME");
5470
5471         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5472
5473         return NDIS_STATUS_SUCCESS;
5474 }
5475
5476
5477 static inline INT DO_RACFG_CMD_RX_STOP(
5478         IN      PRTMP_ADAPTER   pAdapter,
5479         IN      struct iwreq    *wrq,
5480         IN  struct ate_racfghdr *pRaCfg)
5481 {
5482         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_STOP\n"));
5483
5484         Set_ATE_Proc(pAdapter, "RXSTOP");
5485
5486         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5487
5488         return NDIS_STATUS_SUCCESS;
5489 }
5490
5491
5492 static inline INT DO_RACFG_CMD_ATE_START_TX_CARRIER(
5493         IN      PRTMP_ADAPTER   pAdapter,
5494         IN      struct iwreq    *wrq,
5495         IN  struct ate_racfghdr *pRaCfg)
5496 {
5497         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CARRIER\n"));
5498
5499         Set_ATE_Proc(pAdapter, "TXCARR");
5500
5501         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5502
5503         return NDIS_STATUS_SUCCESS;
5504 }
5505
5506
5507 static inline INT DO_RACFG_CMD_ATE_START_TX_CONT(
5508         IN      PRTMP_ADAPTER   pAdapter,
5509         IN      struct iwreq    *wrq,
5510         IN  struct ate_racfghdr *pRaCfg)
5511 {
5512         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CONT\n"));
5513
5514         Set_ATE_Proc(pAdapter, "TXCONT");
5515
5516         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5517
5518         return NDIS_STATUS_SUCCESS;
5519 }
5520
5521
5522 static inline INT DO_RACFG_CMD_ATE_START_TX_FRAME(
5523         IN      PRTMP_ADAPTER   pAdapter,
5524         IN      struct iwreq    *wrq,
5525         IN  struct ate_racfghdr *pRaCfg)
5526 {
5527         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_FRAME\n"));
5528
5529         Set_ATE_Proc(pAdapter, "TXFRAME");
5530
5531         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5532
5533         return NDIS_STATUS_SUCCESS;
5534 }
5535
5536
5537 static inline INT DO_RACFG_CMD_ATE_SET_BW(
5538         IN      PRTMP_ADAPTER   pAdapter,
5539         IN      struct iwreq    *wrq,
5540         IN  struct ate_racfghdr *pRaCfg)
5541 {
5542         SHORT    value = 0;
5543         STRING    str[LEN_OF_ARG];
5544
5545         NdisZeroMemory(str, LEN_OF_ARG);
5546
5547         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_BW\n"));
5548
5549         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5550         value = ntohs(value);
5551         sprintf((char *)str, "%d", value);
5552
5553         Set_ATE_TX_BW_Proc(pAdapter, str);
5554
5555         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5556
5557         return NDIS_STATUS_SUCCESS;
5558 }
5559
5560
5561 static inline INT DO_RACFG_CMD_ATE_SET_TX_POWER0(
5562         IN      PRTMP_ADAPTER   pAdapter,
5563         IN      struct iwreq    *wrq,
5564         IN  struct ate_racfghdr *pRaCfg)
5565 {
5566         SHORT    value = 0;
5567         STRING    str[LEN_OF_ARG];
5568
5569         NdisZeroMemory(str, LEN_OF_ARG);
5570
5571         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER0\n"));
5572
5573         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5574         value = ntohs(value);
5575         sprintf((char *)str, "%d", value);
5576         Set_ATE_TX_POWER0_Proc(pAdapter, str);
5577
5578         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5579
5580         return NDIS_STATUS_SUCCESS;
5581 }
5582
5583
5584 static inline INT DO_RACFG_CMD_ATE_SET_TX_POWER1(
5585         IN      PRTMP_ADAPTER   pAdapter,
5586         IN      struct iwreq    *wrq,
5587         IN  struct ate_racfghdr *pRaCfg)
5588 {
5589         SHORT    value = 0;
5590         STRING    str[LEN_OF_ARG];
5591
5592         NdisZeroMemory(str, LEN_OF_ARG);
5593
5594         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER1\n"));
5595
5596         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5597         value = ntohs(value);
5598         sprintf((char *)str, "%d", value);
5599         Set_ATE_TX_POWER1_Proc(pAdapter, str);
5600
5601         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5602
5603         return NDIS_STATUS_SUCCESS;
5604 }
5605
5606
5607 static inline INT DO_RACFG_CMD_ATE_SET_FREQ_OFFSET(
5608         IN      PRTMP_ADAPTER   pAdapter,
5609         IN      struct iwreq    *wrq,
5610         IN  struct ate_racfghdr *pRaCfg)
5611 {
5612         SHORT    value = 0;
5613         STRING    str[LEN_OF_ARG];
5614
5615         NdisZeroMemory(str, LEN_OF_ARG);
5616
5617         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_FREQ_OFFSET\n"));
5618
5619         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5620         value = ntohs(value);
5621         sprintf((char *)str, "%d", value);
5622         Set_ATE_TX_FREQOFFSET_Proc(pAdapter, str);
5623
5624         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5625
5626         return NDIS_STATUS_SUCCESS;
5627 }
5628
5629
5630 static inline INT DO_RACFG_CMD_ATE_GET_STATISTICS(
5631         IN      PRTMP_ADAPTER   pAdapter,
5632         IN      struct iwreq    *wrq,
5633         IN  struct ate_racfghdr *pRaCfg)
5634 {
5635         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_GET_STATISTICS\n"));
5636
5637         memcpy_exl(pAdapter, &pRaCfg->data[0], (UCHAR *)&pAdapter->ate.TxDoneCount, 4);
5638         memcpy_exl(pAdapter, &pRaCfg->data[4], (UCHAR *)&pAdapter->WlanCounters.RetryCount.u.LowPart, 4);
5639         memcpy_exl(pAdapter, &pRaCfg->data[8], (UCHAR *)&pAdapter->WlanCounters.FailedCount.u.LowPart, 4);
5640         memcpy_exl(pAdapter, &pRaCfg->data[12], (UCHAR *)&pAdapter->WlanCounters.RTSSuccessCount.u.LowPart, 4);
5641         memcpy_exl(pAdapter, &pRaCfg->data[16], (UCHAR *)&pAdapter->WlanCounters.RTSFailureCount.u.LowPart, 4);
5642         memcpy_exl(pAdapter, &pRaCfg->data[20], (UCHAR *)&pAdapter->WlanCounters.ReceivedFragmentCount.QuadPart, 4);
5643         memcpy_exl(pAdapter, &pRaCfg->data[24], (UCHAR *)&pAdapter->WlanCounters.FCSErrorCount.u.LowPart, 4);
5644         memcpy_exl(pAdapter, &pRaCfg->data[28], (UCHAR *)&pAdapter->Counters8023.RxNoBuffer, 4);
5645         memcpy_exl(pAdapter, &pRaCfg->data[32], (UCHAR *)&pAdapter->WlanCounters.FrameDuplicateCount.u.LowPart, 4);
5646         memcpy_exl(pAdapter, &pRaCfg->data[36], (UCHAR *)&pAdapter->RalinkCounters.OneSecFalseCCACnt, 4);
5647
5648         if (pAdapter->ate.RxAntennaSel == 0)
5649         {
5650                 INT32 RSSI0 = 0;
5651                 INT32 RSSI1 = 0;
5652                 INT32 RSSI2 = 0;
5653
5654                 RSSI0 = (INT32)(pAdapter->ate.LastRssi0 - pAdapter->BbpRssiToDbmDelta);
5655                 RSSI1 = (INT32)(pAdapter->ate.LastRssi1 - pAdapter->BbpRssiToDbmDelta);
5656                 RSSI2 = (INT32)(pAdapter->ate.LastRssi2 - pAdapter->BbpRssiToDbmDelta);
5657                 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4);
5658                 memcpy_exl(pAdapter, &pRaCfg->data[44], (UCHAR *)&RSSI1, 4);
5659                 memcpy_exl(pAdapter, &pRaCfg->data[48], (UCHAR *)&RSSI2, 4);
5660                 RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+52, NDIS_STATUS_SUCCESS);
5661         }
5662         else
5663         {
5664                 INT32 RSSI0 = 0;
5665
5666                 RSSI0 = (INT32)(pAdapter->ate.LastRssi0 - pAdapter->BbpRssiToDbmDelta);
5667                 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4);
5668                 RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+44, NDIS_STATUS_SUCCESS);
5669         }
5670
5671         return NDIS_STATUS_SUCCESS;
5672 }
5673
5674
5675 static inline INT DO_RACFG_CMD_ATE_RESET_COUNTER(
5676         IN      PRTMP_ADAPTER   pAdapter,
5677         IN      struct iwreq    *wrq,
5678         IN  struct ate_racfghdr *pRaCfg)
5679 {
5680         SHORT    value = 1;
5681         STRING    str[LEN_OF_ARG];
5682
5683         NdisZeroMemory(str, LEN_OF_ARG);
5684
5685         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_RESET_COUNTER\n"));
5686
5687         sprintf((char *)str, "%d", value);
5688         Set_ResetStatCounter_Proc(pAdapter, str);
5689
5690         pAdapter->ate.TxDoneCount = 0;
5691
5692         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5693
5694         return NDIS_STATUS_SUCCESS;
5695 }
5696
5697
5698 static inline INT DO_RACFG_CMD_ATE_SEL_TX_ANTENNA(
5699         IN      PRTMP_ADAPTER   pAdapter,
5700         IN      struct iwreq    *wrq,
5701         IN  struct ate_racfghdr *pRaCfg)
5702 {
5703         SHORT    value = 0;
5704         STRING    str[LEN_OF_ARG];
5705
5706         NdisZeroMemory(str, LEN_OF_ARG);
5707
5708         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_TX_ANTENNA\n"));
5709
5710         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5711         value = ntohs(value);
5712         sprintf((char *)str, "%d", value);
5713         Set_ATE_TX_Antenna_Proc(pAdapter, str);
5714
5715         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5716
5717         return NDIS_STATUS_SUCCESS;
5718 }
5719
5720
5721 static inline INT DO_RACFG_CMD_ATE_SEL_RX_ANTENNA(
5722         IN      PRTMP_ADAPTER   pAdapter,
5723         IN      struct iwreq    *wrq,
5724         IN  struct ate_racfghdr *pRaCfg)
5725 {
5726         SHORT    value = 0;
5727         STRING    str[LEN_OF_ARG];
5728
5729         NdisZeroMemory(str, LEN_OF_ARG);
5730
5731         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_RX_ANTENNA\n"));
5732
5733         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5734         value = ntohs(value);
5735         sprintf((char *)str, "%d", value);
5736         Set_ATE_RX_Antenna_Proc(pAdapter, str);
5737
5738         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5739
5740         return NDIS_STATUS_SUCCESS;
5741 }
5742
5743
5744 static inline INT DO_RACFG_CMD_ATE_SET_PREAMBLE(
5745         IN      PRTMP_ADAPTER   pAdapter,
5746         IN      struct iwreq    *wrq,
5747         IN  struct ate_racfghdr *pRaCfg)
5748 {
5749         SHORT    value = 0;
5750         STRING    str[LEN_OF_ARG];
5751
5752         NdisZeroMemory(str, LEN_OF_ARG);
5753
5754         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_PREAMBLE\n"));
5755
5756         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5757         value = ntohs(value);
5758         sprintf((char *)str, "%d", value);
5759         Set_ATE_TX_MODE_Proc(pAdapter, str);
5760
5761         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5762
5763         return NDIS_STATUS_SUCCESS;
5764 }
5765
5766
5767 static inline INT DO_RACFG_CMD_ATE_SET_CHANNEL(
5768         IN      PRTMP_ADAPTER   pAdapter,
5769         IN      struct iwreq    *wrq,
5770         IN  struct ate_racfghdr *pRaCfg)
5771 {
5772         SHORT    value = 0;
5773         STRING    str[LEN_OF_ARG];
5774
5775         NdisZeroMemory(str, LEN_OF_ARG);
5776
5777         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_CHANNEL\n"));
5778
5779         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5780         value = ntohs(value);
5781         sprintf((char *)str, "%d", value);
5782         Set_ATE_CHANNEL_Proc(pAdapter, str);
5783
5784         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5785
5786         return NDIS_STATUS_SUCCESS;
5787 }
5788
5789
5790 static inline INT DO_RACFG_CMD_ATE_SET_ADDR1(
5791         IN      PRTMP_ADAPTER   pAdapter,
5792         IN      struct iwreq    *wrq,
5793         IN  struct ate_racfghdr *pRaCfg)
5794 {
5795         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR1\n"));
5796
5797         /*
5798                 Addr is an array of UCHAR,
5799                 so no need to perform endian swap.
5800         */
5801         memcpy(pAdapter->ate.Addr1, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5802
5803         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5804
5805         return NDIS_STATUS_SUCCESS;
5806 }
5807
5808
5809 static inline INT DO_RACFG_CMD_ATE_SET_ADDR2(
5810         IN      PRTMP_ADAPTER   pAdapter,
5811         IN      struct iwreq    *wrq,
5812         IN  struct ate_racfghdr *pRaCfg)
5813 {
5814         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR2\n"));
5815
5816         /*
5817                 Addr is an array of UCHAR,
5818                 so no need to perform endian swap.
5819         */
5820         memcpy(pAdapter->ate.Addr2, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5821
5822         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5823
5824         return NDIS_STATUS_SUCCESS;
5825 }
5826
5827
5828 static inline INT DO_RACFG_CMD_ATE_SET_ADDR3(
5829         IN      PRTMP_ADAPTER   pAdapter,
5830         IN      struct iwreq    *wrq,
5831         IN  struct ate_racfghdr *pRaCfg)
5832 {
5833         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR3\n"));
5834
5835         /*
5836                 Addr is an array of UCHAR,
5837                 so no need to perform endian swap.
5838         */
5839         memcpy(pAdapter->ate.Addr3, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5840
5841         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5842
5843         return NDIS_STATUS_SUCCESS;
5844 }
5845
5846
5847 static inline INT DO_RACFG_CMD_ATE_SET_RATE(
5848         IN      PRTMP_ADAPTER   pAdapter,
5849         IN      struct iwreq    *wrq,
5850         IN  struct ate_racfghdr *pRaCfg)
5851 {
5852         SHORT    value = 0;
5853         STRING    str[LEN_OF_ARG];
5854
5855         NdisZeroMemory(str, LEN_OF_ARG);
5856
5857         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_RATE\n"));
5858
5859         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5860         value = ntohs(value);
5861         sprintf((char *)str, "%d", value);
5862         Set_ATE_TX_MCS_Proc(pAdapter, str);
5863
5864         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5865
5866         return NDIS_STATUS_SUCCESS;
5867 }
5868
5869
5870 static inline INT DO_RACFG_CMD_ATE_SET_TX_FRAME_LEN(
5871         IN      PRTMP_ADAPTER   pAdapter,
5872         IN      struct iwreq    *wrq,
5873         IN  struct ate_racfghdr *pRaCfg)
5874 {
5875         SHORT    value = 0;
5876         STRING    str[LEN_OF_ARG];
5877
5878         NdisZeroMemory(str, LEN_OF_ARG);
5879
5880         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_LEN\n"));
5881
5882         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5883         value = ntohs(value);
5884         sprintf((char *)str, "%d", value);
5885         Set_ATE_TX_LENGTH_Proc(pAdapter, str);
5886
5887         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5888
5889         return NDIS_STATUS_SUCCESS;
5890 }
5891
5892
5893 static inline INT DO_RACFG_CMD_ATE_SET_TX_FRAME_COUNT(
5894         IN      PRTMP_ADAPTER   pAdapter,
5895         IN      struct iwreq    *wrq,
5896         IN  struct ate_racfghdr *pRaCfg)
5897 {
5898         USHORT    value = 0;
5899         STRING    str[LEN_OF_ARG];
5900
5901         NdisZeroMemory(str, LEN_OF_ARG);
5902
5903         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_COUNT\n"));
5904
5905         memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5906         value = ntohs(value);
5907
5908 #ifdef RTMP_MAC_PCI
5909         /* TX_FRAME_COUNT == 0 means tx infinitely */
5910         if (value == 0)
5911         {
5912                 /* Use TxCount = 0xFFFFFFFF to approximate the infinity. */
5913                 pAdapter->ate.TxCount = 0xFFFFFFFF;
5914                 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_COUNT_Proc (TxCount = %d)\n", pAdapter->ate.TxCount));
5915                 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_COUNT_Proc Success\n"));
5916
5917
5918         }
5919         else
5920 #endif // RTMP_MAC_PCI //
5921         {
5922                 sprintf((char *)str, "%d", value);
5923                 Set_ATE_TX_COUNT_Proc(pAdapter, str);
5924         }
5925
5926         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5927
5928         return NDIS_STATUS_SUCCESS;
5929 }
5930
5931
5932 static inline INT DO_RACFG_CMD_ATE_START_RX_FRAME(
5933         IN      PRTMP_ADAPTER   pAdapter,
5934         IN      struct iwreq    *wrq,
5935         IN  struct ate_racfghdr *pRaCfg)
5936 {
5937         ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n"));
5938
5939         Set_ATE_Proc(pAdapter, "RXFRAME");
5940
5941         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5942
5943         return NDIS_STATUS_SUCCESS;
5944 }
5945
5946
5947 static inline INT DO_RACFG_CMD_ATE_E2PROM_READ_BULK(
5948         IN      PRTMP_ADAPTER   pAdapter,
5949         IN      struct iwreq    *wrq,
5950         IN  struct ate_racfghdr *pRaCfg)
5951 {
5952         USHORT offset;
5953         USHORT len;
5954         USHORT buffer[EEPROM_SIZE/2];
5955
5956         offset = ntohs(pRaCfg->status);
5957         memcpy(&len, pRaCfg->data, 2);
5958         len = ntohs(len);
5959
5960         rt_ee_read_all(pAdapter, (USHORT *)buffer);
5961
5962         if (offset + len <= EEPROM_SIZE)
5963                 memcpy_exs(pAdapter, pRaCfg->data, (UCHAR *)buffer+offset, len);
5964         else
5965                 ATEDBGPRINT(RT_DEBUG_ERROR, ("exceed EEPROM size\n"));
5966
5967         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+len, NDIS_STATUS_SUCCESS);
5968
5969         return NDIS_STATUS_SUCCESS;
5970 }
5971
5972
5973 static inline INT DO_RACFG_CMD_ATE_E2PROM_WRITE_BULK(
5974         IN      PRTMP_ADAPTER   pAdapter,
5975         IN      struct iwreq    *wrq,
5976         IN  struct ate_racfghdr *pRaCfg)
5977 {
5978         USHORT offset;
5979         USHORT len;
5980         USHORT buffer[EEPROM_SIZE/2];
5981
5982         offset = ntohs(pRaCfg->status);
5983         memcpy(&len, pRaCfg->data, 2);
5984         len = ntohs(len);
5985
5986         rt_ee_read_all(pAdapter,(USHORT *)buffer);
5987         memcpy_exs(pAdapter, (UCHAR *)buffer + offset, (UCHAR *)pRaCfg->data + 2, len);
5988         rt_ee_write_all(pAdapter,(USHORT *)buffer);
5989
5990         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
5991
5992         return NDIS_STATUS_SUCCESS;
5993 }
5994
5995
5996 static inline INT DO_RACFG_CMD_ATE_IO_WRITE_BULK(
5997         IN      PRTMP_ADAPTER   pAdapter,
5998         IN      struct iwreq    *wrq,
5999         IN  struct ate_racfghdr *pRaCfg)
6000 {
6001         UINT32 offset, i, value;
6002         USHORT len;
6003
6004         memcpy(&offset, &pRaCfg->status, 4);
6005         offset = ntohl(offset);
6006         memcpy(&len, pRaCfg->data+2, 2);
6007         len = ntohs(len);
6008
6009         for (i = 0; i < len; i += 4)
6010         {
6011                 memcpy_exl(pAdapter, (UCHAR *)&value, pRaCfg->data+4+i, 4);
6012                 ATEDBGPRINT(RT_DEBUG_TRACE,("Write %x %x\n", offset + i, value));
6013                 RTMP_IO_WRITE32(pAdapter, ((offset+i) & (0xffff)), value);
6014         }
6015
6016         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
6017
6018         return NDIS_STATUS_SUCCESS;
6019 }
6020
6021
6022 static inline INT DO_RACFG_CMD_ATE_BBP_READ_BULK(
6023         IN      PRTMP_ADAPTER   pAdapter,
6024         IN      struct iwreq    *wrq,
6025         IN  struct ate_racfghdr *pRaCfg)
6026 {
6027         USHORT offset;
6028         USHORT len;
6029         USHORT j;
6030
6031         offset = ntohs(pRaCfg->status);
6032         memcpy(&len, pRaCfg->data, 2);
6033         len = ntohs(len);
6034
6035         for (j = offset; j < (offset+len); j++)
6036         {
6037                 pRaCfg->data[j - offset] = 0;
6038
6039                 if (pAdapter->ate.Mode == ATE_STOP)
6040                 {
6041                         RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j - offset]);
6042                 }
6043                 else
6044                 {
6045                         ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j - offset]);
6046                 }
6047         }
6048
6049         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status)+len, NDIS_STATUS_SUCCESS);
6050
6051         return NDIS_STATUS_SUCCESS;
6052 }
6053
6054
6055 static inline INT DO_RACFG_CMD_ATE_BBP_WRITE_BULK(
6056         IN      PRTMP_ADAPTER   pAdapter,
6057         IN      struct iwreq    *wrq,
6058         IN  struct ate_racfghdr *pRaCfg)
6059 {
6060         USHORT offset;
6061         USHORT len;
6062         USHORT j;
6063         UCHAR *value;
6064
6065         offset = ntohs(pRaCfg->status);
6066         memcpy(&len, pRaCfg->data, 2);
6067         len = ntohs(len);
6068
6069         for (j = offset; j < (offset+len); j++)
6070         {
6071                 value = pRaCfg->data + 2 + (j - offset);
6072                 if (pAdapter->ate.Mode == ATE_STOP)
6073                 {
6074                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, j,  *value);
6075                 }
6076                 else
6077                 {
6078                         ATE_BBP_IO_WRITE8_BY_REG_ID(pAdapter, j,  *value);
6079                 }
6080         }
6081
6082         RESPONSE_TO_GUI(pRaCfg, wrq, sizeof(pRaCfg->status), NDIS_STATUS_SUCCESS);
6083
6084         return NDIS_STATUS_SUCCESS;
6085 }
6086
6087
6088 #endif // RALINK_28xx_QA //
6089 #endif  // RALINK_ATE //