2 *************************************************************************
4 * 5F., No.36, Taiyuan St., Jhubei City,
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 *************************************************************************
31 Ralink Wireless Chip related definition & structures
35 -------- ---------- ----------------------------------------------
38 #ifndef __RTMP_CHIP_H__
39 #define __RTMP_CHIP_H__
41 #include "rtmp_type.h"
44 #include "chip/rt2860.h"
47 #include "chip/rt2870.h"
50 #include "chip/rt3070.h"
53 #include "chip/rt3090.h"
56 // We will have a cost down version which mac version is 0x3090xxxx
61 // b) Replacement for RT3090
63 // d) Interference over channel #14
64 // e) New BBP features (e.g., SIG re-modulation)
66 #define IS_RT3090A(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))
68 // We will have a cost down version which mac version is 0x3090xxxx
69 #define IS_RT3090(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) || (IS_RT3090A(_pAd)))
71 #define IS_RT3070(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
72 #define IS_RT3071(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
73 #define IS_RT2070(_pAd) (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27))
75 #define IS_RT30xx(_pAd) (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd))
76 //#define IS_RT305X(_pAd) ((_pAd)->MACVersion == 0x28720200)
78 /* RT3572, 3592, 3562, 3062 share the same MAC version */
79 #define IS_RT3572(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
80 #define IS_VERSION_BEFORE_F(_pAd) (((_pAd)->MACVersion&0xffff) <= 0x0211)
81 // F version is 0x0212, E version is 0x0211. 309x can save more power after F version.
82 #define IS_VERSION_AFTER_F(_pAd) ((((_pAd)->MACVersion&0xffff) >= 0x0212) || (((_pAd)->b3090ESpecialChip == TRUE)))
86 // a) Base on RT3090 (RF IC: RT3020)
90 // e) Internal components: PA and LNA
93 #define IS_RT3390(_pAd) (((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)
95 // ------------------------------------------------------
96 // PCI registers - base address 0x0000
97 // ------------------------------------------------------
98 #define CHIP_PCI_CFG 0x0000
99 #define CHIP_PCI_EECTRL 0x0004
100 #define CHIP_PCI_MCUCTRL 0x0008
104 #define RETRY_LIMIT 10
108 // ------------------------------------------------------
109 // BBP & RF definition
110 // ------------------------------------------------------
115 //-------------------------------------------------------------------------
117 //-------------------------------------------------------------------------
124 #define EEPROM_WRITE_OPCODE 0x05
125 #define EEPROM_READ_OPCODE 0x06
126 #define EEPROM_EWDS_OPCODE 0x10
127 #define EEPROM_EWEN_OPCODE 0x13
129 #define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
130 #define NUM_EEPROM_TX_G_PARMS 7
131 #define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID
132 #define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID
133 #define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID
134 #define EEPROM_G_TX_PWR_OFFSET 0x52
135 #define EEPROM_G_TX2_PWR_OFFSET 0x60
136 #define EEPROM_LED1_OFFSET 0x3c
137 #define EEPROM_LED2_OFFSET 0x3e
138 #define EEPROM_LED3_OFFSET 0x40
139 #define EEPROM_LNA_OFFSET 0x44
140 #define EEPROM_RSSI_BG_OFFSET 0x46
141 #define EEPROM_TXMIXER_GAIN_2_4G 0x48
142 #define EEPROM_RSSI_A_OFFSET 0x4a
143 #define EEPROM_TXMIXER_GAIN_5G 0x4c
144 #define EEPROM_DEFINE_MAX_TXPWR 0x4e
145 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde // 20MHZ 2.4G tx power.
146 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee // 40MHZ 2.4G tx power.
147 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa // 20MHZ 5G tx power.
148 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a // 40MHZ 5G tx power.
149 #define EEPROM_A_TX_PWR_OFFSET 0x78
150 #define EEPROM_A_TX2_PWR_OFFSET 0xa6
151 //#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j
152 //#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe
153 //#define EEPROM_TSSI_REF_OFFSET 0x54
154 //#define EEPROM_TSSI_DELTA_OFFSET 0x24
155 //#define EEPROM_CCK_TX_PWR_OFFSET 0x62
156 //#define EEPROM_CALIBRATE_OFFSET 0x7c
157 #define EEPROM_VERSION_OFFSET 0x02
158 #define EEPROM_FREQ_OFFSET 0x3a
159 #define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power.
160 #define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
161 #define VALID_EEPROM_VERSION 1
165 * EEPROM operation related marcos
167 #define RT28xx_EEPROM_READ16(_pAd, _offset, _value) \
168 (_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value))
170 #define RT28xx_EEPROM_WRITE16(_pAd, _offset, _value) \
171 (_pAd)->chipOps.eewrite((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (USHORT)(_value))
175 // -------------------------------------------------------------------
176 // E2PROM data layout
177 // -------------------------------------------------------------------
180 // MCU_LEDCS: MCU LED Control Setting.
182 typedef union _MCU_LEDCS_STRUC {
188 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
192 // EEPROM antenna select format
194 typedef union _EEPROM_ANTENNA_STRUC {
196 USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
197 USHORT TxPath:4; // 1: 1T, 2: 2T
198 USHORT RfIcType:4; // see E2PROM document
202 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
204 typedef union _EEPROM_NIC_CINFIG2_STRUC {
206 USHORT HardwareRadioControl:1; // 1:enable, 0:disable
207 USHORT DynamicTxAgcControl:1; //
208 USHORT ExternalLNAForG:1; //
209 USHORT ExternalLNAForA:1; // external LNA enable for 2.4G
210 USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
211 USHORT BW40MSidebandForG:1;
212 USHORT BW40MSidebandForA:1;
213 USHORT EnableWPSPBC:1; // WPS PBC Control bit
214 USHORT BW40MAvailForG:1; // 0:enable, 1:disable
215 USHORT BW40MAvailForA:1; // 0:enable, 1:disable
216 USHORT Rsv1:1; // must be 0
217 USHORT AntDiversity:1; // Antenna diversity
218 USHORT Rsv2:3; // must be 0
219 USHORT DACTestBit:1; // control if driver should patch the DAC issue
222 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
225 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
227 typedef union _EEPROM_TX_PWR_STRUC {
229 CHAR Byte0; // Low Byte
230 CHAR Byte1; // High Byte
233 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
235 typedef union _EEPROM_VERSION_STRUC {
237 UCHAR FaeReleaseNumber; // Low Byte
238 UCHAR Version; // High Byte
241 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
243 typedef union _EEPROM_LED_STRUC {
245 USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
246 USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
247 USHORT PolarityACT:1; // Polarity ACT setting.
248 USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
249 USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
250 USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
251 USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
252 USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
253 USHORT LedMode:5; // Led mode.
254 USHORT Rsvd:3; // Reserved
257 } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
259 typedef union _EEPROM_TXPOWER_DELTA_STRUC {
261 UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
262 UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
263 UCHAR TxPowerEnable:1;// Enable
266 } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
268 #endif // __RTMP_CHIP_H__ //