2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * A note about mapbase / membase
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/ratelimit.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_reg.h>
37 #include <linux/serial_core.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/nmi.h>
41 #include <linux/mutex.h>
42 #include <linux/slab.h>
55 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
56 * is unsafe when used on edge-triggered interrupts.
58 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
60 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
62 static struct uart_driver serial8250_reg;
64 static int serial_index(struct uart_port *port)
66 return (serial8250_reg.minor - 64) + port->line;
69 static unsigned int skip_txen_test; /* force skip of txen test at init time */
75 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
77 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
81 #define DEBUG_INTR(fmt...) printk(fmt)
83 #define DEBUG_INTR(fmt...) do { } while (0)
86 #define PASS_LIMIT 256
88 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
92 * We default to IRQ0 for the "no irq" hack. Some
93 * machine types want others as well - they're free
94 * to redefine this in their header file.
96 #define is_real_interrupt(irq) ((irq) != 0)
98 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
99 #define CONFIG_SERIAL_DETECT_IRQ 1
101 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
102 #define CONFIG_SERIAL_MANY_PORTS 1
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
109 #define CONFIG_HUB6 1
111 #include <asm/serial.h>
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
117 #ifndef SERIAL_PORT_DFNS
118 #define SERIAL_PORT_DFNS
121 static const struct old_serial_port old_serial_port[] = {
122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
125 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
127 #ifdef CONFIG_SERIAL_8250_RSA
129 #define PORT_RSA_MAX 4
130 static unsigned long probe_rsa[PORT_RSA_MAX];
131 static unsigned int probe_rsa_count;
132 #endif /* CONFIG_SERIAL_8250_RSA */
134 struct uart_8250_port {
135 struct uart_port port;
136 struct timer_list timer; /* "no irq" timer */
137 struct list_head list; /* ports on this IRQ */
138 unsigned short capabilities; /* port capabilities */
139 unsigned short bugs; /* port bugs */
140 unsigned int tx_loadsz; /* transmit fifo load size */
145 unsigned char mcr_mask; /* mask of user bits */
146 unsigned char mcr_force; /* mask of forced bits */
147 unsigned char cur_iotype; /* Running I/O type */
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read but the bits will not
152 * be immediately processed.
154 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
155 unsigned char lsr_saved_flags;
156 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
157 unsigned char msr_saved_flags;
161 struct hlist_node node;
163 spinlock_t lock; /* Protects list not the hash */
164 struct list_head *head;
167 #define NR_IRQ_HASH 32 /* Can be adjusted later */
168 static struct hlist_head irq_lists[NR_IRQ_HASH];
169 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
172 * Here we define the default xmit fifo size used for each type of UART.
174 static const struct serial8250_config uart_config[] = {
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO,
211 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
227 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
235 .name = "16C950/954",
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
247 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
261 .flags = UART_CAP_FIFO,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_NATSEMI,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
275 .flags = UART_CAP_FIFO | UART_CAP_UUE,
281 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
282 .flags = UART_CAP_FIFO,
288 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
289 .flags = UART_CAP_FIFO,
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
296 .flags = UART_CAP_FIFO | UART_CAP_AFE,
302 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
303 .flags = UART_CAP_FIFO | UART_CAP_AFE,
307 #if defined(CONFIG_MIPS_ALCHEMY)
309 /* Au1x00 UART hardware has a weird register layout */
310 static const u8 au_io_in_map[] = {
320 static const u8 au_io_out_map[] = {
328 /* sane hardware needs no mapping */
329 static inline int map_8250_in_reg(struct uart_port *p, int offset)
331 if (p->iotype != UPIO_AU)
333 return au_io_in_map[offset];
336 static inline int map_8250_out_reg(struct uart_port *p, int offset)
338 if (p->iotype != UPIO_AU)
340 return au_io_out_map[offset];
343 #elif defined(CONFIG_SERIAL_8250_RM9K)
367 static inline int map_8250_in_reg(struct uart_port *p, int offset)
369 if (p->iotype != UPIO_RM9000)
371 return regmap_in[offset];
374 static inline int map_8250_out_reg(struct uart_port *p, int offset)
376 if (p->iotype != UPIO_RM9000)
378 return regmap_out[offset];
383 /* sane hardware needs no mapping */
384 #define map_8250_in_reg(up, offset) (offset)
385 #define map_8250_out_reg(up, offset) (offset)
389 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
391 offset = map_8250_in_reg(p, offset) << p->regshift;
392 outb(p->hub6 - 1 + offset, p->iobase);
393 return inb(p->iobase + 1);
396 static void hub6_serial_out(struct uart_port *p, int offset, int value)
398 offset = map_8250_out_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 outb(value, p->iobase + 1);
403 static unsigned int mem_serial_in(struct uart_port *p, int offset)
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 return readb(p->membase + offset);
409 static void mem_serial_out(struct uart_port *p, int offset, int value)
411 offset = map_8250_out_reg(p, offset) << p->regshift;
412 writeb(value, p->membase + offset);
415 static void mem32_serial_out(struct uart_port *p, int offset, int value)
417 offset = map_8250_out_reg(p, offset) << p->regshift;
418 writel(value, p->membase + offset);
421 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
423 offset = map_8250_in_reg(p, offset) << p->regshift;
424 return readl(p->membase + offset);
427 static unsigned int au_serial_in(struct uart_port *p, int offset)
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return __raw_readl(p->membase + offset);
433 static void au_serial_out(struct uart_port *p, int offset, int value)
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 __raw_writel(value, p->membase + offset);
439 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
442 offset = map_8250_in_reg(p, offset) << p->regshift;
443 if (offset == UART_IIR) {
444 tmp = readl(p->membase + (UART_IIR & ~3));
445 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
447 return readb(p->membase + offset);
450 static void tsi_serial_out(struct uart_port *p, int offset, int value)
452 offset = map_8250_out_reg(p, offset) << p->regshift;
453 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
454 writeb(value, p->membase + offset);
457 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
459 int save_offset = offset;
460 offset = map_8250_out_reg(p, offset) << p->regshift;
461 /* Save the LCR value so it can be re-written when a
462 * Busy Detect interrupt occurs. */
463 if (save_offset == UART_LCR) {
464 struct uart_8250_port *up = (struct uart_8250_port *)p;
467 writeb(value, p->membase + offset);
468 /* Read the IER to ensure any interrupt is cleared before
469 * returning from ISR. */
470 if (save_offset == UART_TX || save_offset == UART_IER)
471 value = p->serial_in(p, UART_IER);
474 static unsigned int io_serial_in(struct uart_port *p, int offset)
476 offset = map_8250_in_reg(p, offset) << p->regshift;
477 return inb(p->iobase + offset);
480 static void io_serial_out(struct uart_port *p, int offset, int value)
482 offset = map_8250_out_reg(p, offset) << p->regshift;
483 outb(value, p->iobase + offset);
486 static void set_io_from_upio(struct uart_port *p)
488 struct uart_8250_port *up = (struct uart_8250_port *)p;
491 p->serial_in = hub6_serial_in;
492 p->serial_out = hub6_serial_out;
496 p->serial_in = mem_serial_in;
497 p->serial_out = mem_serial_out;
502 p->serial_in = mem32_serial_in;
503 p->serial_out = mem32_serial_out;
507 p->serial_in = au_serial_in;
508 p->serial_out = au_serial_out;
512 p->serial_in = tsi_serial_in;
513 p->serial_out = tsi_serial_out;
517 p->serial_in = mem_serial_in;
518 p->serial_out = dwapb_serial_out;
522 p->serial_in = io_serial_in;
523 p->serial_out = io_serial_out;
526 /* Remember loaded iotype */
527 up->cur_iotype = p->iotype;
531 serial_out_sync(struct uart_8250_port *up, int offset, int value)
533 struct uart_port *p = &up->port;
539 p->serial_out(p, offset, value);
540 p->serial_in(p, UART_LCR); /* safe, no side-effects */
543 p->serial_out(p, offset, value);
547 #define serial_in(up, offset) \
548 (up->port.serial_in(&(up)->port, (offset)))
549 #define serial_out(up, offset, value) \
550 (up->port.serial_out(&(up)->port, (offset), (value)))
552 * We used to support using pause I/O for certain machines. We
553 * haven't supported this for a while, but just in case it's badly
554 * needed for certain old 386 machines, I've left these #define's
557 #define serial_inp(up, offset) serial_in(up, offset)
558 #define serial_outp(up, offset, value) serial_out(up, offset, value)
560 /* Uart divisor latch read */
561 static inline int _serial_dl_read(struct uart_8250_port *up)
563 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
566 /* Uart divisor latch write */
567 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
569 serial_outp(up, UART_DLL, value & 0xff);
570 serial_outp(up, UART_DLM, value >> 8 & 0xff);
573 #if defined(CONFIG_MIPS_ALCHEMY)
574 /* Au1x00 haven't got a standard divisor latch */
575 static int serial_dl_read(struct uart_8250_port *up)
577 if (up->port.iotype == UPIO_AU)
578 return __raw_readl(up->port.membase + 0x28);
580 return _serial_dl_read(up);
583 static void serial_dl_write(struct uart_8250_port *up, int value)
585 if (up->port.iotype == UPIO_AU)
586 __raw_writel(value, up->port.membase + 0x28);
588 _serial_dl_write(up, value);
590 #elif defined(CONFIG_SERIAL_8250_RM9K)
591 static int serial_dl_read(struct uart_8250_port *up)
593 return (up->port.iotype == UPIO_RM9000) ?
594 (((__raw_readl(up->port.membase + 0x10) << 8) |
595 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
599 static void serial_dl_write(struct uart_8250_port *up, int value)
601 if (up->port.iotype == UPIO_RM9000) {
602 __raw_writel(value, up->port.membase + 0x08);
603 __raw_writel(value >> 8, up->port.membase + 0x10);
605 _serial_dl_write(up, value);
609 #define serial_dl_read(up) _serial_dl_read(up)
610 #define serial_dl_write(up, value) _serial_dl_write(up, value)
616 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
618 serial_out(up, UART_SCR, offset);
619 serial_out(up, UART_ICR, value);
622 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
626 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
627 serial_out(up, UART_SCR, offset);
628 value = serial_in(up, UART_ICR);
629 serial_icr_write(up, UART_ACR, up->acr);
637 static void serial8250_clear_fifos(struct uart_8250_port *p)
639 if (p->capabilities & UART_CAP_FIFO) {
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
641 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
642 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
643 serial_outp(p, UART_FCR, 0);
648 * IER sleep support. UARTs which have EFRs need the "extended
649 * capability" bit enabled. Note that on XR16C850s, we need to
650 * reset LCR to write to IER.
652 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
654 if (p->capabilities & UART_CAP_SLEEP) {
655 if (p->capabilities & UART_CAP_EFR) {
656 serial_outp(p, UART_LCR, 0xBF);
657 serial_outp(p, UART_EFR, UART_EFR_ECB);
658 serial_outp(p, UART_LCR, 0);
660 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
661 if (p->capabilities & UART_CAP_EFR) {
662 serial_outp(p, UART_LCR, 0xBF);
663 serial_outp(p, UART_EFR, 0);
664 serial_outp(p, UART_LCR, 0);
669 #ifdef CONFIG_SERIAL_8250_RSA
671 * Attempts to turn on the RSA FIFO. Returns zero on failure.
672 * We set the port uart clock rate if we succeed.
674 static int __enable_rsa(struct uart_8250_port *up)
679 mode = serial_inp(up, UART_RSA_MSR);
680 result = mode & UART_RSA_MSR_FIFO;
683 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
684 mode = serial_inp(up, UART_RSA_MSR);
685 result = mode & UART_RSA_MSR_FIFO;
689 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
694 static void enable_rsa(struct uart_8250_port *up)
696 if (up->port.type == PORT_RSA) {
697 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
698 spin_lock_irq(&up->port.lock);
700 spin_unlock_irq(&up->port.lock);
702 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
703 serial_outp(up, UART_RSA_FRR, 0);
708 * Attempts to turn off the RSA FIFO. Returns zero on failure.
709 * It is unknown why interrupts were disabled in here. However,
710 * the caller is expected to preserve this behaviour by grabbing
711 * the spinlock before calling this function.
713 static void disable_rsa(struct uart_8250_port *up)
718 if (up->port.type == PORT_RSA &&
719 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
720 spin_lock_irq(&up->port.lock);
722 mode = serial_inp(up, UART_RSA_MSR);
723 result = !(mode & UART_RSA_MSR_FIFO);
726 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
727 mode = serial_inp(up, UART_RSA_MSR);
728 result = !(mode & UART_RSA_MSR_FIFO);
732 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
733 spin_unlock_irq(&up->port.lock);
736 #endif /* CONFIG_SERIAL_8250_RSA */
739 * This is a quickie test to see how big the FIFO is.
740 * It doesn't work at all the time, more's the pity.
742 static int size_fifo(struct uart_8250_port *up)
744 unsigned char old_fcr, old_mcr, old_lcr;
745 unsigned short old_dl;
748 old_lcr = serial_inp(up, UART_LCR);
749 serial_outp(up, UART_LCR, 0);
750 old_fcr = serial_inp(up, UART_FCR);
751 old_mcr = serial_inp(up, UART_MCR);
752 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
753 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
754 serial_outp(up, UART_MCR, UART_MCR_LOOP);
755 serial_outp(up, UART_LCR, UART_LCR_DLAB);
756 old_dl = serial_dl_read(up);
757 serial_dl_write(up, 0x0001);
758 serial_outp(up, UART_LCR, 0x03);
759 for (count = 0; count < 256; count++)
760 serial_outp(up, UART_TX, count);
761 mdelay(20);/* FIXME - schedule_timeout */
762 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
763 (count < 256); count++)
764 serial_inp(up, UART_RX);
765 serial_outp(up, UART_FCR, old_fcr);
766 serial_outp(up, UART_MCR, old_mcr);
767 serial_outp(up, UART_LCR, UART_LCR_DLAB);
768 serial_dl_write(up, old_dl);
769 serial_outp(up, UART_LCR, old_lcr);
775 * Read UART ID using the divisor method - set DLL and DLM to zero
776 * and the revision will be in DLL and device type in DLM. We
777 * preserve the device state across this.
779 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
781 unsigned char old_dll, old_dlm, old_lcr;
784 old_lcr = serial_inp(p, UART_LCR);
785 serial_outp(p, UART_LCR, UART_LCR_DLAB);
787 old_dll = serial_inp(p, UART_DLL);
788 old_dlm = serial_inp(p, UART_DLM);
790 serial_outp(p, UART_DLL, 0);
791 serial_outp(p, UART_DLM, 0);
793 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
795 serial_outp(p, UART_DLL, old_dll);
796 serial_outp(p, UART_DLM, old_dlm);
797 serial_outp(p, UART_LCR, old_lcr);
803 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
804 * When this function is called we know it is at least a StarTech
805 * 16650 V2, but it might be one of several StarTech UARTs, or one of
806 * its clones. (We treat the broken original StarTech 16650 V1 as a
807 * 16550, and why not? Startech doesn't seem to even acknowledge its
810 * What evil have men's minds wrought...
812 static void autoconfig_has_efr(struct uart_8250_port *up)
814 unsigned int id1, id2, id3, rev;
817 * Everything with an EFR has SLEEP
819 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
822 * First we check to see if it's an Oxford Semiconductor UART.
824 * If we have to do this here because some non-National
825 * Semiconductor clone chips lock up if you try writing to the
826 * LSR register (which serial_icr_read does)
830 * Check for Oxford Semiconductor 16C950.
832 * EFR [4] must be set else this test fails.
834 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
835 * claims that it's needed for 952 dual UART's (which are not
836 * recommended for new designs).
839 serial_out(up, UART_LCR, 0xBF);
840 serial_out(up, UART_EFR, UART_EFR_ECB);
841 serial_out(up, UART_LCR, 0x00);
842 id1 = serial_icr_read(up, UART_ID1);
843 id2 = serial_icr_read(up, UART_ID2);
844 id3 = serial_icr_read(up, UART_ID3);
845 rev = serial_icr_read(up, UART_REV);
847 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
849 if (id1 == 0x16 && id2 == 0xC9 &&
850 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
851 up->port.type = PORT_16C950;
854 * Enable work around for the Oxford Semiconductor 952 rev B
855 * chip which causes it to seriously miscalculate baud rates
858 if (id3 == 0x52 && rev == 0x01)
859 up->bugs |= UART_BUG_QUOT;
864 * We check for a XR16C850 by setting DLL and DLM to 0, and then
865 * reading back DLL and DLM. The chip type depends on the DLM
867 * 0x10 - XR16C850 and the DLL contains the chip revision.
871 id1 = autoconfig_read_divisor_id(up);
872 DEBUG_AUTOCONF("850id=%04x ", id1);
875 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
876 up->port.type = PORT_16850;
881 * It wasn't an XR16C850.
883 * We distinguish between the '654 and the '650 by counting
884 * how many bytes are in the FIFO. I'm using this for now,
885 * since that's the technique that was sent to me in the
886 * serial driver update, but I'm not convinced this works.
887 * I've had problems doing this in the past. -TYT
889 if (size_fifo(up) == 64)
890 up->port.type = PORT_16654;
892 up->port.type = PORT_16650V2;
896 * We detected a chip without a FIFO. Only two fall into
897 * this category - the original 8250 and the 16450. The
898 * 16450 has a scratch register (accessible with LCR=0)
900 static void autoconfig_8250(struct uart_8250_port *up)
902 unsigned char scratch, status1, status2;
904 up->port.type = PORT_8250;
906 scratch = serial_in(up, UART_SCR);
907 serial_outp(up, UART_SCR, 0xa5);
908 status1 = serial_in(up, UART_SCR);
909 serial_outp(up, UART_SCR, 0x5a);
910 status2 = serial_in(up, UART_SCR);
911 serial_outp(up, UART_SCR, scratch);
913 if (status1 == 0xa5 && status2 == 0x5a)
914 up->port.type = PORT_16450;
917 static int broken_efr(struct uart_8250_port *up)
920 * Exar ST16C2550 "A2" devices incorrectly detect as
921 * having an EFR, and report an ID of 0x0201. See
922 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
924 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
931 * We know that the chip has FIFOs. Does it have an EFR? The
932 * EFR is located in the same register position as the IIR and
933 * we know the top two bits of the IIR are currently set. The
934 * EFR should contain zero. Try to read the EFR.
936 static void autoconfig_16550a(struct uart_8250_port *up)
938 unsigned char status1, status2;
939 unsigned int iersave;
941 up->port.type = PORT_16550A;
942 up->capabilities |= UART_CAP_FIFO;
945 * Check for presence of the EFR when DLAB is set.
946 * Only ST16C650V1 UARTs pass this test.
948 serial_outp(up, UART_LCR, UART_LCR_DLAB);
949 if (serial_in(up, UART_EFR) == 0) {
950 serial_outp(up, UART_EFR, 0xA8);
951 if (serial_in(up, UART_EFR) != 0) {
952 DEBUG_AUTOCONF("EFRv1 ");
953 up->port.type = PORT_16650;
954 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
956 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
958 serial_outp(up, UART_EFR, 0);
963 * Maybe it requires 0xbf to be written to the LCR.
964 * (other ST16C650V2 UARTs, TI16C752A, etc)
966 serial_outp(up, UART_LCR, 0xBF);
967 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
968 DEBUG_AUTOCONF("EFRv2 ");
969 autoconfig_has_efr(up);
974 * Check for a National Semiconductor SuperIO chip.
975 * Attempt to switch to bank 2, read the value of the LOOP bit
976 * from EXCR1. Switch back to bank 0, change it in MCR. Then
977 * switch back to bank 2, read it from EXCR1 again and check
978 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
980 serial_outp(up, UART_LCR, 0);
981 status1 = serial_in(up, UART_MCR);
982 serial_outp(up, UART_LCR, 0xE0);
983 status2 = serial_in(up, 0x02); /* EXCR1 */
985 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
986 serial_outp(up, UART_LCR, 0);
987 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
988 serial_outp(up, UART_LCR, 0xE0);
989 status2 = serial_in(up, 0x02); /* EXCR1 */
990 serial_outp(up, UART_LCR, 0);
991 serial_outp(up, UART_MCR, status1);
993 if ((status2 ^ status1) & UART_MCR_LOOP) {
996 serial_outp(up, UART_LCR, 0xE0);
998 quot = serial_dl_read(up);
1001 status1 = serial_in(up, 0x04); /* EXCR2 */
1002 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1003 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1004 serial_outp(up, 0x04, status1);
1006 serial_dl_write(up, quot);
1008 serial_outp(up, UART_LCR, 0);
1010 up->port.uartclk = 921600*16;
1011 up->port.type = PORT_NS16550A;
1012 up->capabilities |= UART_NATSEMI;
1018 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1019 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1020 * Try setting it with and without DLAB set. Cheap clones
1021 * set bit 5 without DLAB set.
1023 serial_outp(up, UART_LCR, 0);
1024 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1025 status1 = serial_in(up, UART_IIR) >> 5;
1026 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1027 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1028 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1029 status2 = serial_in(up, UART_IIR) >> 5;
1030 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1031 serial_outp(up, UART_LCR, 0);
1033 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1035 if (status1 == 6 && status2 == 7) {
1036 up->port.type = PORT_16750;
1037 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1042 * Try writing and reading the UART_IER_UUE bit (b6).
1043 * If it works, this is probably one of the Xscale platform's
1045 * We're going to explicitly set the UUE bit to 0 before
1046 * trying to write and read a 1 just to make sure it's not
1047 * already a 1 and maybe locked there before we even start start.
1049 iersave = serial_in(up, UART_IER);
1050 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1051 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1053 * OK it's in a known zero state, try writing and reading
1054 * without disturbing the current state of the other bits.
1056 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1057 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1060 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1062 DEBUG_AUTOCONF("Xscale ");
1063 up->port.type = PORT_XSCALE;
1064 up->capabilities |= UART_CAP_UUE;
1069 * If we got here we couldn't force the IER_UUE bit to 0.
1070 * Log it and continue.
1072 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1074 serial_outp(up, UART_IER, iersave);
1077 * We distinguish between 16550A and U6 16550A by counting
1078 * how many bytes are in the FIFO.
1080 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1081 up->port.type = PORT_U6_16550A;
1082 up->capabilities |= UART_CAP_AFE;
1087 * This routine is called by rs_init() to initialize a specific serial
1088 * port. It determines what type of UART chip this serial port is
1089 * using: 8250, 16450, 16550, 16550A. The important question is
1090 * whether or not this UART is a 16550A or not, since this will
1091 * determine whether or not we can use its FIFO features or not.
1093 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1095 unsigned char status1, scratch, scratch2, scratch3;
1096 unsigned char save_lcr, save_mcr;
1097 unsigned long flags;
1099 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1102 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1103 serial_index(&up->port), up->port.iobase, up->port.membase);
1106 * We really do need global IRQs disabled here - we're going to
1107 * be frobbing the chips IRQ enable register to see if it exists.
1109 spin_lock_irqsave(&up->port.lock, flags);
1111 up->capabilities = 0;
1114 if (!(up->port.flags & UPF_BUGGY_UART)) {
1116 * Do a simple existence test first; if we fail this,
1117 * there's no point trying anything else.
1119 * 0x80 is used as a nonsense port to prevent against
1120 * false positives due to ISA bus float. The
1121 * assumption is that 0x80 is a non-existent port;
1122 * which should be safe since include/asm/io.h also
1123 * makes this assumption.
1125 * Note: this is safe as long as MCR bit 4 is clear
1126 * and the device is in "PC" mode.
1128 scratch = serial_inp(up, UART_IER);
1129 serial_outp(up, UART_IER, 0);
1134 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1135 * 16C754B) allow only to modify them if an EFR bit is set.
1137 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1138 serial_outp(up, UART_IER, 0x0F);
1142 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1143 serial_outp(up, UART_IER, scratch);
1144 if (scratch2 != 0 || scratch3 != 0x0F) {
1146 * We failed; there's nothing here
1148 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1149 scratch2, scratch3);
1154 save_mcr = serial_in(up, UART_MCR);
1155 save_lcr = serial_in(up, UART_LCR);
1158 * Check to see if a UART is really there. Certain broken
1159 * internal modems based on the Rockwell chipset fail this
1160 * test, because they apparently don't implement the loopback
1161 * test mode. So this test is skipped on the COM 1 through
1162 * COM 4 ports. This *should* be safe, since no board
1163 * manufacturer would be stupid enough to design a board
1164 * that conflicts with COM 1-4 --- we hope!
1166 if (!(up->port.flags & UPF_SKIP_TEST)) {
1167 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1168 status1 = serial_inp(up, UART_MSR) & 0xF0;
1169 serial_outp(up, UART_MCR, save_mcr);
1170 if (status1 != 0x90) {
1171 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1178 * We're pretty sure there's a port here. Lets find out what
1179 * type of port it is. The IIR top two bits allows us to find
1180 * out if it's 8250 or 16450, 16550, 16550A or later. This
1181 * determines what we test for next.
1183 * We also initialise the EFR (if any) to zero for later. The
1184 * EFR occupies the same register location as the FCR and IIR.
1186 serial_outp(up, UART_LCR, 0xBF);
1187 serial_outp(up, UART_EFR, 0);
1188 serial_outp(up, UART_LCR, 0);
1190 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1191 scratch = serial_in(up, UART_IIR) >> 6;
1193 DEBUG_AUTOCONF("iir=%d ", scratch);
1197 autoconfig_8250(up);
1200 up->port.type = PORT_UNKNOWN;
1203 up->port.type = PORT_16550;
1206 autoconfig_16550a(up);
1210 #ifdef CONFIG_SERIAL_8250_RSA
1212 * Only probe for RSA ports if we got the region.
1214 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1217 for (i = 0 ; i < probe_rsa_count; ++i) {
1218 if (probe_rsa[i] == up->port.iobase &&
1220 up->port.type = PORT_RSA;
1227 serial_outp(up, UART_LCR, save_lcr);
1229 if (up->capabilities != uart_config[up->port.type].flags) {
1231 "ttyS%d: detected caps %08x should be %08x\n",
1232 serial_index(&up->port), up->capabilities,
1233 uart_config[up->port.type].flags);
1236 up->port.fifosize = uart_config[up->port.type].fifo_size;
1237 up->capabilities = uart_config[up->port.type].flags;
1238 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1240 if (up->port.type == PORT_UNKNOWN)
1246 #ifdef CONFIG_SERIAL_8250_RSA
1247 if (up->port.type == PORT_RSA)
1248 serial_outp(up, UART_RSA_FRR, 0);
1250 serial_outp(up, UART_MCR, save_mcr);
1251 serial8250_clear_fifos(up);
1252 serial_in(up, UART_RX);
1253 if (up->capabilities & UART_CAP_UUE)
1254 serial_outp(up, UART_IER, UART_IER_UUE);
1256 serial_outp(up, UART_IER, 0);
1259 spin_unlock_irqrestore(&up->port.lock, flags);
1260 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1263 static void autoconfig_irq(struct uart_8250_port *up)
1265 unsigned char save_mcr, save_ier;
1266 unsigned char save_ICP = 0;
1267 unsigned int ICP = 0;
1271 if (up->port.flags & UPF_FOURPORT) {
1272 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1273 save_ICP = inb_p(ICP);
1278 /* forget possible initially masked and pending IRQ */
1279 probe_irq_off(probe_irq_on());
1280 save_mcr = serial_inp(up, UART_MCR);
1281 save_ier = serial_inp(up, UART_IER);
1282 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1284 irqs = probe_irq_on();
1285 serial_outp(up, UART_MCR, 0);
1287 if (up->port.flags & UPF_FOURPORT) {
1288 serial_outp(up, UART_MCR,
1289 UART_MCR_DTR | UART_MCR_RTS);
1291 serial_outp(up, UART_MCR,
1292 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1294 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1295 (void)serial_inp(up, UART_LSR);
1296 (void)serial_inp(up, UART_RX);
1297 (void)serial_inp(up, UART_IIR);
1298 (void)serial_inp(up, UART_MSR);
1299 serial_outp(up, UART_TX, 0xFF);
1301 irq = probe_irq_off(irqs);
1303 serial_outp(up, UART_MCR, save_mcr);
1304 serial_outp(up, UART_IER, save_ier);
1306 if (up->port.flags & UPF_FOURPORT)
1307 outb_p(save_ICP, ICP);
1309 up->port.irq = (irq > 0) ? irq : 0;
1312 static inline void __stop_tx(struct uart_8250_port *p)
1314 if (p->ier & UART_IER_THRI) {
1315 p->ier &= ~UART_IER_THRI;
1316 serial_out(p, UART_IER, p->ier);
1320 static void serial8250_stop_tx(struct uart_port *port)
1322 struct uart_8250_port *up = (struct uart_8250_port *)port;
1327 * We really want to stop the transmitter from sending.
1329 if (up->port.type == PORT_16C950) {
1330 up->acr |= UART_ACR_TXDIS;
1331 serial_icr_write(up, UART_ACR, up->acr);
1335 static void transmit_chars(struct uart_8250_port *up);
1337 static void serial8250_start_tx(struct uart_port *port)
1339 struct uart_8250_port *up = (struct uart_8250_port *)port;
1341 if (!(up->ier & UART_IER_THRI)) {
1342 up->ier |= UART_IER_THRI;
1343 serial_out(up, UART_IER, up->ier);
1345 if (up->bugs & UART_BUG_TXEN) {
1347 lsr = serial_in(up, UART_LSR);
1348 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1349 if ((up->port.type == PORT_RM9000) ?
1350 (lsr & UART_LSR_THRE) :
1351 (lsr & UART_LSR_TEMT))
1357 * Re-enable the transmitter if we disabled it.
1359 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1360 up->acr &= ~UART_ACR_TXDIS;
1361 serial_icr_write(up, UART_ACR, up->acr);
1365 static void serial8250_stop_rx(struct uart_port *port)
1367 struct uart_8250_port *up = (struct uart_8250_port *)port;
1369 up->ier &= ~UART_IER_RLSI;
1370 up->port.read_status_mask &= ~UART_LSR_DR;
1371 serial_out(up, UART_IER, up->ier);
1374 static void serial8250_enable_ms(struct uart_port *port)
1376 struct uart_8250_port *up = (struct uart_8250_port *)port;
1378 /* no MSR capabilities */
1379 if (up->bugs & UART_BUG_NOMSR)
1382 up->ier |= UART_IER_MSI;
1383 serial_out(up, UART_IER, up->ier);
1387 receive_chars(struct uart_8250_port *up, unsigned int *status)
1389 struct tty_struct *tty = up->port.state->port.tty;
1390 unsigned char ch, lsr = *status;
1391 int max_count = 256;
1395 if (likely(lsr & UART_LSR_DR))
1396 ch = serial_inp(up, UART_RX);
1399 * Intel 82571 has a Serial Over Lan device that will
1400 * set UART_LSR_BI without setting UART_LSR_DR when
1401 * it receives a break. To avoid reading from the
1402 * receive buffer without UART_LSR_DR bit set, we
1403 * just force the read character to be 0
1408 up->port.icount.rx++;
1410 lsr |= up->lsr_saved_flags;
1411 up->lsr_saved_flags = 0;
1413 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1415 * For statistics only
1417 if (lsr & UART_LSR_BI) {
1418 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1419 up->port.icount.brk++;
1421 * We do the SysRQ and SAK checking
1422 * here because otherwise the break
1423 * may get masked by ignore_status_mask
1424 * or read_status_mask.
1426 if (uart_handle_break(&up->port))
1428 } else if (lsr & UART_LSR_PE)
1429 up->port.icount.parity++;
1430 else if (lsr & UART_LSR_FE)
1431 up->port.icount.frame++;
1432 if (lsr & UART_LSR_OE)
1433 up->port.icount.overrun++;
1436 * Mask off conditions which should be ignored.
1438 lsr &= up->port.read_status_mask;
1440 if (lsr & UART_LSR_BI) {
1441 DEBUG_INTR("handling break....");
1443 } else if (lsr & UART_LSR_PE)
1445 else if (lsr & UART_LSR_FE)
1448 if (uart_handle_sysrq_char(&up->port, ch))
1451 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1454 lsr = serial_inp(up, UART_LSR);
1455 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1456 spin_unlock(&up->port.lock);
1457 tty_flip_buffer_push(tty);
1458 spin_lock(&up->port.lock);
1462 static void transmit_chars(struct uart_8250_port *up)
1464 struct circ_buf *xmit = &up->port.state->xmit;
1467 if (up->port.x_char) {
1468 serial_outp(up, UART_TX, up->port.x_char);
1469 up->port.icount.tx++;
1470 up->port.x_char = 0;
1473 if (uart_tx_stopped(&up->port)) {
1474 serial8250_stop_tx(&up->port);
1477 if (uart_circ_empty(xmit)) {
1482 count = up->tx_loadsz;
1484 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486 up->port.icount.tx++;
1487 if (uart_circ_empty(xmit))
1489 } while (--count > 0);
1491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1492 uart_write_wakeup(&up->port);
1494 DEBUG_INTR("THRE...");
1496 if (uart_circ_empty(xmit))
1500 static unsigned int check_modem_status(struct uart_8250_port *up)
1502 unsigned int status = serial_in(up, UART_MSR);
1504 status |= up->msr_saved_flags;
1505 up->msr_saved_flags = 0;
1506 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1507 up->port.state != NULL) {
1508 if (status & UART_MSR_TERI)
1509 up->port.icount.rng++;
1510 if (status & UART_MSR_DDSR)
1511 up->port.icount.dsr++;
1512 if (status & UART_MSR_DDCD)
1513 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1514 if (status & UART_MSR_DCTS)
1515 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1517 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1524 * This handles the interrupt from one port.
1526 static void serial8250_handle_port(struct uart_8250_port *up)
1528 unsigned int status;
1529 unsigned long flags;
1531 spin_lock_irqsave(&up->port.lock, flags);
1533 status = serial_inp(up, UART_LSR);
1535 DEBUG_INTR("status = %x...", status);
1537 if (status & (UART_LSR_DR | UART_LSR_BI))
1538 receive_chars(up, &status);
1539 check_modem_status(up);
1540 if (status & UART_LSR_THRE)
1543 spin_unlock_irqrestore(&up->port.lock, flags);
1547 * This is the serial driver's interrupt routine.
1549 * Arjan thinks the old way was overly complex, so it got simplified.
1550 * Alan disagrees, saying that need the complexity to handle the weird
1551 * nature of ISA shared interrupts. (This is a special exception.)
1553 * In order to handle ISA shared interrupts properly, we need to check
1554 * that all ports have been serviced, and therefore the ISA interrupt
1555 * line has been de-asserted.
1557 * This means we need to loop through all ports. checking that they
1558 * don't have an interrupt pending.
1560 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1562 struct irq_info *i = dev_id;
1563 struct list_head *l, *end = NULL;
1564 int pass_counter = 0, handled = 0;
1566 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1568 spin_lock(&i->lock);
1572 struct uart_8250_port *up;
1575 up = list_entry(l, struct uart_8250_port, list);
1577 iir = serial_in(up, UART_IIR);
1578 if (!(iir & UART_IIR_NO_INT)) {
1579 serial8250_handle_port(up);
1584 } else if (up->port.iotype == UPIO_DWAPB &&
1585 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1586 /* The DesignWare APB UART has an Busy Detect (0x07)
1587 * interrupt meaning an LCR write attempt occured while the
1588 * UART was busy. The interrupt must be cleared by reading
1589 * the UART status register (USR) and the LCR re-written. */
1590 unsigned int status;
1591 status = *(volatile u32 *)up->port.private_data;
1592 serial_out(up, UART_LCR, up->lcr);
1597 } else if (end == NULL)
1602 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1603 /* If we hit this, we're dead. */
1604 printk_ratelimited(KERN_ERR
1605 "serial8250: too much work for irq%d\n", irq);
1610 spin_unlock(&i->lock);
1612 DEBUG_INTR("end.\n");
1614 return IRQ_RETVAL(handled);
1618 * To support ISA shared interrupts, we need to have one interrupt
1619 * handler that ensures that the IRQ line has been deasserted
1620 * before returning. Failing to do this will result in the IRQ
1621 * line being stuck active, and, since ISA irqs are edge triggered,
1622 * no more IRQs will be seen.
1624 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1626 spin_lock_irq(&i->lock);
1628 if (!list_empty(i->head)) {
1629 if (i->head == &up->list)
1630 i->head = i->head->next;
1631 list_del(&up->list);
1633 BUG_ON(i->head != &up->list);
1636 spin_unlock_irq(&i->lock);
1637 /* List empty so throw away the hash node */
1638 if (i->head == NULL) {
1639 hlist_del(&i->node);
1644 static int serial_link_irq_chain(struct uart_8250_port *up)
1646 struct hlist_head *h;
1647 struct hlist_node *n;
1649 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1651 mutex_lock(&hash_mutex);
1653 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1655 hlist_for_each(n, h) {
1656 i = hlist_entry(n, struct irq_info, node);
1657 if (i->irq == up->port.irq)
1662 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1664 mutex_unlock(&hash_mutex);
1667 spin_lock_init(&i->lock);
1668 i->irq = up->port.irq;
1669 hlist_add_head(&i->node, h);
1671 mutex_unlock(&hash_mutex);
1673 spin_lock_irq(&i->lock);
1676 list_add(&up->list, i->head);
1677 spin_unlock_irq(&i->lock);
1681 INIT_LIST_HEAD(&up->list);
1682 i->head = &up->list;
1683 spin_unlock_irq(&i->lock);
1684 irq_flags |= up->port.irqflags;
1685 ret = request_irq(up->port.irq, serial8250_interrupt,
1686 irq_flags, "serial", i);
1688 serial_do_unlink(i, up);
1694 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1697 struct hlist_node *n;
1698 struct hlist_head *h;
1700 mutex_lock(&hash_mutex);
1702 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1704 hlist_for_each(n, h) {
1705 i = hlist_entry(n, struct irq_info, node);
1706 if (i->irq == up->port.irq)
1711 BUG_ON(i->head == NULL);
1713 if (list_empty(i->head))
1714 free_irq(up->port.irq, i);
1716 serial_do_unlink(i, up);
1717 mutex_unlock(&hash_mutex);
1721 * This function is used to handle ports that do not have an
1722 * interrupt. This doesn't work very well for 16450's, but gives
1723 * barely passable results for a 16550A. (Although at the expense
1724 * of much CPU overhead).
1726 static void serial8250_timeout(unsigned long data)
1728 struct uart_8250_port *up = (struct uart_8250_port *)data;
1731 iir = serial_in(up, UART_IIR);
1732 if (!(iir & UART_IIR_NO_INT))
1733 serial8250_handle_port(up);
1734 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1737 static void serial8250_backup_timeout(unsigned long data)
1739 struct uart_8250_port *up = (struct uart_8250_port *)data;
1740 unsigned int iir, ier = 0, lsr;
1741 unsigned long flags;
1744 * Must disable interrupts or else we risk racing with the interrupt
1747 if (is_real_interrupt(up->port.irq)) {
1748 ier = serial_in(up, UART_IER);
1749 serial_out(up, UART_IER, 0);
1752 iir = serial_in(up, UART_IIR);
1755 * This should be a safe test for anyone who doesn't trust the
1756 * IIR bits on their UART, but it's specifically designed for
1757 * the "Diva" UART used on the management processor on many HP
1758 * ia64 and parisc boxes.
1760 spin_lock_irqsave(&up->port.lock, flags);
1761 lsr = serial_in(up, UART_LSR);
1762 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1763 spin_unlock_irqrestore(&up->port.lock, flags);
1764 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1765 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1766 (lsr & UART_LSR_THRE)) {
1767 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1768 iir |= UART_IIR_THRI;
1771 if (!(iir & UART_IIR_NO_INT))
1772 serial8250_handle_port(up);
1774 if (is_real_interrupt(up->port.irq))
1775 serial_out(up, UART_IER, ier);
1777 /* Standard timer interval plus 0.2s to keep the port running */
1778 mod_timer(&up->timer,
1779 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1782 static unsigned int serial8250_tx_empty(struct uart_port *port)
1784 struct uart_8250_port *up = (struct uart_8250_port *)port;
1785 unsigned long flags;
1788 spin_lock_irqsave(&up->port.lock, flags);
1789 lsr = serial_in(up, UART_LSR);
1790 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1791 spin_unlock_irqrestore(&up->port.lock, flags);
1793 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1796 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1798 struct uart_8250_port *up = (struct uart_8250_port *)port;
1799 unsigned int status;
1802 status = check_modem_status(up);
1805 if (status & UART_MSR_DCD)
1807 if (status & UART_MSR_RI)
1809 if (status & UART_MSR_DSR)
1811 if (status & UART_MSR_CTS)
1816 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1818 struct uart_8250_port *up = (struct uart_8250_port *)port;
1819 unsigned char mcr = 0;
1821 if (mctrl & TIOCM_RTS)
1822 mcr |= UART_MCR_RTS;
1823 if (mctrl & TIOCM_DTR)
1824 mcr |= UART_MCR_DTR;
1825 if (mctrl & TIOCM_OUT1)
1826 mcr |= UART_MCR_OUT1;
1827 if (mctrl & TIOCM_OUT2)
1828 mcr |= UART_MCR_OUT2;
1829 if (mctrl & TIOCM_LOOP)
1830 mcr |= UART_MCR_LOOP;
1832 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1834 serial_out(up, UART_MCR, mcr);
1837 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1839 struct uart_8250_port *up = (struct uart_8250_port *)port;
1840 unsigned long flags;
1842 spin_lock_irqsave(&up->port.lock, flags);
1843 if (break_state == -1)
1844 up->lcr |= UART_LCR_SBC;
1846 up->lcr &= ~UART_LCR_SBC;
1847 serial_out(up, UART_LCR, up->lcr);
1848 spin_unlock_irqrestore(&up->port.lock, flags);
1852 * Wait for transmitter & holding register to empty
1854 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1856 unsigned int status, tmout = 10000;
1858 /* Wait up to 10ms for the character(s) to be sent. */
1860 status = serial_in(up, UART_LSR);
1862 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1864 if ((status & bits) == bits)
1871 /* Wait up to 1s for flow control if necessary */
1872 if (up->port.flags & UPF_CONS_FLOW) {
1874 for (tmout = 1000000; tmout; tmout--) {
1875 unsigned int msr = serial_in(up, UART_MSR);
1876 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1877 if (msr & UART_MSR_CTS)
1880 touch_nmi_watchdog();
1885 #ifdef CONFIG_CONSOLE_POLL
1887 * Console polling routines for writing and reading from the uart while
1888 * in an interrupt or debug context.
1891 static int serial8250_get_poll_char(struct uart_port *port)
1893 struct uart_8250_port *up = (struct uart_8250_port *)port;
1894 unsigned char lsr = serial_inp(up, UART_LSR);
1896 if (!(lsr & UART_LSR_DR))
1897 return NO_POLL_CHAR;
1899 return serial_inp(up, UART_RX);
1903 static void serial8250_put_poll_char(struct uart_port *port,
1907 struct uart_8250_port *up = (struct uart_8250_port *)port;
1910 * First save the IER then disable the interrupts
1912 ier = serial_in(up, UART_IER);
1913 if (up->capabilities & UART_CAP_UUE)
1914 serial_out(up, UART_IER, UART_IER_UUE);
1916 serial_out(up, UART_IER, 0);
1918 wait_for_xmitr(up, BOTH_EMPTY);
1920 * Send the character out.
1921 * If a LF, also do CR...
1923 serial_out(up, UART_TX, c);
1925 wait_for_xmitr(up, BOTH_EMPTY);
1926 serial_out(up, UART_TX, 13);
1930 * Finally, wait for transmitter to become empty
1931 * and restore the IER
1933 wait_for_xmitr(up, BOTH_EMPTY);
1934 serial_out(up, UART_IER, ier);
1937 #endif /* CONFIG_CONSOLE_POLL */
1939 static int serial8250_startup(struct uart_port *port)
1941 struct uart_8250_port *up = (struct uart_8250_port *)port;
1942 unsigned long flags;
1943 unsigned char lsr, iir;
1946 up->capabilities = uart_config[up->port.type].flags;
1949 if (up->port.iotype != up->cur_iotype)
1950 set_io_from_upio(port);
1952 if (up->port.type == PORT_16C950) {
1953 /* Wake up and initialize UART */
1955 serial_outp(up, UART_LCR, 0xBF);
1956 serial_outp(up, UART_EFR, UART_EFR_ECB);
1957 serial_outp(up, UART_IER, 0);
1958 serial_outp(up, UART_LCR, 0);
1959 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1960 serial_outp(up, UART_LCR, 0xBF);
1961 serial_outp(up, UART_EFR, UART_EFR_ECB);
1962 serial_outp(up, UART_LCR, 0);
1965 #ifdef CONFIG_SERIAL_8250_RSA
1967 * If this is an RSA port, see if we can kick it up to the
1968 * higher speed clock.
1974 * Clear the FIFO buffers and disable them.
1975 * (they will be reenabled in set_termios())
1977 serial8250_clear_fifos(up);
1980 * Clear the interrupt registers.
1982 (void) serial_inp(up, UART_LSR);
1983 (void) serial_inp(up, UART_RX);
1984 (void) serial_inp(up, UART_IIR);
1985 (void) serial_inp(up, UART_MSR);
1988 * At this point, there's no way the LSR could still be 0xff;
1989 * if it is, then bail out, because there's likely no UART
1992 if (!(up->port.flags & UPF_BUGGY_UART) &&
1993 (serial_inp(up, UART_LSR) == 0xff)) {
1994 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1995 serial_index(&up->port));
2000 * For a XR16C850, we need to set the trigger levels
2002 if (up->port.type == PORT_16850) {
2005 serial_outp(up, UART_LCR, 0xbf);
2007 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2008 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2009 serial_outp(up, UART_TRG, UART_TRG_96);
2010 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2011 serial_outp(up, UART_TRG, UART_TRG_96);
2013 serial_outp(up, UART_LCR, 0);
2016 if (is_real_interrupt(up->port.irq)) {
2019 * Test for UARTs that do not reassert THRE when the
2020 * transmitter is idle and the interrupt has already
2021 * been cleared. Real 16550s should always reassert
2022 * this interrupt whenever the transmitter is idle and
2023 * the interrupt is enabled. Delays are necessary to
2024 * allow register changes to become visible.
2026 spin_lock_irqsave(&up->port.lock, flags);
2027 if (up->port.irqflags & IRQF_SHARED)
2028 disable_irq_nosync(up->port.irq);
2030 wait_for_xmitr(up, UART_LSR_THRE);
2031 serial_out_sync(up, UART_IER, UART_IER_THRI);
2032 udelay(1); /* allow THRE to set */
2033 iir1 = serial_in(up, UART_IIR);
2034 serial_out(up, UART_IER, 0);
2035 serial_out_sync(up, UART_IER, UART_IER_THRI);
2036 udelay(1); /* allow a working UART time to re-assert THRE */
2037 iir = serial_in(up, UART_IIR);
2038 serial_out(up, UART_IER, 0);
2040 if (up->port.irqflags & IRQF_SHARED)
2041 enable_irq(up->port.irq);
2042 spin_unlock_irqrestore(&up->port.lock, flags);
2045 * If the interrupt is not reasserted, setup a timer to
2046 * kick the UART on a regular basis.
2048 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2049 up->bugs |= UART_BUG_THRE;
2050 pr_debug("ttyS%d - using backup timer\n",
2051 serial_index(port));
2056 * The above check will only give an accurate result the first time
2057 * the port is opened so this value needs to be preserved.
2059 if (up->bugs & UART_BUG_THRE) {
2060 up->timer.function = serial8250_backup_timeout;
2061 up->timer.data = (unsigned long)up;
2062 mod_timer(&up->timer, jiffies +
2063 uart_poll_timeout(port) + HZ / 5);
2067 * If the "interrupt" for this port doesn't correspond with any
2068 * hardware interrupt, we use a timer-based system. The original
2069 * driver used to do this with IRQ0.
2071 if (!is_real_interrupt(up->port.irq)) {
2072 up->timer.data = (unsigned long)up;
2073 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2075 retval = serial_link_irq_chain(up);
2081 * Now, initialize the UART
2083 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2085 spin_lock_irqsave(&up->port.lock, flags);
2086 if (up->port.flags & UPF_FOURPORT) {
2087 if (!is_real_interrupt(up->port.irq))
2088 up->port.mctrl |= TIOCM_OUT1;
2091 * Most PC uarts need OUT2 raised to enable interrupts.
2093 if (is_real_interrupt(up->port.irq))
2094 up->port.mctrl |= TIOCM_OUT2;
2096 serial8250_set_mctrl(&up->port, up->port.mctrl);
2098 /* Serial over Lan (SoL) hack:
2099 Intel 8257x Gigabit ethernet chips have a
2100 16550 emulation, to be used for Serial Over Lan.
2101 Those chips take a longer time than a normal
2102 serial device to signalize that a transmission
2103 data was queued. Due to that, the above test generally
2104 fails. One solution would be to delay the reading of
2105 iir. However, this is not reliable, since the timeout
2106 is variable. So, let's just don't test if we receive
2107 TX irq. This way, we'll never enable UART_BUG_TXEN.
2109 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2110 goto dont_test_tx_en;
2113 * Do a quick test to see if we receive an
2114 * interrupt when we enable the TX irq.
2116 serial_outp(up, UART_IER, UART_IER_THRI);
2117 lsr = serial_in(up, UART_LSR);
2118 iir = serial_in(up, UART_IIR);
2119 serial_outp(up, UART_IER, 0);
2121 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2122 if (!(up->bugs & UART_BUG_TXEN)) {
2123 up->bugs |= UART_BUG_TXEN;
2124 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2125 serial_index(port));
2128 up->bugs &= ~UART_BUG_TXEN;
2132 spin_unlock_irqrestore(&up->port.lock, flags);
2135 * Clear the interrupt registers again for luck, and clear the
2136 * saved flags to avoid getting false values from polling
2137 * routines or the previous session.
2139 serial_inp(up, UART_LSR);
2140 serial_inp(up, UART_RX);
2141 serial_inp(up, UART_IIR);
2142 serial_inp(up, UART_MSR);
2143 up->lsr_saved_flags = 0;
2144 up->msr_saved_flags = 0;
2147 * Finally, enable interrupts. Note: Modem status interrupts
2148 * are set via set_termios(), which will be occurring imminently
2149 * anyway, so we don't enable them here.
2151 up->ier = UART_IER_RLSI | UART_IER_RDI;
2152 serial_outp(up, UART_IER, up->ier);
2154 if (up->port.flags & UPF_FOURPORT) {
2157 * Enable interrupts on the AST Fourport board
2159 icp = (up->port.iobase & 0xfe0) | 0x01f;
2167 static void serial8250_shutdown(struct uart_port *port)
2169 struct uart_8250_port *up = (struct uart_8250_port *)port;
2170 unsigned long flags;
2173 * Disable interrupts from this port
2176 serial_outp(up, UART_IER, 0);
2178 spin_lock_irqsave(&up->port.lock, flags);
2179 if (up->port.flags & UPF_FOURPORT) {
2180 /* reset interrupts on the AST Fourport board */
2181 inb((up->port.iobase & 0xfe0) | 0x1f);
2182 up->port.mctrl |= TIOCM_OUT1;
2184 up->port.mctrl &= ~TIOCM_OUT2;
2186 serial8250_set_mctrl(&up->port, up->port.mctrl);
2187 spin_unlock_irqrestore(&up->port.lock, flags);
2190 * Disable break condition and FIFOs
2192 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2193 serial8250_clear_fifos(up);
2195 #ifdef CONFIG_SERIAL_8250_RSA
2197 * Reset the RSA board back to 115kbps compat mode.
2203 * Read data port to reset things, and then unlink from
2206 (void) serial_in(up, UART_RX);
2208 del_timer_sync(&up->timer);
2209 up->timer.function = serial8250_timeout;
2210 if (is_real_interrupt(up->port.irq))
2211 serial_unlink_irq_chain(up);
2214 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2219 * Handle magic divisors for baud rates above baud_base on
2220 * SMSC SuperIO chips.
2222 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2223 baud == (port->uartclk/4))
2225 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2226 baud == (port->uartclk/8))
2229 quot = uart_get_divisor(port, baud);
2235 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2236 struct ktermios *old)
2238 struct uart_8250_port *up = (struct uart_8250_port *)port;
2239 unsigned char cval, fcr = 0;
2240 unsigned long flags;
2241 unsigned int baud, quot;
2243 switch (termios->c_cflag & CSIZE) {
2245 cval = UART_LCR_WLEN5;
2248 cval = UART_LCR_WLEN6;
2251 cval = UART_LCR_WLEN7;
2255 cval = UART_LCR_WLEN8;
2259 if (termios->c_cflag & CSTOPB)
2260 cval |= UART_LCR_STOP;
2261 if (termios->c_cflag & PARENB)
2262 cval |= UART_LCR_PARITY;
2263 if (!(termios->c_cflag & PARODD))
2264 cval |= UART_LCR_EPAR;
2266 if (termios->c_cflag & CMSPAR)
2267 cval |= UART_LCR_SPAR;
2271 * Ask the core to calculate the divisor for us.
2273 baud = uart_get_baud_rate(port, termios, old,
2274 port->uartclk / 16 / 0xffff,
2275 port->uartclk / 16);
2276 quot = serial8250_get_divisor(port, baud);
2279 * Oxford Semi 952 rev B workaround
2281 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2284 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2286 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2288 fcr = uart_config[up->port.type].fcr;
2292 * MCR-based auto flow control. When AFE is enabled, RTS will be
2293 * deasserted when the receive FIFO contains more characters than
2294 * the trigger, or the MCR RTS bit is cleared. In the case where
2295 * the remote UART is not using CTS auto flow control, we must
2296 * have sufficient FIFO entries for the latency of the remote
2297 * UART to respond. IOW, at least 32 bytes of FIFO.
2299 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2300 up->mcr &= ~UART_MCR_AFE;
2301 if (termios->c_cflag & CRTSCTS)
2302 up->mcr |= UART_MCR_AFE;
2306 * Ok, we're now changing the port state. Do it with
2307 * interrupts disabled.
2309 spin_lock_irqsave(&up->port.lock, flags);
2312 * Update the per-port timeout.
2314 uart_update_timeout(port, termios->c_cflag, baud);
2316 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2317 if (termios->c_iflag & INPCK)
2318 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2319 if (termios->c_iflag & (BRKINT | PARMRK))
2320 up->port.read_status_mask |= UART_LSR_BI;
2323 * Characteres to ignore
2325 up->port.ignore_status_mask = 0;
2326 if (termios->c_iflag & IGNPAR)
2327 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2328 if (termios->c_iflag & IGNBRK) {
2329 up->port.ignore_status_mask |= UART_LSR_BI;
2331 * If we're ignoring parity and break indicators,
2332 * ignore overruns too (for real raw support).
2334 if (termios->c_iflag & IGNPAR)
2335 up->port.ignore_status_mask |= UART_LSR_OE;
2339 * ignore all characters if CREAD is not set
2341 if ((termios->c_cflag & CREAD) == 0)
2342 up->port.ignore_status_mask |= UART_LSR_DR;
2345 * CTS flow control flag and modem status interrupts
2346 * Only disable MSI if no threads are waiting in
2347 * serial_core::uart_wait_modem_status
2349 if (!waitqueue_active(&up->port.state->port.delta_msr_wait))
2350 up->ier &= ~UART_IER_MSI;
2351 if (!(up->bugs & UART_BUG_NOMSR) &&
2352 UART_ENABLE_MS(&up->port, termios->c_cflag))
2353 up->ier |= UART_IER_MSI;
2354 if (up->capabilities & UART_CAP_UUE)
2355 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2357 serial_out(up, UART_IER, up->ier);
2359 if (up->capabilities & UART_CAP_EFR) {
2360 unsigned char efr = 0;
2362 * TI16C752/Startech hardware flow control. FIXME:
2363 * - TI16C752 requires control thresholds to be set.
2364 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2366 if (termios->c_cflag & CRTSCTS)
2367 efr |= UART_EFR_CTS;
2369 serial_outp(up, UART_LCR, 0xBF);
2370 serial_outp(up, UART_EFR, efr);
2373 #ifdef CONFIG_ARCH_OMAP
2374 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2375 if (cpu_is_omap1510() && is_omap_port(up)) {
2376 if (baud == 115200) {
2378 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2380 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2384 if (up->capabilities & UART_NATSEMI) {
2385 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2386 serial_outp(up, UART_LCR, 0xe0);
2388 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2391 serial_dl_write(up, quot);
2394 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2395 * is written without DLAB set, this mode will be disabled.
2397 if (up->port.type == PORT_16750)
2398 serial_outp(up, UART_FCR, fcr);
2400 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2401 up->lcr = cval; /* Save LCR */
2402 if (up->port.type != PORT_16750) {
2403 if (fcr & UART_FCR_ENABLE_FIFO) {
2404 /* emulated UARTs (Lucent Venus 167x) need two steps */
2405 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2407 serial_outp(up, UART_FCR, fcr); /* set fcr */
2409 serial8250_set_mctrl(&up->port, up->port.mctrl);
2410 spin_unlock_irqrestore(&up->port.lock, flags);
2411 /* Don't rewrite B0 */
2412 if (tty_termios_baud_rate(termios))
2413 tty_termios_encode_baud_rate(termios, baud, baud);
2415 EXPORT_SYMBOL(serial8250_do_set_termios);
2418 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2419 struct ktermios *old)
2421 if (port->set_termios)
2422 port->set_termios(port, termios, old);
2424 serial8250_do_set_termios(port, termios, old);
2428 serial8250_set_ldisc(struct uart_port *port, int new)
2431 port->flags |= UPF_HARDPPS_CD;
2432 serial8250_enable_ms(port);
2434 port->flags &= ~UPF_HARDPPS_CD;
2438 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2439 unsigned int oldstate)
2441 struct uart_8250_port *p = (struct uart_8250_port *)port;
2443 serial8250_set_sleep(p, state != 0);
2445 EXPORT_SYMBOL(serial8250_do_pm);
2448 serial8250_pm(struct uart_port *port, unsigned int state,
2449 unsigned int oldstate)
2452 port->pm(port, state, oldstate);
2454 serial8250_do_pm(port, state, oldstate);
2457 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2459 if (pt->port.iotype == UPIO_AU)
2461 #ifdef CONFIG_ARCH_OMAP
2462 if (is_omap_port(pt))
2463 return 0x16 << pt->port.regshift;
2465 return 8 << pt->port.regshift;
2469 * Resource handling.
2471 static int serial8250_request_std_resource(struct uart_8250_port *up)
2473 unsigned int size = serial8250_port_size(up);
2476 switch (up->port.iotype) {
2482 if (!up->port.mapbase)
2485 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2490 if (up->port.flags & UPF_IOREMAP) {
2491 up->port.membase = ioremap_nocache(up->port.mapbase,
2493 if (!up->port.membase) {
2494 release_mem_region(up->port.mapbase, size);
2502 if (!request_region(up->port.iobase, size, "serial"))
2509 static void serial8250_release_std_resource(struct uart_8250_port *up)
2511 unsigned int size = serial8250_port_size(up);
2513 switch (up->port.iotype) {
2519 if (!up->port.mapbase)
2522 if (up->port.flags & UPF_IOREMAP) {
2523 iounmap(up->port.membase);
2524 up->port.membase = NULL;
2527 release_mem_region(up->port.mapbase, size);
2532 release_region(up->port.iobase, size);
2537 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2539 unsigned long start = UART_RSA_BASE << up->port.regshift;
2540 unsigned int size = 8 << up->port.regshift;
2543 switch (up->port.iotype) {
2546 start += up->port.iobase;
2547 if (request_region(start, size, "serial-rsa"))
2557 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2559 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2560 unsigned int size = 8 << up->port.regshift;
2562 switch (up->port.iotype) {
2565 release_region(up->port.iobase + offset, size);
2570 static void serial8250_release_port(struct uart_port *port)
2572 struct uart_8250_port *up = (struct uart_8250_port *)port;
2574 serial8250_release_std_resource(up);
2575 if (up->port.type == PORT_RSA)
2576 serial8250_release_rsa_resource(up);
2579 static int serial8250_request_port(struct uart_port *port)
2581 struct uart_8250_port *up = (struct uart_8250_port *)port;
2584 ret = serial8250_request_std_resource(up);
2585 if (ret == 0 && up->port.type == PORT_RSA) {
2586 ret = serial8250_request_rsa_resource(up);
2588 serial8250_release_std_resource(up);
2594 static void serial8250_config_port(struct uart_port *port, int flags)
2596 struct uart_8250_port *up = (struct uart_8250_port *)port;
2597 int probeflags = PROBE_ANY;
2601 * Find the region that we can probe for. This in turn
2602 * tells us whether we can probe for the type of port.
2604 ret = serial8250_request_std_resource(up);
2608 ret = serial8250_request_rsa_resource(up);
2610 probeflags &= ~PROBE_RSA;
2612 if (up->port.iotype != up->cur_iotype)
2613 set_io_from_upio(port);
2615 if (flags & UART_CONFIG_TYPE)
2616 autoconfig(up, probeflags);
2618 /* if access method is AU, it is a 16550 with a quirk */
2619 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2620 up->bugs |= UART_BUG_NOMSR;
2622 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2625 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2626 serial8250_release_rsa_resource(up);
2627 if (up->port.type == PORT_UNKNOWN)
2628 serial8250_release_std_resource(up);
2632 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2634 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2635 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2636 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2637 ser->type == PORT_STARTECH)
2643 serial8250_type(struct uart_port *port)
2645 int type = port->type;
2647 if (type >= ARRAY_SIZE(uart_config))
2649 return uart_config[type].name;
2652 static struct uart_ops serial8250_pops = {
2653 .tx_empty = serial8250_tx_empty,
2654 .set_mctrl = serial8250_set_mctrl,
2655 .get_mctrl = serial8250_get_mctrl,
2656 .stop_tx = serial8250_stop_tx,
2657 .start_tx = serial8250_start_tx,
2658 .stop_rx = serial8250_stop_rx,
2659 .enable_ms = serial8250_enable_ms,
2660 .break_ctl = serial8250_break_ctl,
2661 .startup = serial8250_startup,
2662 .shutdown = serial8250_shutdown,
2663 .set_termios = serial8250_set_termios,
2664 .set_ldisc = serial8250_set_ldisc,
2665 .pm = serial8250_pm,
2666 .type = serial8250_type,
2667 .release_port = serial8250_release_port,
2668 .request_port = serial8250_request_port,
2669 .config_port = serial8250_config_port,
2670 .verify_port = serial8250_verify_port,
2671 #ifdef CONFIG_CONSOLE_POLL
2672 .poll_get_char = serial8250_get_poll_char,
2673 .poll_put_char = serial8250_put_poll_char,
2677 static struct uart_8250_port serial8250_ports[UART_NR];
2679 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2680 unsigned short *capabilities);
2682 void serial8250_set_isa_configurator(
2683 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2685 serial8250_isa_config = v;
2687 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2689 static void __init serial8250_isa_init_ports(void)
2691 struct uart_8250_port *up;
2692 static int first = 1;
2699 for (i = 0; i < nr_uarts; i++) {
2700 struct uart_8250_port *up = &serial8250_ports[i];
2703 spin_lock_init(&up->port.lock);
2705 init_timer(&up->timer);
2706 up->timer.function = serial8250_timeout;
2709 * ALPHA_KLUDGE_MCR needs to be killed.
2711 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2712 up->mcr_force = ALPHA_KLUDGE_MCR;
2714 up->port.ops = &serial8250_pops;
2718 irqflag = IRQF_SHARED;
2720 for (i = 0, up = serial8250_ports;
2721 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2723 up->port.iobase = old_serial_port[i].port;
2724 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2725 up->port.irqflags = old_serial_port[i].irqflags;
2726 up->port.uartclk = old_serial_port[i].baud_base * 16;
2727 up->port.flags = old_serial_port[i].flags;
2728 up->port.hub6 = old_serial_port[i].hub6;
2729 up->port.membase = old_serial_port[i].iomem_base;
2730 up->port.iotype = old_serial_port[i].io_type;
2731 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2732 set_io_from_upio(&up->port);
2733 up->port.irqflags |= irqflag;
2734 if (serial8250_isa_config != NULL)
2735 serial8250_isa_config(i, &up->port, &up->capabilities);
2741 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2743 up->port.type = type;
2744 up->port.fifosize = uart_config[type].fifo_size;
2745 up->capabilities = uart_config[type].flags;
2746 up->tx_loadsz = uart_config[type].tx_loadsz;
2750 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2754 for (i = 0; i < nr_uarts; i++) {
2755 struct uart_8250_port *up = &serial8250_ports[i];
2756 up->cur_iotype = 0xFF;
2759 serial8250_isa_init_ports();
2761 for (i = 0; i < nr_uarts; i++) {
2762 struct uart_8250_port *up = &serial8250_ports[i];
2766 if (up->port.flags & UPF_FIXED_TYPE)
2767 serial8250_init_fixed_type_port(up, up->port.type);
2769 uart_add_one_port(drv, &up->port);
2773 #ifdef CONFIG_SERIAL_8250_CONSOLE
2775 static void serial8250_console_putchar(struct uart_port *port, int ch)
2777 struct uart_8250_port *up = (struct uart_8250_port *)port;
2779 wait_for_xmitr(up, UART_LSR_THRE);
2780 serial_out(up, UART_TX, ch);
2784 * Print a string to the serial port trying not to disturb
2785 * any possible real use of the port...
2787 * The console_lock must be held when we get here.
2790 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2792 struct uart_8250_port *up = &serial8250_ports[co->index];
2793 unsigned long flags;
2797 touch_nmi_watchdog();
2799 local_irq_save(flags);
2800 if (up->port.sysrq) {
2801 /* serial8250_handle_port() already took the lock */
2803 } else if (oops_in_progress) {
2804 locked = spin_trylock(&up->port.lock);
2806 spin_lock(&up->port.lock);
2809 * First save the IER then disable the interrupts
2811 ier = serial_in(up, UART_IER);
2813 if (up->capabilities & UART_CAP_UUE)
2814 serial_out(up, UART_IER, UART_IER_UUE);
2816 serial_out(up, UART_IER, 0);
2818 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2821 * Finally, wait for transmitter to become empty
2822 * and restore the IER
2824 wait_for_xmitr(up, BOTH_EMPTY);
2825 serial_out(up, UART_IER, ier);
2828 * The receive handling will happen properly because the
2829 * receive ready bit will still be set; it is not cleared
2830 * on read. However, modem control will not, we must
2831 * call it if we have saved something in the saved flags
2832 * while processing with interrupts off.
2834 if (up->msr_saved_flags)
2835 check_modem_status(up);
2838 spin_unlock(&up->port.lock);
2839 local_irq_restore(flags);
2842 static int __init serial8250_console_setup(struct console *co, char *options)
2844 struct uart_port *port;
2851 * Check whether an invalid uart number has been specified, and
2852 * if so, search for the first available port that does have
2855 if (co->index >= nr_uarts)
2857 port = &serial8250_ports[co->index].port;
2858 if (!port->iobase && !port->membase)
2862 uart_parse_options(options, &baud, &parity, &bits, &flow);
2864 return uart_set_options(port, co, baud, parity, bits, flow);
2867 static int serial8250_console_early_setup(void)
2869 return serial8250_find_port_for_earlycon();
2872 static struct console serial8250_console = {
2874 .write = serial8250_console_write,
2875 .device = uart_console_device,
2876 .setup = serial8250_console_setup,
2877 .early_setup = serial8250_console_early_setup,
2878 .flags = CON_PRINTBUFFER,
2880 .data = &serial8250_reg,
2883 static int __init serial8250_console_init(void)
2885 if (nr_uarts > UART_NR)
2888 serial8250_isa_init_ports();
2889 register_console(&serial8250_console);
2892 console_initcall(serial8250_console_init);
2894 int serial8250_find_port(struct uart_port *p)
2897 struct uart_port *port;
2899 for (line = 0; line < nr_uarts; line++) {
2900 port = &serial8250_ports[line].port;
2901 if (uart_match_port(p, port))
2907 #define SERIAL8250_CONSOLE &serial8250_console
2909 #define SERIAL8250_CONSOLE NULL
2912 static struct uart_driver serial8250_reg = {
2913 .owner = THIS_MODULE,
2914 .driver_name = "serial",
2918 .cons = SERIAL8250_CONSOLE,
2922 * early_serial_setup - early registration for 8250 ports
2924 * Setup an 8250 port structure prior to console initialisation. Use
2925 * after console initialisation will cause undefined behaviour.
2927 int __init early_serial_setup(struct uart_port *port)
2929 struct uart_port *p;
2931 if (port->line >= ARRAY_SIZE(serial8250_ports))
2934 serial8250_isa_init_ports();
2935 p = &serial8250_ports[port->line].port;
2936 p->iobase = port->iobase;
2937 p->membase = port->membase;
2939 p->irqflags = port->irqflags;
2940 p->uartclk = port->uartclk;
2941 p->fifosize = port->fifosize;
2942 p->regshift = port->regshift;
2943 p->iotype = port->iotype;
2944 p->flags = port->flags;
2945 p->mapbase = port->mapbase;
2946 p->private_data = port->private_data;
2947 p->type = port->type;
2948 p->line = port->line;
2950 set_io_from_upio(p);
2951 if (port->serial_in)
2952 p->serial_in = port->serial_in;
2953 if (port->serial_out)
2954 p->serial_out = port->serial_out;
2960 * serial8250_suspend_port - suspend one serial port
2961 * @line: serial line number
2963 * Suspend one serial port.
2965 void serial8250_suspend_port(int line)
2967 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2971 * serial8250_resume_port - resume one serial port
2972 * @line: serial line number
2974 * Resume one serial port.
2976 void serial8250_resume_port(int line)
2978 struct uart_8250_port *up = &serial8250_ports[line];
2980 if (up->capabilities & UART_NATSEMI) {
2983 /* Ensure it's still in high speed mode */
2984 serial_outp(up, UART_LCR, 0xE0);
2986 tmp = serial_in(up, 0x04); /* EXCR2 */
2987 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2988 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2989 serial_outp(up, 0x04, tmp);
2991 serial_outp(up, UART_LCR, 0);
2993 uart_resume_port(&serial8250_reg, &up->port);
2997 * Register a set of serial devices attached to a platform device. The
2998 * list is terminated with a zero flags entry, which means we expect
2999 * all entries to have at least UPF_BOOT_AUTOCONF set.
3001 static int __devinit serial8250_probe(struct platform_device *dev)
3003 struct plat_serial8250_port *p = dev->dev.platform_data;
3004 struct uart_port port;
3005 int ret, i, irqflag = 0;
3007 memset(&port, 0, sizeof(struct uart_port));
3010 irqflag = IRQF_SHARED;
3012 for (i = 0; p && p->flags != 0; p++, i++) {
3013 port.iobase = p->iobase;
3014 port.membase = p->membase;
3016 port.irqflags = p->irqflags;
3017 port.uartclk = p->uartclk;
3018 port.regshift = p->regshift;
3019 port.iotype = p->iotype;
3020 port.flags = p->flags;
3021 port.mapbase = p->mapbase;
3022 port.hub6 = p->hub6;
3023 port.private_data = p->private_data;
3024 port.type = p->type;
3025 port.serial_in = p->serial_in;
3026 port.serial_out = p->serial_out;
3027 port.set_termios = p->set_termios;
3029 port.dev = &dev->dev;
3030 port.irqflags |= irqflag;
3031 ret = serial8250_register_port(&port);
3033 dev_err(&dev->dev, "unable to register port at index %d "
3034 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3035 p->iobase, (unsigned long long)p->mapbase,
3043 * Remove serial ports registered against a platform device.
3045 static int __devexit serial8250_remove(struct platform_device *dev)
3049 for (i = 0; i < nr_uarts; i++) {
3050 struct uart_8250_port *up = &serial8250_ports[i];
3052 if (up->port.dev == &dev->dev)
3053 serial8250_unregister_port(i);
3058 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3062 for (i = 0; i < UART_NR; i++) {
3063 struct uart_8250_port *up = &serial8250_ports[i];
3065 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3066 uart_suspend_port(&serial8250_reg, &up->port);
3072 static int serial8250_resume(struct platform_device *dev)
3076 for (i = 0; i < UART_NR; i++) {
3077 struct uart_8250_port *up = &serial8250_ports[i];
3079 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3080 serial8250_resume_port(i);
3086 static struct platform_driver serial8250_isa_driver = {
3087 .probe = serial8250_probe,
3088 .remove = __devexit_p(serial8250_remove),
3089 .suspend = serial8250_suspend,
3090 .resume = serial8250_resume,
3092 .name = "serial8250",
3093 .owner = THIS_MODULE,
3098 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3099 * in the table in include/asm/serial.h
3101 static struct platform_device *serial8250_isa_devs;
3104 * serial8250_register_port and serial8250_unregister_port allows for
3105 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3106 * modems and PCI multiport cards.
3108 static DEFINE_MUTEX(serial_mutex);
3110 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3115 * First, find a port entry which matches.
3117 for (i = 0; i < nr_uarts; i++)
3118 if (uart_match_port(&serial8250_ports[i].port, port))
3119 return &serial8250_ports[i];
3122 * We didn't find a matching entry, so look for the first
3123 * free entry. We look for one which hasn't been previously
3124 * used (indicated by zero iobase).
3126 for (i = 0; i < nr_uarts; i++)
3127 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3128 serial8250_ports[i].port.iobase == 0)
3129 return &serial8250_ports[i];
3132 * That also failed. Last resort is to find any entry which
3133 * doesn't have a real port associated with it.
3135 for (i = 0; i < nr_uarts; i++)
3136 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3137 return &serial8250_ports[i];
3143 * serial8250_register_port - register a serial port
3144 * @port: serial port template
3146 * Configure the serial port specified by the request. If the
3147 * port exists and is in use, it is hung up and unregistered
3150 * The port is then probed and if necessary the IRQ is autodetected
3151 * If this fails an error is returned.
3153 * On success the port is ready to use and the line number is returned.
3155 int serial8250_register_port(struct uart_port *port)
3157 struct uart_8250_port *uart;
3160 if (port->uartclk == 0)
3163 mutex_lock(&serial_mutex);
3165 uart = serial8250_find_match_or_unused(port);
3167 uart_remove_one_port(&serial8250_reg, &uart->port);
3169 uart->port.iobase = port->iobase;
3170 uart->port.membase = port->membase;
3171 uart->port.irq = port->irq;
3172 uart->port.irqflags = port->irqflags;
3173 uart->port.uartclk = port->uartclk;
3174 uart->port.fifosize = port->fifosize;
3175 uart->port.regshift = port->regshift;
3176 uart->port.iotype = port->iotype;
3177 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3178 uart->port.mapbase = port->mapbase;
3179 uart->port.private_data = port->private_data;
3181 uart->port.dev = port->dev;
3183 if (port->flags & UPF_FIXED_TYPE)
3184 serial8250_init_fixed_type_port(uart, port->type);
3186 set_io_from_upio(&uart->port);
3187 /* Possibly override default I/O functions. */
3188 if (port->serial_in)
3189 uart->port.serial_in = port->serial_in;
3190 if (port->serial_out)
3191 uart->port.serial_out = port->serial_out;
3192 /* Possibly override set_termios call */
3193 if (port->set_termios)
3194 uart->port.set_termios = port->set_termios;
3196 uart->port.pm = port->pm;
3198 if (serial8250_isa_config != NULL)
3199 serial8250_isa_config(0, &uart->port,
3200 &uart->capabilities);
3202 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3204 ret = uart->port.line;
3206 mutex_unlock(&serial_mutex);
3210 EXPORT_SYMBOL(serial8250_register_port);
3213 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3214 * @line: serial line number
3216 * Remove one serial port. This may not be called from interrupt
3217 * context. We hand the port back to the our control.
3219 void serial8250_unregister_port(int line)
3221 struct uart_8250_port *uart = &serial8250_ports[line];
3223 mutex_lock(&serial_mutex);
3224 uart_remove_one_port(&serial8250_reg, &uart->port);
3225 if (serial8250_isa_devs) {
3226 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3227 uart->port.type = PORT_UNKNOWN;
3228 uart->port.dev = &serial8250_isa_devs->dev;
3229 uart_add_one_port(&serial8250_reg, &uart->port);
3231 uart->port.dev = NULL;
3233 mutex_unlock(&serial_mutex);
3235 EXPORT_SYMBOL(serial8250_unregister_port);
3237 static int __init serial8250_init(void)
3241 if (nr_uarts > UART_NR)
3244 printk(KERN_INFO "Serial: 8250/16550 driver, "
3245 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3246 share_irqs ? "en" : "dis");
3249 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3251 serial8250_reg.nr = UART_NR;
3252 ret = uart_register_driver(&serial8250_reg);
3257 serial8250_isa_devs = platform_device_alloc("serial8250",
3258 PLAT8250_DEV_LEGACY);
3259 if (!serial8250_isa_devs) {
3261 goto unreg_uart_drv;
3264 ret = platform_device_add(serial8250_isa_devs);
3268 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3270 ret = platform_driver_register(&serial8250_isa_driver);
3274 platform_device_del(serial8250_isa_devs);
3276 platform_device_put(serial8250_isa_devs);
3279 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3281 uart_unregister_driver(&serial8250_reg);
3287 static void __exit serial8250_exit(void)
3289 struct platform_device *isa_dev = serial8250_isa_devs;
3292 * This tells serial8250_unregister_port() not to re-register
3293 * the ports (thereby making serial8250_isa_driver permanently
3296 serial8250_isa_devs = NULL;
3298 platform_driver_unregister(&serial8250_isa_driver);
3299 platform_device_unregister(isa_dev);
3302 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3304 uart_unregister_driver(&serial8250_reg);
3308 module_init(serial8250_init);
3309 module_exit(serial8250_exit);
3311 EXPORT_SYMBOL(serial8250_suspend_port);
3312 EXPORT_SYMBOL(serial8250_resume_port);
3314 MODULE_LICENSE("GPL");
3315 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3317 module_param(share_irqs, uint, 0644);
3318 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3321 module_param(nr_uarts, uint, 0644);
3322 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3324 module_param(skip_txen_test, uint, 0644);
3325 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3327 #ifdef CONFIG_SERIAL_8250_RSA
3328 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3329 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3331 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);