2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
11 * Driver debug definitions.
13 /* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */
14 /* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */
15 /* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */
16 /* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */
17 /* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */
18 /* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */
19 /* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */
20 /* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */
21 /* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */
22 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
23 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
24 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
25 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
26 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
27 /* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
28 /* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */
29 /* #define QL_DEBUG_LEVEL_17 */ /* Output EEH trace messages */
30 /* #define QL_DEBUG_LEVEL_18 */ /* Output T10 CRC trace messages */
32 /* #define QL_PRINTK_BUF */ /* Captures printk to buffer */
35 * Macros use for debugging the driver.
38 #define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0)
40 #if defined(QL_DEBUG_LEVEL_1)
41 #define DEBUG1(x) do {x;} while (0)
43 #define DEBUG1(x) do {} while (0)
46 #define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0)
47 #define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0)
48 #define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
49 #define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0)
50 #define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
51 #define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0)
52 #define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0)
53 #define DEBUG2_17(x) do { if (ql2xextended_error_logging) { x; } } while (0)
55 #if defined(QL_DEBUG_LEVEL_3)
56 #define DEBUG3(x) do {x;} while (0)
57 #define DEBUG3_11(x) do {x;} while (0)
59 #define DEBUG3(x) do {} while (0)
62 #if defined(QL_DEBUG_LEVEL_4)
63 #define DEBUG4(x) do {x;} while (0)
65 #define DEBUG4(x) do {} while (0)
68 #if defined(QL_DEBUG_LEVEL_5)
69 #define DEBUG5(x) do {x;} while (0)
71 #define DEBUG5(x) do {} while (0)
74 #if defined(QL_DEBUG_LEVEL_7)
75 #define DEBUG7(x) do {x;} while (0)
77 #define DEBUG7(x) do {} while (0)
80 #if defined(QL_DEBUG_LEVEL_9)
81 #define DEBUG9(x) do {x;} while (0)
82 #define DEBUG9_10(x) do {x;} while (0)
84 #define DEBUG9(x) do {} while (0)
87 #if defined(QL_DEBUG_LEVEL_10)
88 #define DEBUG10(x) do {x;} while (0)
89 #define DEBUG9_10(x) do {x;} while (0)
91 #define DEBUG10(x) do {} while (0)
92 #if !defined(DEBUG9_10)
93 #define DEBUG9_10(x) do {} while (0)
97 #if defined(QL_DEBUG_LEVEL_11)
98 #define DEBUG11(x) do{x;} while(0)
99 #if !defined(DEBUG3_11)
100 #define DEBUG3_11(x) do{x;} while(0)
103 #define DEBUG11(x) do{} while(0)
104 #if !defined(QL_DEBUG_LEVEL_3)
105 #define DEBUG3_11(x) do{} while(0)
109 #if defined(QL_DEBUG_LEVEL_12)
110 #define DEBUG12(x) do {x;} while (0)
112 #define DEBUG12(x) do {} while (0)
115 #if defined(QL_DEBUG_LEVEL_13)
116 #define DEBUG13(x) do {x;} while (0)
118 #define DEBUG13(x) do {} while (0)
121 #if defined(QL_DEBUG_LEVEL_14)
122 #define DEBUG14(x) do {x;} while (0)
124 #define DEBUG14(x) do {} while (0)
127 #if defined(QL_DEBUG_LEVEL_15)
128 #define DEBUG15(x) do {x;} while (0)
130 #define DEBUG15(x) do {} while (0)
133 #if defined(QL_DEBUG_LEVEL_16)
134 #define DEBUG16(x) do {x;} while (0)
136 #define DEBUG16(x) do {} while (0)
139 #if defined(QL_DEBUG_LEVEL_17)
140 #define DEBUG17(x) do {x;} while (0)
142 #define DEBUG17(x) do {} while (0)
145 #if defined(QL_DEBUG_LEVEL_18)
146 #define DEBUG18(x) do {if (ql2xextended_error_logging) x; } while (0)
148 #define DEBUG18(x) do {} while (0)
153 * Firmware Dump structure definition
156 struct qla2300_fw_dump {
158 uint16_t pbiu_reg[8];
159 uint16_t risc_host_reg[8];
160 uint16_t mailbox_reg[32];
161 uint16_t resp_dma_reg[32];
162 uint16_t dma_reg[48];
163 uint16_t risc_hdw_reg[16];
164 uint16_t risc_gp0_reg[16];
165 uint16_t risc_gp1_reg[16];
166 uint16_t risc_gp2_reg[16];
167 uint16_t risc_gp3_reg[16];
168 uint16_t risc_gp4_reg[16];
169 uint16_t risc_gp5_reg[16];
170 uint16_t risc_gp6_reg[16];
171 uint16_t risc_gp7_reg[16];
172 uint16_t frame_buf_hdw_reg[64];
173 uint16_t fpm_b0_reg[64];
174 uint16_t fpm_b1_reg[64];
175 uint16_t risc_ram[0xf800];
176 uint16_t stack_ram[0x1000];
177 uint16_t data_ram[1];
180 struct qla2100_fw_dump {
182 uint16_t pbiu_reg[8];
183 uint16_t mailbox_reg[32];
184 uint16_t dma_reg[48];
185 uint16_t risc_hdw_reg[16];
186 uint16_t risc_gp0_reg[16];
187 uint16_t risc_gp1_reg[16];
188 uint16_t risc_gp2_reg[16];
189 uint16_t risc_gp3_reg[16];
190 uint16_t risc_gp4_reg[16];
191 uint16_t risc_gp5_reg[16];
192 uint16_t risc_gp6_reg[16];
193 uint16_t risc_gp7_reg[16];
194 uint16_t frame_buf_hdw_reg[16];
195 uint16_t fpm_b0_reg[64];
196 uint16_t fpm_b1_reg[64];
197 uint16_t risc_ram[0xf000];
200 struct qla24xx_fw_dump {
201 uint32_t host_status;
202 uint32_t host_reg[32];
203 uint32_t shadow_reg[7];
204 uint16_t mailbox_reg[32];
205 uint32_t xseq_gp_reg[128];
206 uint32_t xseq_0_reg[16];
207 uint32_t xseq_1_reg[16];
208 uint32_t rseq_gp_reg[128];
209 uint32_t rseq_0_reg[16];
210 uint32_t rseq_1_reg[16];
211 uint32_t rseq_2_reg[16];
212 uint32_t cmd_dma_reg[16];
213 uint32_t req0_dma_reg[15];
214 uint32_t resp0_dma_reg[15];
215 uint32_t req1_dma_reg[15];
216 uint32_t xmt0_dma_reg[32];
217 uint32_t xmt1_dma_reg[32];
218 uint32_t xmt2_dma_reg[32];
219 uint32_t xmt3_dma_reg[32];
220 uint32_t xmt4_dma_reg[32];
221 uint32_t xmt_data_dma_reg[16];
222 uint32_t rcvt0_data_dma_reg[32];
223 uint32_t rcvt1_data_dma_reg[32];
224 uint32_t risc_gp_reg[128];
225 uint32_t lmc_reg[112];
226 uint32_t fpm_hdw_reg[192];
227 uint32_t fb_hdw_reg[176];
228 uint32_t code_ram[0x2000];
232 struct qla25xx_fw_dump {
233 uint32_t host_status;
234 uint32_t host_risc_reg[32];
235 uint32_t pcie_regs[4];
236 uint32_t host_reg[32];
237 uint32_t shadow_reg[11];
238 uint32_t risc_io_reg;
239 uint16_t mailbox_reg[32];
240 uint32_t xseq_gp_reg[128];
241 uint32_t xseq_0_reg[48];
242 uint32_t xseq_1_reg[16];
243 uint32_t rseq_gp_reg[128];
244 uint32_t rseq_0_reg[32];
245 uint32_t rseq_1_reg[16];
246 uint32_t rseq_2_reg[16];
247 uint32_t aseq_gp_reg[128];
248 uint32_t aseq_0_reg[32];
249 uint32_t aseq_1_reg[16];
250 uint32_t aseq_2_reg[16];
251 uint32_t cmd_dma_reg[16];
252 uint32_t req0_dma_reg[15];
253 uint32_t resp0_dma_reg[15];
254 uint32_t req1_dma_reg[15];
255 uint32_t xmt0_dma_reg[32];
256 uint32_t xmt1_dma_reg[32];
257 uint32_t xmt2_dma_reg[32];
258 uint32_t xmt3_dma_reg[32];
259 uint32_t xmt4_dma_reg[32];
260 uint32_t xmt_data_dma_reg[16];
261 uint32_t rcvt0_data_dma_reg[32];
262 uint32_t rcvt1_data_dma_reg[32];
263 uint32_t risc_gp_reg[128];
264 uint32_t lmc_reg[128];
265 uint32_t fpm_hdw_reg[192];
266 uint32_t fb_hdw_reg[192];
267 uint32_t code_ram[0x2000];
271 struct qla81xx_fw_dump {
272 uint32_t host_status;
273 uint32_t host_risc_reg[32];
274 uint32_t pcie_regs[4];
275 uint32_t host_reg[32];
276 uint32_t shadow_reg[11];
277 uint32_t risc_io_reg;
278 uint16_t mailbox_reg[32];
279 uint32_t xseq_gp_reg[128];
280 uint32_t xseq_0_reg[48];
281 uint32_t xseq_1_reg[16];
282 uint32_t rseq_gp_reg[128];
283 uint32_t rseq_0_reg[32];
284 uint32_t rseq_1_reg[16];
285 uint32_t rseq_2_reg[16];
286 uint32_t aseq_gp_reg[128];
287 uint32_t aseq_0_reg[32];
288 uint32_t aseq_1_reg[16];
289 uint32_t aseq_2_reg[16];
290 uint32_t cmd_dma_reg[16];
291 uint32_t req0_dma_reg[15];
292 uint32_t resp0_dma_reg[15];
293 uint32_t req1_dma_reg[15];
294 uint32_t xmt0_dma_reg[32];
295 uint32_t xmt1_dma_reg[32];
296 uint32_t xmt2_dma_reg[32];
297 uint32_t xmt3_dma_reg[32];
298 uint32_t xmt4_dma_reg[32];
299 uint32_t xmt_data_dma_reg[16];
300 uint32_t rcvt0_data_dma_reg[32];
301 uint32_t rcvt1_data_dma_reg[32];
302 uint32_t risc_gp_reg[128];
303 uint32_t lmc_reg[128];
304 uint32_t fpm_hdw_reg[224];
305 uint32_t fb_hdw_reg[208];
306 uint32_t code_ram[0x2000];
310 #define EFT_NUM_BUFFERS 4
311 #define EFT_BYTES_PER_BUFFER 0x4000
312 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
314 #define FCE_NUM_BUFFERS 64
315 #define FCE_BYTES_PER_BUFFER 0x400
316 #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
317 #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
319 struct qla2xxx_fce_chain {
329 struct qla2xxx_mq_chain {
334 uint32_t qregs[4 * QLA_MQ_SIZE];
337 #define DUMP_CHAIN_VARIANT 0x80000000
338 #define DUMP_CHAIN_FCE 0x7FFFFAF0
339 #define DUMP_CHAIN_MQ 0x7FFFFAF1
340 #define DUMP_CHAIN_LAST 0x80000000
342 struct qla2xxx_fw_dump {
343 uint8_t signature[4];
346 uint32_t fw_major_version;
347 uint32_t fw_minor_version;
348 uint32_t fw_subminor_version;
349 uint32_t fw_attributes;
353 uint32_t subsystem_vendor;
354 uint32_t subsystem_device;
365 uint32_t header_size;
368 struct qla2100_fw_dump isp21;
369 struct qla2300_fw_dump isp23;
370 struct qla24xx_fw_dump isp24;
371 struct qla25xx_fw_dump isp25;
372 struct qla81xx_fw_dump isp81;